PicNeck  0.1
Macros
nrf52_bitfields.h File Reference

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Macros

#define AAR_INTENSET_NOTRESOLVED_Pos   (2UL)
 
#define AAR_INTENSET_NOTRESOLVED_Msk   (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos)
 
#define AAR_INTENSET_NOTRESOLVED_Disabled   (0UL)
 
#define AAR_INTENSET_NOTRESOLVED_Enabled   (1UL)
 
#define AAR_INTENSET_NOTRESOLVED_Set   (1UL)
 
#define AAR_INTENSET_RESOLVED_Pos   (1UL)
 
#define AAR_INTENSET_RESOLVED_Msk   (0x1UL << AAR_INTENSET_RESOLVED_Pos)
 
#define AAR_INTENSET_RESOLVED_Disabled   (0UL)
 
#define AAR_INTENSET_RESOLVED_Enabled   (1UL)
 
#define AAR_INTENSET_RESOLVED_Set   (1UL)
 
#define AAR_INTENSET_END_Pos   (0UL)
 
#define AAR_INTENSET_END_Msk   (0x1UL << AAR_INTENSET_END_Pos)
 
#define AAR_INTENSET_END_Disabled   (0UL)
 
#define AAR_INTENSET_END_Enabled   (1UL)
 
#define AAR_INTENSET_END_Set   (1UL)
 
#define AAR_INTENCLR_NOTRESOLVED_Pos   (2UL)
 
#define AAR_INTENCLR_NOTRESOLVED_Msk   (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos)
 
#define AAR_INTENCLR_NOTRESOLVED_Disabled   (0UL)
 
#define AAR_INTENCLR_NOTRESOLVED_Enabled   (1UL)
 
#define AAR_INTENCLR_NOTRESOLVED_Clear   (1UL)
 
#define AAR_INTENCLR_RESOLVED_Pos   (1UL)
 
#define AAR_INTENCLR_RESOLVED_Msk   (0x1UL << AAR_INTENCLR_RESOLVED_Pos)
 
#define AAR_INTENCLR_RESOLVED_Disabled   (0UL)
 
#define AAR_INTENCLR_RESOLVED_Enabled   (1UL)
 
#define AAR_INTENCLR_RESOLVED_Clear   (1UL)
 
#define AAR_INTENCLR_END_Pos   (0UL)
 
#define AAR_INTENCLR_END_Msk   (0x1UL << AAR_INTENCLR_END_Pos)
 
#define AAR_INTENCLR_END_Disabled   (0UL)
 
#define AAR_INTENCLR_END_Enabled   (1UL)
 
#define AAR_INTENCLR_END_Clear   (1UL)
 
#define AAR_STATUS_STATUS_Pos   (0UL)
 
#define AAR_STATUS_STATUS_Msk   (0xFUL << AAR_STATUS_STATUS_Pos)
 
#define AAR_ENABLE_ENABLE_Pos   (0UL)
 
#define AAR_ENABLE_ENABLE_Msk   (0x3UL << AAR_ENABLE_ENABLE_Pos)
 
#define AAR_ENABLE_ENABLE_Disabled   (0UL)
 
#define AAR_ENABLE_ENABLE_Enabled   (3UL)
 
#define AAR_NIRK_NIRK_Pos   (0UL)
 
#define AAR_NIRK_NIRK_Msk   (0x1FUL << AAR_NIRK_NIRK_Pos)
 
#define AAR_IRKPTR_IRKPTR_Pos   (0UL)
 
#define AAR_IRKPTR_IRKPTR_Msk   (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos)
 
#define AAR_ADDRPTR_ADDRPTR_Pos   (0UL)
 
#define AAR_ADDRPTR_ADDRPTR_Msk   (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos)
 
#define AAR_SCRATCHPTR_SCRATCHPTR_Pos   (0UL)
 
#define AAR_SCRATCHPTR_SCRATCHPTR_Msk   (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos)
 
#define BPROT_CONFIG0_REGION31_Pos   (31UL)
 
#define BPROT_CONFIG0_REGION31_Msk   (0x1UL << BPROT_CONFIG0_REGION31_Pos)
 
#define BPROT_CONFIG0_REGION31_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION31_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION30_Pos   (30UL)
 
#define BPROT_CONFIG0_REGION30_Msk   (0x1UL << BPROT_CONFIG0_REGION30_Pos)
 
#define BPROT_CONFIG0_REGION30_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION30_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION29_Pos   (29UL)
 
#define BPROT_CONFIG0_REGION29_Msk   (0x1UL << BPROT_CONFIG0_REGION29_Pos)
 
#define BPROT_CONFIG0_REGION29_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION29_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION28_Pos   (28UL)
 
#define BPROT_CONFIG0_REGION28_Msk   (0x1UL << BPROT_CONFIG0_REGION28_Pos)
 
#define BPROT_CONFIG0_REGION28_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION28_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION27_Pos   (27UL)
 
#define BPROT_CONFIG0_REGION27_Msk   (0x1UL << BPROT_CONFIG0_REGION27_Pos)
 
#define BPROT_CONFIG0_REGION27_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION27_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION26_Pos   (26UL)
 
#define BPROT_CONFIG0_REGION26_Msk   (0x1UL << BPROT_CONFIG0_REGION26_Pos)
 
#define BPROT_CONFIG0_REGION26_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION26_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION25_Pos   (25UL)
 
#define BPROT_CONFIG0_REGION25_Msk   (0x1UL << BPROT_CONFIG0_REGION25_Pos)
 
#define BPROT_CONFIG0_REGION25_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION25_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION24_Pos   (24UL)
 
#define BPROT_CONFIG0_REGION24_Msk   (0x1UL << BPROT_CONFIG0_REGION24_Pos)
 
#define BPROT_CONFIG0_REGION24_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION24_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION23_Pos   (23UL)
 
#define BPROT_CONFIG0_REGION23_Msk   (0x1UL << BPROT_CONFIG0_REGION23_Pos)
 
#define BPROT_CONFIG0_REGION23_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION23_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION22_Pos   (22UL)
 
#define BPROT_CONFIG0_REGION22_Msk   (0x1UL << BPROT_CONFIG0_REGION22_Pos)
 
#define BPROT_CONFIG0_REGION22_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION22_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION21_Pos   (21UL)
 
#define BPROT_CONFIG0_REGION21_Msk   (0x1UL << BPROT_CONFIG0_REGION21_Pos)
 
#define BPROT_CONFIG0_REGION21_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION21_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION20_Pos   (20UL)
 
#define BPROT_CONFIG0_REGION20_Msk   (0x1UL << BPROT_CONFIG0_REGION20_Pos)
 
#define BPROT_CONFIG0_REGION20_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION20_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION19_Pos   (19UL)
 
#define BPROT_CONFIG0_REGION19_Msk   (0x1UL << BPROT_CONFIG0_REGION19_Pos)
 
#define BPROT_CONFIG0_REGION19_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION19_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION18_Pos   (18UL)
 
#define BPROT_CONFIG0_REGION18_Msk   (0x1UL << BPROT_CONFIG0_REGION18_Pos)
 
#define BPROT_CONFIG0_REGION18_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION18_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION17_Pos   (17UL)
 
#define BPROT_CONFIG0_REGION17_Msk   (0x1UL << BPROT_CONFIG0_REGION17_Pos)
 
#define BPROT_CONFIG0_REGION17_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION17_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION16_Pos   (16UL)
 
#define BPROT_CONFIG0_REGION16_Msk   (0x1UL << BPROT_CONFIG0_REGION16_Pos)
 
#define BPROT_CONFIG0_REGION16_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION16_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION15_Pos   (15UL)
 
#define BPROT_CONFIG0_REGION15_Msk   (0x1UL << BPROT_CONFIG0_REGION15_Pos)
 
#define BPROT_CONFIG0_REGION15_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION15_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION14_Pos   (14UL)
 
#define BPROT_CONFIG0_REGION14_Msk   (0x1UL << BPROT_CONFIG0_REGION14_Pos)
 
#define BPROT_CONFIG0_REGION14_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION14_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION13_Pos   (13UL)
 
#define BPROT_CONFIG0_REGION13_Msk   (0x1UL << BPROT_CONFIG0_REGION13_Pos)
 
#define BPROT_CONFIG0_REGION13_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION13_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION12_Pos   (12UL)
 
#define BPROT_CONFIG0_REGION12_Msk   (0x1UL << BPROT_CONFIG0_REGION12_Pos)
 
#define BPROT_CONFIG0_REGION12_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION12_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION11_Pos   (11UL)
 
#define BPROT_CONFIG0_REGION11_Msk   (0x1UL << BPROT_CONFIG0_REGION11_Pos)
 
#define BPROT_CONFIG0_REGION11_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION11_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION10_Pos   (10UL)
 
#define BPROT_CONFIG0_REGION10_Msk   (0x1UL << BPROT_CONFIG0_REGION10_Pos)
 
#define BPROT_CONFIG0_REGION10_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION10_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION9_Pos   (9UL)
 
#define BPROT_CONFIG0_REGION9_Msk   (0x1UL << BPROT_CONFIG0_REGION9_Pos)
 
#define BPROT_CONFIG0_REGION9_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION9_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION8_Pos   (8UL)
 
#define BPROT_CONFIG0_REGION8_Msk   (0x1UL << BPROT_CONFIG0_REGION8_Pos)
 
#define BPROT_CONFIG0_REGION8_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION8_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION7_Pos   (7UL)
 
#define BPROT_CONFIG0_REGION7_Msk   (0x1UL << BPROT_CONFIG0_REGION7_Pos)
 
#define BPROT_CONFIG0_REGION7_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION7_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION6_Pos   (6UL)
 
#define BPROT_CONFIG0_REGION6_Msk   (0x1UL << BPROT_CONFIG0_REGION6_Pos)
 
#define BPROT_CONFIG0_REGION6_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION6_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION5_Pos   (5UL)
 
#define BPROT_CONFIG0_REGION5_Msk   (0x1UL << BPROT_CONFIG0_REGION5_Pos)
 
#define BPROT_CONFIG0_REGION5_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION5_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION4_Pos   (4UL)
 
#define BPROT_CONFIG0_REGION4_Msk   (0x1UL << BPROT_CONFIG0_REGION4_Pos)
 
#define BPROT_CONFIG0_REGION4_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION4_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION3_Pos   (3UL)
 
#define BPROT_CONFIG0_REGION3_Msk   (0x1UL << BPROT_CONFIG0_REGION3_Pos)
 
#define BPROT_CONFIG0_REGION3_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION3_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION2_Pos   (2UL)
 
#define BPROT_CONFIG0_REGION2_Msk   (0x1UL << BPROT_CONFIG0_REGION2_Pos)
 
#define BPROT_CONFIG0_REGION2_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION2_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION1_Pos   (1UL)
 
#define BPROT_CONFIG0_REGION1_Msk   (0x1UL << BPROT_CONFIG0_REGION1_Pos)
 
#define BPROT_CONFIG0_REGION1_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION1_Enabled   (1UL)
 
#define BPROT_CONFIG0_REGION0_Pos   (0UL)
 
#define BPROT_CONFIG0_REGION0_Msk   (0x1UL << BPROT_CONFIG0_REGION0_Pos)
 
#define BPROT_CONFIG0_REGION0_Disabled   (0UL)
 
#define BPROT_CONFIG0_REGION0_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION63_Pos   (31UL)
 
#define BPROT_CONFIG1_REGION63_Msk   (0x1UL << BPROT_CONFIG1_REGION63_Pos)
 
#define BPROT_CONFIG1_REGION63_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION63_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION62_Pos   (30UL)
 
#define BPROT_CONFIG1_REGION62_Msk   (0x1UL << BPROT_CONFIG1_REGION62_Pos)
 
#define BPROT_CONFIG1_REGION62_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION62_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION61_Pos   (29UL)
 
#define BPROT_CONFIG1_REGION61_Msk   (0x1UL << BPROT_CONFIG1_REGION61_Pos)
 
#define BPROT_CONFIG1_REGION61_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION61_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION60_Pos   (28UL)
 
#define BPROT_CONFIG1_REGION60_Msk   (0x1UL << BPROT_CONFIG1_REGION60_Pos)
 
#define BPROT_CONFIG1_REGION60_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION60_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION59_Pos   (27UL)
 
#define BPROT_CONFIG1_REGION59_Msk   (0x1UL << BPROT_CONFIG1_REGION59_Pos)
 
#define BPROT_CONFIG1_REGION59_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION59_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION58_Pos   (26UL)
 
#define BPROT_CONFIG1_REGION58_Msk   (0x1UL << BPROT_CONFIG1_REGION58_Pos)
 
#define BPROT_CONFIG1_REGION58_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION58_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION57_Pos   (25UL)
 
#define BPROT_CONFIG1_REGION57_Msk   (0x1UL << BPROT_CONFIG1_REGION57_Pos)
 
#define BPROT_CONFIG1_REGION57_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION57_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION56_Pos   (24UL)
 
#define BPROT_CONFIG1_REGION56_Msk   (0x1UL << BPROT_CONFIG1_REGION56_Pos)
 
#define BPROT_CONFIG1_REGION56_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION56_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION55_Pos   (23UL)
 
#define BPROT_CONFIG1_REGION55_Msk   (0x1UL << BPROT_CONFIG1_REGION55_Pos)
 
#define BPROT_CONFIG1_REGION55_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION55_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION54_Pos   (22UL)
 
#define BPROT_CONFIG1_REGION54_Msk   (0x1UL << BPROT_CONFIG1_REGION54_Pos)
 
#define BPROT_CONFIG1_REGION54_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION54_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION53_Pos   (21UL)
 
#define BPROT_CONFIG1_REGION53_Msk   (0x1UL << BPROT_CONFIG1_REGION53_Pos)
 
#define BPROT_CONFIG1_REGION53_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION53_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION52_Pos   (20UL)
 
#define BPROT_CONFIG1_REGION52_Msk   (0x1UL << BPROT_CONFIG1_REGION52_Pos)
 
#define BPROT_CONFIG1_REGION52_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION52_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION51_Pos   (19UL)
 
#define BPROT_CONFIG1_REGION51_Msk   (0x1UL << BPROT_CONFIG1_REGION51_Pos)
 
#define BPROT_CONFIG1_REGION51_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION51_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION50_Pos   (18UL)
 
#define BPROT_CONFIG1_REGION50_Msk   (0x1UL << BPROT_CONFIG1_REGION50_Pos)
 
#define BPROT_CONFIG1_REGION50_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION50_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION49_Pos   (17UL)
 
#define BPROT_CONFIG1_REGION49_Msk   (0x1UL << BPROT_CONFIG1_REGION49_Pos)
 
#define BPROT_CONFIG1_REGION49_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION49_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION48_Pos   (16UL)
 
#define BPROT_CONFIG1_REGION48_Msk   (0x1UL << BPROT_CONFIG1_REGION48_Pos)
 
#define BPROT_CONFIG1_REGION48_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION48_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION47_Pos   (15UL)
 
#define BPROT_CONFIG1_REGION47_Msk   (0x1UL << BPROT_CONFIG1_REGION47_Pos)
 
#define BPROT_CONFIG1_REGION47_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION47_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION46_Pos   (14UL)
 
#define BPROT_CONFIG1_REGION46_Msk   (0x1UL << BPROT_CONFIG1_REGION46_Pos)
 
#define BPROT_CONFIG1_REGION46_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION46_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION45_Pos   (13UL)
 
#define BPROT_CONFIG1_REGION45_Msk   (0x1UL << BPROT_CONFIG1_REGION45_Pos)
 
#define BPROT_CONFIG1_REGION45_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION45_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION44_Pos   (12UL)
 
#define BPROT_CONFIG1_REGION44_Msk   (0x1UL << BPROT_CONFIG1_REGION44_Pos)
 
#define BPROT_CONFIG1_REGION44_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION44_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION43_Pos   (11UL)
 
#define BPROT_CONFIG1_REGION43_Msk   (0x1UL << BPROT_CONFIG1_REGION43_Pos)
 
#define BPROT_CONFIG1_REGION43_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION43_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION42_Pos   (10UL)
 
#define BPROT_CONFIG1_REGION42_Msk   (0x1UL << BPROT_CONFIG1_REGION42_Pos)
 
#define BPROT_CONFIG1_REGION42_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION42_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION41_Pos   (9UL)
 
#define BPROT_CONFIG1_REGION41_Msk   (0x1UL << BPROT_CONFIG1_REGION41_Pos)
 
#define BPROT_CONFIG1_REGION41_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION41_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION40_Pos   (8UL)
 
#define BPROT_CONFIG1_REGION40_Msk   (0x1UL << BPROT_CONFIG1_REGION40_Pos)
 
#define BPROT_CONFIG1_REGION40_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION40_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION39_Pos   (7UL)
 
#define BPROT_CONFIG1_REGION39_Msk   (0x1UL << BPROT_CONFIG1_REGION39_Pos)
 
#define BPROT_CONFIG1_REGION39_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION39_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION38_Pos   (6UL)
 
#define BPROT_CONFIG1_REGION38_Msk   (0x1UL << BPROT_CONFIG1_REGION38_Pos)
 
#define BPROT_CONFIG1_REGION38_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION38_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION37_Pos   (5UL)
 
#define BPROT_CONFIG1_REGION37_Msk   (0x1UL << BPROT_CONFIG1_REGION37_Pos)
 
#define BPROT_CONFIG1_REGION37_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION37_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION36_Pos   (4UL)
 
#define BPROT_CONFIG1_REGION36_Msk   (0x1UL << BPROT_CONFIG1_REGION36_Pos)
 
#define BPROT_CONFIG1_REGION36_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION36_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION35_Pos   (3UL)
 
#define BPROT_CONFIG1_REGION35_Msk   (0x1UL << BPROT_CONFIG1_REGION35_Pos)
 
#define BPROT_CONFIG1_REGION35_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION35_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION34_Pos   (2UL)
 
#define BPROT_CONFIG1_REGION34_Msk   (0x1UL << BPROT_CONFIG1_REGION34_Pos)
 
#define BPROT_CONFIG1_REGION34_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION34_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION33_Pos   (1UL)
 
#define BPROT_CONFIG1_REGION33_Msk   (0x1UL << BPROT_CONFIG1_REGION33_Pos)
 
#define BPROT_CONFIG1_REGION33_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION33_Enabled   (1UL)
 
#define BPROT_CONFIG1_REGION32_Pos   (0UL)
 
#define BPROT_CONFIG1_REGION32_Msk   (0x1UL << BPROT_CONFIG1_REGION32_Pos)
 
#define BPROT_CONFIG1_REGION32_Disabled   (0UL)
 
#define BPROT_CONFIG1_REGION32_Enabled   (1UL)
 
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos   (0UL)
 
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk   (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos)
 
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled   (0UL)
 
#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled   (1UL)
 
#define BPROT_CONFIG2_REGION95_Pos   (31UL)
 
#define BPROT_CONFIG2_REGION95_Msk   (0x1UL << BPROT_CONFIG2_REGION95_Pos)
 
#define BPROT_CONFIG2_REGION95_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION95_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION94_Pos   (30UL)
 
#define BPROT_CONFIG2_REGION94_Msk   (0x1UL << BPROT_CONFIG2_REGION94_Pos)
 
#define BPROT_CONFIG2_REGION94_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION94_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION93_Pos   (29UL)
 
#define BPROT_CONFIG2_REGION93_Msk   (0x1UL << BPROT_CONFIG2_REGION93_Pos)
 
#define BPROT_CONFIG2_REGION93_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION93_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION92_Pos   (28UL)
 
#define BPROT_CONFIG2_REGION92_Msk   (0x1UL << BPROT_CONFIG2_REGION92_Pos)
 
#define BPROT_CONFIG2_REGION92_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION92_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION91_Pos   (27UL)
 
#define BPROT_CONFIG2_REGION91_Msk   (0x1UL << BPROT_CONFIG2_REGION91_Pos)
 
#define BPROT_CONFIG2_REGION91_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION91_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION90_Pos   (26UL)
 
#define BPROT_CONFIG2_REGION90_Msk   (0x1UL << BPROT_CONFIG2_REGION90_Pos)
 
#define BPROT_CONFIG2_REGION90_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION90_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION89_Pos   (25UL)
 
#define BPROT_CONFIG2_REGION89_Msk   (0x1UL << BPROT_CONFIG2_REGION89_Pos)
 
#define BPROT_CONFIG2_REGION89_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION89_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION88_Pos   (24UL)
 
#define BPROT_CONFIG2_REGION88_Msk   (0x1UL << BPROT_CONFIG2_REGION88_Pos)
 
#define BPROT_CONFIG2_REGION88_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION88_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION87_Pos   (23UL)
 
#define BPROT_CONFIG2_REGION87_Msk   (0x1UL << BPROT_CONFIG2_REGION87_Pos)
 
#define BPROT_CONFIG2_REGION87_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION87_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION86_Pos   (22UL)
 
#define BPROT_CONFIG2_REGION86_Msk   (0x1UL << BPROT_CONFIG2_REGION86_Pos)
 
#define BPROT_CONFIG2_REGION86_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION86_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION85_Pos   (21UL)
 
#define BPROT_CONFIG2_REGION85_Msk   (0x1UL << BPROT_CONFIG2_REGION85_Pos)
 
#define BPROT_CONFIG2_REGION85_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION85_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION84_Pos   (20UL)
 
#define BPROT_CONFIG2_REGION84_Msk   (0x1UL << BPROT_CONFIG2_REGION84_Pos)
 
#define BPROT_CONFIG2_REGION84_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION84_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION83_Pos   (19UL)
 
#define BPROT_CONFIG2_REGION83_Msk   (0x1UL << BPROT_CONFIG2_REGION83_Pos)
 
#define BPROT_CONFIG2_REGION83_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION83_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION82_Pos   (18UL)
 
#define BPROT_CONFIG2_REGION82_Msk   (0x1UL << BPROT_CONFIG2_REGION82_Pos)
 
#define BPROT_CONFIG2_REGION82_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION82_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION81_Pos   (17UL)
 
#define BPROT_CONFIG2_REGION81_Msk   (0x1UL << BPROT_CONFIG2_REGION81_Pos)
 
#define BPROT_CONFIG2_REGION81_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION81_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION80_Pos   (16UL)
 
#define BPROT_CONFIG2_REGION80_Msk   (0x1UL << BPROT_CONFIG2_REGION80_Pos)
 
#define BPROT_CONFIG2_REGION80_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION80_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION79_Pos   (15UL)
 
#define BPROT_CONFIG2_REGION79_Msk   (0x1UL << BPROT_CONFIG2_REGION79_Pos)
 
#define BPROT_CONFIG2_REGION79_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION79_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION78_Pos   (14UL)
 
#define BPROT_CONFIG2_REGION78_Msk   (0x1UL << BPROT_CONFIG2_REGION78_Pos)
 
#define BPROT_CONFIG2_REGION78_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION78_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION77_Pos   (13UL)
 
#define BPROT_CONFIG2_REGION77_Msk   (0x1UL << BPROT_CONFIG2_REGION77_Pos)
 
#define BPROT_CONFIG2_REGION77_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION77_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION76_Pos   (12UL)
 
#define BPROT_CONFIG2_REGION76_Msk   (0x1UL << BPROT_CONFIG2_REGION76_Pos)
 
#define BPROT_CONFIG2_REGION76_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION76_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION75_Pos   (11UL)
 
#define BPROT_CONFIG2_REGION75_Msk   (0x1UL << BPROT_CONFIG2_REGION75_Pos)
 
#define BPROT_CONFIG2_REGION75_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION75_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION74_Pos   (10UL)
 
#define BPROT_CONFIG2_REGION74_Msk   (0x1UL << BPROT_CONFIG2_REGION74_Pos)
 
#define BPROT_CONFIG2_REGION74_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION74_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION73_Pos   (9UL)
 
#define BPROT_CONFIG2_REGION73_Msk   (0x1UL << BPROT_CONFIG2_REGION73_Pos)
 
#define BPROT_CONFIG2_REGION73_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION73_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION72_Pos   (8UL)
 
#define BPROT_CONFIG2_REGION72_Msk   (0x1UL << BPROT_CONFIG2_REGION72_Pos)
 
#define BPROT_CONFIG2_REGION72_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION72_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION71_Pos   (7UL)
 
#define BPROT_CONFIG2_REGION71_Msk   (0x1UL << BPROT_CONFIG2_REGION71_Pos)
 
#define BPROT_CONFIG2_REGION71_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION71_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION70_Pos   (6UL)
 
#define BPROT_CONFIG2_REGION70_Msk   (0x1UL << BPROT_CONFIG2_REGION70_Pos)
 
#define BPROT_CONFIG2_REGION70_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION70_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION69_Pos   (5UL)
 
#define BPROT_CONFIG2_REGION69_Msk   (0x1UL << BPROT_CONFIG2_REGION69_Pos)
 
#define BPROT_CONFIG2_REGION69_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION69_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION68_Pos   (4UL)
 
#define BPROT_CONFIG2_REGION68_Msk   (0x1UL << BPROT_CONFIG2_REGION68_Pos)
 
#define BPROT_CONFIG2_REGION68_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION68_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION67_Pos   (3UL)
 
#define BPROT_CONFIG2_REGION67_Msk   (0x1UL << BPROT_CONFIG2_REGION67_Pos)
 
#define BPROT_CONFIG2_REGION67_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION67_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION66_Pos   (2UL)
 
#define BPROT_CONFIG2_REGION66_Msk   (0x1UL << BPROT_CONFIG2_REGION66_Pos)
 
#define BPROT_CONFIG2_REGION66_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION66_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION65_Pos   (1UL)
 
#define BPROT_CONFIG2_REGION65_Msk   (0x1UL << BPROT_CONFIG2_REGION65_Pos)
 
#define BPROT_CONFIG2_REGION65_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION65_Enabled   (1UL)
 
#define BPROT_CONFIG2_REGION64_Pos   (0UL)
 
#define BPROT_CONFIG2_REGION64_Msk   (0x1UL << BPROT_CONFIG2_REGION64_Pos)
 
#define BPROT_CONFIG2_REGION64_Disabled   (0UL)
 
#define BPROT_CONFIG2_REGION64_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION127_Pos   (31UL)
 
#define BPROT_CONFIG3_REGION127_Msk   (0x1UL << BPROT_CONFIG3_REGION127_Pos)
 
#define BPROT_CONFIG3_REGION127_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION127_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION126_Pos   (30UL)
 
#define BPROT_CONFIG3_REGION126_Msk   (0x1UL << BPROT_CONFIG3_REGION126_Pos)
 
#define BPROT_CONFIG3_REGION126_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION126_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION125_Pos   (29UL)
 
#define BPROT_CONFIG3_REGION125_Msk   (0x1UL << BPROT_CONFIG3_REGION125_Pos)
 
#define BPROT_CONFIG3_REGION125_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION125_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION124_Pos   (28UL)
 
#define BPROT_CONFIG3_REGION124_Msk   (0x1UL << BPROT_CONFIG3_REGION124_Pos)
 
#define BPROT_CONFIG3_REGION124_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION124_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION123_Pos   (27UL)
 
#define BPROT_CONFIG3_REGION123_Msk   (0x1UL << BPROT_CONFIG3_REGION123_Pos)
 
#define BPROT_CONFIG3_REGION123_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION123_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION122_Pos   (26UL)
 
#define BPROT_CONFIG3_REGION122_Msk   (0x1UL << BPROT_CONFIG3_REGION122_Pos)
 
#define BPROT_CONFIG3_REGION122_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION122_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION121_Pos   (25UL)
 
#define BPROT_CONFIG3_REGION121_Msk   (0x1UL << BPROT_CONFIG3_REGION121_Pos)
 
#define BPROT_CONFIG3_REGION121_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION121_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION120_Pos   (24UL)
 
#define BPROT_CONFIG3_REGION120_Msk   (0x1UL << BPROT_CONFIG3_REGION120_Pos)
 
#define BPROT_CONFIG3_REGION120_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION120_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION119_Pos   (23UL)
 
#define BPROT_CONFIG3_REGION119_Msk   (0x1UL << BPROT_CONFIG3_REGION119_Pos)
 
#define BPROT_CONFIG3_REGION119_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION119_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION118_Pos   (22UL)
 
#define BPROT_CONFIG3_REGION118_Msk   (0x1UL << BPROT_CONFIG3_REGION118_Pos)
 
#define BPROT_CONFIG3_REGION118_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION118_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION117_Pos   (21UL)
 
#define BPROT_CONFIG3_REGION117_Msk   (0x1UL << BPROT_CONFIG3_REGION117_Pos)
 
#define BPROT_CONFIG3_REGION117_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION117_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION116_Pos   (20UL)
 
#define BPROT_CONFIG3_REGION116_Msk   (0x1UL << BPROT_CONFIG3_REGION116_Pos)
 
#define BPROT_CONFIG3_REGION116_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION116_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION115_Pos   (19UL)
 
#define BPROT_CONFIG3_REGION115_Msk   (0x1UL << BPROT_CONFIG3_REGION115_Pos)
 
#define BPROT_CONFIG3_REGION115_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION115_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION114_Pos   (18UL)
 
#define BPROT_CONFIG3_REGION114_Msk   (0x1UL << BPROT_CONFIG3_REGION114_Pos)
 
#define BPROT_CONFIG3_REGION114_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION114_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION113_Pos   (17UL)
 
#define BPROT_CONFIG3_REGION113_Msk   (0x1UL << BPROT_CONFIG3_REGION113_Pos)
 
#define BPROT_CONFIG3_REGION113_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION113_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION112_Pos   (16UL)
 
#define BPROT_CONFIG3_REGION112_Msk   (0x1UL << BPROT_CONFIG3_REGION112_Pos)
 
#define BPROT_CONFIG3_REGION112_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION112_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION111_Pos   (15UL)
 
#define BPROT_CONFIG3_REGION111_Msk   (0x1UL << BPROT_CONFIG3_REGION111_Pos)
 
#define BPROT_CONFIG3_REGION111_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION111_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION110_Pos   (14UL)
 
#define BPROT_CONFIG3_REGION110_Msk   (0x1UL << BPROT_CONFIG3_REGION110_Pos)
 
#define BPROT_CONFIG3_REGION110_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION110_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION109_Pos   (13UL)
 
#define BPROT_CONFIG3_REGION109_Msk   (0x1UL << BPROT_CONFIG3_REGION109_Pos)
 
#define BPROT_CONFIG3_REGION109_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION109_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION108_Pos   (12UL)
 
#define BPROT_CONFIG3_REGION108_Msk   (0x1UL << BPROT_CONFIG3_REGION108_Pos)
 
#define BPROT_CONFIG3_REGION108_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION108_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION107_Pos   (11UL)
 
#define BPROT_CONFIG3_REGION107_Msk   (0x1UL << BPROT_CONFIG3_REGION107_Pos)
 
#define BPROT_CONFIG3_REGION107_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION107_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION106_Pos   (10UL)
 
#define BPROT_CONFIG3_REGION106_Msk   (0x1UL << BPROT_CONFIG3_REGION106_Pos)
 
#define BPROT_CONFIG3_REGION106_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION106_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION105_Pos   (9UL)
 
#define BPROT_CONFIG3_REGION105_Msk   (0x1UL << BPROT_CONFIG3_REGION105_Pos)
 
#define BPROT_CONFIG3_REGION105_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION105_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION104_Pos   (8UL)
 
#define BPROT_CONFIG3_REGION104_Msk   (0x1UL << BPROT_CONFIG3_REGION104_Pos)
 
#define BPROT_CONFIG3_REGION104_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION104_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION103_Pos   (7UL)
 
#define BPROT_CONFIG3_REGION103_Msk   (0x1UL << BPROT_CONFIG3_REGION103_Pos)
 
#define BPROT_CONFIG3_REGION103_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION103_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION102_Pos   (6UL)
 
#define BPROT_CONFIG3_REGION102_Msk   (0x1UL << BPROT_CONFIG3_REGION102_Pos)
 
#define BPROT_CONFIG3_REGION102_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION102_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION101_Pos   (5UL)
 
#define BPROT_CONFIG3_REGION101_Msk   (0x1UL << BPROT_CONFIG3_REGION101_Pos)
 
#define BPROT_CONFIG3_REGION101_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION101_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION100_Pos   (4UL)
 
#define BPROT_CONFIG3_REGION100_Msk   (0x1UL << BPROT_CONFIG3_REGION100_Pos)
 
#define BPROT_CONFIG3_REGION100_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION100_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION99_Pos   (3UL)
 
#define BPROT_CONFIG3_REGION99_Msk   (0x1UL << BPROT_CONFIG3_REGION99_Pos)
 
#define BPROT_CONFIG3_REGION99_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION99_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION98_Pos   (2UL)
 
#define BPROT_CONFIG3_REGION98_Msk   (0x1UL << BPROT_CONFIG3_REGION98_Pos)
 
#define BPROT_CONFIG3_REGION98_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION98_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION97_Pos   (1UL)
 
#define BPROT_CONFIG3_REGION97_Msk   (0x1UL << BPROT_CONFIG3_REGION97_Pos)
 
#define BPROT_CONFIG3_REGION97_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION97_Enabled   (1UL)
 
#define BPROT_CONFIG3_REGION96_Pos   (0UL)
 
#define BPROT_CONFIG3_REGION96_Msk   (0x1UL << BPROT_CONFIG3_REGION96_Pos)
 
#define BPROT_CONFIG3_REGION96_Disabled   (0UL)
 
#define BPROT_CONFIG3_REGION96_Enabled   (1UL)
 
#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos   (0UL)
 
#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk   (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos)
 
#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled   (0UL)
 
#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled   (1UL)
 
#define CCM_INTENSET_ERROR_Pos   (2UL)
 
#define CCM_INTENSET_ERROR_Msk   (0x1UL << CCM_INTENSET_ERROR_Pos)
 
#define CCM_INTENSET_ERROR_Disabled   (0UL)
 
#define CCM_INTENSET_ERROR_Enabled   (1UL)
 
#define CCM_INTENSET_ERROR_Set   (1UL)
 
#define CCM_INTENSET_ENDCRYPT_Pos   (1UL)
 
#define CCM_INTENSET_ENDCRYPT_Msk   (0x1UL << CCM_INTENSET_ENDCRYPT_Pos)
 
#define CCM_INTENSET_ENDCRYPT_Disabled   (0UL)
 
#define CCM_INTENSET_ENDCRYPT_Enabled   (1UL)
 
#define CCM_INTENSET_ENDCRYPT_Set   (1UL)
 
#define CCM_INTENSET_ENDKSGEN_Pos   (0UL)
 
#define CCM_INTENSET_ENDKSGEN_Msk   (0x1UL << CCM_INTENSET_ENDKSGEN_Pos)
 
#define CCM_INTENSET_ENDKSGEN_Disabled   (0UL)
 
#define CCM_INTENSET_ENDKSGEN_Enabled   (1UL)
 
#define CCM_INTENSET_ENDKSGEN_Set   (1UL)
 
#define CCM_INTENCLR_ERROR_Pos   (2UL)
 
#define CCM_INTENCLR_ERROR_Msk   (0x1UL << CCM_INTENCLR_ERROR_Pos)
 
#define CCM_INTENCLR_ERROR_Disabled   (0UL)
 
#define CCM_INTENCLR_ERROR_Enabled   (1UL)
 
#define CCM_INTENCLR_ERROR_Clear   (1UL)
 
#define CCM_INTENCLR_ENDCRYPT_Pos   (1UL)
 
#define CCM_INTENCLR_ENDCRYPT_Msk   (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos)
 
#define CCM_INTENCLR_ENDCRYPT_Disabled   (0UL)
 
#define CCM_INTENCLR_ENDCRYPT_Enabled   (1UL)
 
#define CCM_INTENCLR_ENDCRYPT_Clear   (1UL)
 
#define CCM_INTENCLR_ENDKSGEN_Pos   (0UL)
 
#define CCM_INTENCLR_ENDKSGEN_Msk   (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos)
 
#define CCM_INTENCLR_ENDKSGEN_Disabled   (0UL)
 
#define CCM_INTENCLR_ENDKSGEN_Enabled   (1UL)
 
#define CCM_INTENCLR_ENDKSGEN_Clear   (1UL)
 
#define CCM_MICSTATUS_MICSTATUS_Pos   (0UL)
 
#define CCM_MICSTATUS_MICSTATUS_Msk   (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos)
 
#define CCM_MICSTATUS_MICSTATUS_CheckFailed   (0UL)
 
#define CCM_MICSTATUS_MICSTATUS_CheckPassed   (1UL)
 
#define CCM_ENABLE_ENABLE_Pos   (0UL)
 
#define CCM_ENABLE_ENABLE_Msk   (0x3UL << CCM_ENABLE_ENABLE_Pos)
 
#define CCM_ENABLE_ENABLE_Disabled   (0UL)
 
#define CCM_ENABLE_ENABLE_Enabled   (2UL)
 
#define CCM_MODE_LENGTH_Pos   (24UL)
 
#define CCM_MODE_LENGTH_Msk   (0x1UL << CCM_MODE_LENGTH_Pos)
 
#define CCM_MODE_LENGTH_Default   (0UL)
 
#define CCM_MODE_LENGTH_Extended   (1UL)
 
#define CCM_MODE_DATARATE_Pos   (16UL)
 
#define CCM_MODE_DATARATE_Msk   (0x1UL << CCM_MODE_DATARATE_Pos)
 
#define CCM_MODE_DATARATE_1Mbit   (0UL)
 
#define CCM_MODE_DATARATE_2Mbit   (1UL)
 
#define CCM_MODE_MODE_Pos   (0UL)
 
#define CCM_MODE_MODE_Msk   (0x1UL << CCM_MODE_MODE_Pos)
 
#define CCM_MODE_MODE_Encryption   (0UL)
 
#define CCM_MODE_MODE_Decryption   (1UL)
 
#define CCM_CNFPTR_CNFPTR_Pos   (0UL)
 
#define CCM_CNFPTR_CNFPTR_Msk   (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos)
 
#define CCM_INPTR_INPTR_Pos   (0UL)
 
#define CCM_INPTR_INPTR_Msk   (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos)
 
#define CCM_OUTPTR_OUTPTR_Pos   (0UL)
 
#define CCM_OUTPTR_OUTPTR_Msk   (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos)
 
#define CCM_SCRATCHPTR_SCRATCHPTR_Pos   (0UL)
 
#define CCM_SCRATCHPTR_SCRATCHPTR_Msk   (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos)
 
#define CLOCK_INTENSET_CTTO_Pos   (4UL)
 
#define CLOCK_INTENSET_CTTO_Msk   (0x1UL << CLOCK_INTENSET_CTTO_Pos)
 
#define CLOCK_INTENSET_CTTO_Disabled   (0UL)
 
#define CLOCK_INTENSET_CTTO_Enabled   (1UL)
 
#define CLOCK_INTENSET_CTTO_Set   (1UL)
 
#define CLOCK_INTENSET_DONE_Pos   (3UL)
 
#define CLOCK_INTENSET_DONE_Msk   (0x1UL << CLOCK_INTENSET_DONE_Pos)
 
#define CLOCK_INTENSET_DONE_Disabled   (0UL)
 
#define CLOCK_INTENSET_DONE_Enabled   (1UL)
 
#define CLOCK_INTENSET_DONE_Set   (1UL)
 
#define CLOCK_INTENSET_LFCLKSTARTED_Pos   (1UL)
 
#define CLOCK_INTENSET_LFCLKSTARTED_Msk   (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos)
 
#define CLOCK_INTENSET_LFCLKSTARTED_Disabled   (0UL)
 
#define CLOCK_INTENSET_LFCLKSTARTED_Enabled   (1UL)
 
#define CLOCK_INTENSET_LFCLKSTARTED_Set   (1UL)
 
#define CLOCK_INTENSET_HFCLKSTARTED_Pos   (0UL)
 
#define CLOCK_INTENSET_HFCLKSTARTED_Msk   (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos)
 
#define CLOCK_INTENSET_HFCLKSTARTED_Disabled   (0UL)
 
#define CLOCK_INTENSET_HFCLKSTARTED_Enabled   (1UL)
 
#define CLOCK_INTENSET_HFCLKSTARTED_Set   (1UL)
 
#define CLOCK_INTENCLR_CTTO_Pos   (4UL)
 
#define CLOCK_INTENCLR_CTTO_Msk   (0x1UL << CLOCK_INTENCLR_CTTO_Pos)
 
#define CLOCK_INTENCLR_CTTO_Disabled   (0UL)
 
#define CLOCK_INTENCLR_CTTO_Enabled   (1UL)
 
#define CLOCK_INTENCLR_CTTO_Clear   (1UL)
 
#define CLOCK_INTENCLR_DONE_Pos   (3UL)
 
#define CLOCK_INTENCLR_DONE_Msk   (0x1UL << CLOCK_INTENCLR_DONE_Pos)
 
#define CLOCK_INTENCLR_DONE_Disabled   (0UL)
 
#define CLOCK_INTENCLR_DONE_Enabled   (1UL)
 
#define CLOCK_INTENCLR_DONE_Clear   (1UL)
 
#define CLOCK_INTENCLR_LFCLKSTARTED_Pos   (1UL)
 
#define CLOCK_INTENCLR_LFCLKSTARTED_Msk   (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos)
 
#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled   (0UL)
 
#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled   (1UL)
 
#define CLOCK_INTENCLR_LFCLKSTARTED_Clear   (1UL)
 
#define CLOCK_INTENCLR_HFCLKSTARTED_Pos   (0UL)
 
#define CLOCK_INTENCLR_HFCLKSTARTED_Msk   (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos)
 
#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled   (0UL)
 
#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled   (1UL)
 
#define CLOCK_INTENCLR_HFCLKSTARTED_Clear   (1UL)
 
#define CLOCK_HFCLKRUN_STATUS_Pos   (0UL)
 
#define CLOCK_HFCLKRUN_STATUS_Msk   (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos)
 
#define CLOCK_HFCLKRUN_STATUS_NotTriggered   (0UL)
 
#define CLOCK_HFCLKRUN_STATUS_Triggered   (1UL)
 
#define CLOCK_HFCLKSTAT_STATE_Pos   (16UL)
 
#define CLOCK_HFCLKSTAT_STATE_Msk   (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos)
 
#define CLOCK_HFCLKSTAT_STATE_NotRunning   (0UL)
 
#define CLOCK_HFCLKSTAT_STATE_Running   (1UL)
 
#define CLOCK_HFCLKSTAT_SRC_Pos   (0UL)
 
#define CLOCK_HFCLKSTAT_SRC_Msk   (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos)
 
#define CLOCK_HFCLKSTAT_SRC_RC   (0UL)
 
#define CLOCK_HFCLKSTAT_SRC_Xtal   (1UL)
 
#define CLOCK_LFCLKRUN_STATUS_Pos   (0UL)
 
#define CLOCK_LFCLKRUN_STATUS_Msk   (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos)
 
#define CLOCK_LFCLKRUN_STATUS_NotTriggered   (0UL)
 
#define CLOCK_LFCLKRUN_STATUS_Triggered   (1UL)
 
#define CLOCK_LFCLKSTAT_STATE_Pos   (16UL)
 
#define CLOCK_LFCLKSTAT_STATE_Msk   (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos)
 
#define CLOCK_LFCLKSTAT_STATE_NotRunning   (0UL)
 
#define CLOCK_LFCLKSTAT_STATE_Running   (1UL)
 
#define CLOCK_LFCLKSTAT_SRC_Pos   (0UL)
 
#define CLOCK_LFCLKSTAT_SRC_Msk   (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos)
 
#define CLOCK_LFCLKSTAT_SRC_RC   (0UL)
 
#define CLOCK_LFCLKSTAT_SRC_Xtal   (1UL)
 
#define CLOCK_LFCLKSTAT_SRC_Synth   (2UL)
 
#define CLOCK_LFCLKSRCCOPY_SRC_Pos   (0UL)
 
#define CLOCK_LFCLKSRCCOPY_SRC_Msk   (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos)
 
#define CLOCK_LFCLKSRCCOPY_SRC_RC   (0UL)
 
#define CLOCK_LFCLKSRCCOPY_SRC_Xtal   (1UL)
 
#define CLOCK_LFCLKSRCCOPY_SRC_Synth   (2UL)
 
#define CLOCK_LFCLKSRC_EXTERNAL_Pos   (17UL)
 
#define CLOCK_LFCLKSRC_EXTERNAL_Msk   (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos)
 
#define CLOCK_LFCLKSRC_EXTERNAL_Disabled   (0UL)
 
#define CLOCK_LFCLKSRC_EXTERNAL_Enabled   (1UL)
 
#define CLOCK_LFCLKSRC_BYPASS_Pos   (16UL)
 
#define CLOCK_LFCLKSRC_BYPASS_Msk   (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos)
 
#define CLOCK_LFCLKSRC_BYPASS_Disabled   (0UL)
 
#define CLOCK_LFCLKSRC_BYPASS_Enabled   (1UL)
 
#define CLOCK_LFCLKSRC_SRC_Pos   (0UL)
 
#define CLOCK_LFCLKSRC_SRC_Msk   (0x3UL << CLOCK_LFCLKSRC_SRC_Pos)
 
#define CLOCK_LFCLKSRC_SRC_RC   (0UL)
 
#define CLOCK_LFCLKSRC_SRC_Xtal   (1UL)
 
#define CLOCK_LFCLKSRC_SRC_Synth   (2UL)
 
#define CLOCK_CTIV_CTIV_Pos   (0UL)
 
#define CLOCK_CTIV_CTIV_Msk   (0x7FUL << CLOCK_CTIV_CTIV_Pos)
 
#define CLOCK_TRACECONFIG_TRACEMUX_Pos   (16UL)
 
#define CLOCK_TRACECONFIG_TRACEMUX_Msk   (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos)
 
#define CLOCK_TRACECONFIG_TRACEMUX_GPIO   (0UL)
 
#define CLOCK_TRACECONFIG_TRACEMUX_Serial   (1UL)
 
#define CLOCK_TRACECONFIG_TRACEMUX_Parallel   (2UL)
 
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos   (0UL)
 
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk   (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos)
 
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz   (0UL)
 
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz   (1UL)
 
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz   (2UL)
 
#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz   (3UL)
 
#define COMP_SHORTS_CROSS_STOP_Pos   (4UL)
 
#define COMP_SHORTS_CROSS_STOP_Msk   (0x1UL << COMP_SHORTS_CROSS_STOP_Pos)
 
#define COMP_SHORTS_CROSS_STOP_Disabled   (0UL)
 
#define COMP_SHORTS_CROSS_STOP_Enabled   (1UL)
 
#define COMP_SHORTS_UP_STOP_Pos   (3UL)
 
#define COMP_SHORTS_UP_STOP_Msk   (0x1UL << COMP_SHORTS_UP_STOP_Pos)
 
#define COMP_SHORTS_UP_STOP_Disabled   (0UL)
 
#define COMP_SHORTS_UP_STOP_Enabled   (1UL)
 
#define COMP_SHORTS_DOWN_STOP_Pos   (2UL)
 
#define COMP_SHORTS_DOWN_STOP_Msk   (0x1UL << COMP_SHORTS_DOWN_STOP_Pos)
 
#define COMP_SHORTS_DOWN_STOP_Disabled   (0UL)
 
#define COMP_SHORTS_DOWN_STOP_Enabled   (1UL)
 
#define COMP_SHORTS_READY_STOP_Pos   (1UL)
 
#define COMP_SHORTS_READY_STOP_Msk   (0x1UL << COMP_SHORTS_READY_STOP_Pos)
 
#define COMP_SHORTS_READY_STOP_Disabled   (0UL)
 
#define COMP_SHORTS_READY_STOP_Enabled   (1UL)
 
#define COMP_SHORTS_READY_SAMPLE_Pos   (0UL)
 
#define COMP_SHORTS_READY_SAMPLE_Msk   (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos)
 
#define COMP_SHORTS_READY_SAMPLE_Disabled   (0UL)
 
#define COMP_SHORTS_READY_SAMPLE_Enabled   (1UL)
 
#define COMP_INTEN_CROSS_Pos   (3UL)
 
#define COMP_INTEN_CROSS_Msk   (0x1UL << COMP_INTEN_CROSS_Pos)
 
#define COMP_INTEN_CROSS_Disabled   (0UL)
 
#define COMP_INTEN_CROSS_Enabled   (1UL)
 
#define COMP_INTEN_UP_Pos   (2UL)
 
#define COMP_INTEN_UP_Msk   (0x1UL << COMP_INTEN_UP_Pos)
 
#define COMP_INTEN_UP_Disabled   (0UL)
 
#define COMP_INTEN_UP_Enabled   (1UL)
 
#define COMP_INTEN_DOWN_Pos   (1UL)
 
#define COMP_INTEN_DOWN_Msk   (0x1UL << COMP_INTEN_DOWN_Pos)
 
#define COMP_INTEN_DOWN_Disabled   (0UL)
 
#define COMP_INTEN_DOWN_Enabled   (1UL)
 
#define COMP_INTEN_READY_Pos   (0UL)
 
#define COMP_INTEN_READY_Msk   (0x1UL << COMP_INTEN_READY_Pos)
 
#define COMP_INTEN_READY_Disabled   (0UL)
 
#define COMP_INTEN_READY_Enabled   (1UL)
 
#define COMP_INTENSET_CROSS_Pos   (3UL)
 
#define COMP_INTENSET_CROSS_Msk   (0x1UL << COMP_INTENSET_CROSS_Pos)
 
#define COMP_INTENSET_CROSS_Disabled   (0UL)
 
#define COMP_INTENSET_CROSS_Enabled   (1UL)
 
#define COMP_INTENSET_CROSS_Set   (1UL)
 
#define COMP_INTENSET_UP_Pos   (2UL)
 
#define COMP_INTENSET_UP_Msk   (0x1UL << COMP_INTENSET_UP_Pos)
 
#define COMP_INTENSET_UP_Disabled   (0UL)
 
#define COMP_INTENSET_UP_Enabled   (1UL)
 
#define COMP_INTENSET_UP_Set   (1UL)
 
#define COMP_INTENSET_DOWN_Pos   (1UL)
 
#define COMP_INTENSET_DOWN_Msk   (0x1UL << COMP_INTENSET_DOWN_Pos)
 
#define COMP_INTENSET_DOWN_Disabled   (0UL)
 
#define COMP_INTENSET_DOWN_Enabled   (1UL)
 
#define COMP_INTENSET_DOWN_Set   (1UL)
 
#define COMP_INTENSET_READY_Pos   (0UL)
 
#define COMP_INTENSET_READY_Msk   (0x1UL << COMP_INTENSET_READY_Pos)
 
#define COMP_INTENSET_READY_Disabled   (0UL)
 
#define COMP_INTENSET_READY_Enabled   (1UL)
 
#define COMP_INTENSET_READY_Set   (1UL)
 
#define COMP_INTENCLR_CROSS_Pos   (3UL)
 
#define COMP_INTENCLR_CROSS_Msk   (0x1UL << COMP_INTENCLR_CROSS_Pos)
 
#define COMP_INTENCLR_CROSS_Disabled   (0UL)
 
#define COMP_INTENCLR_CROSS_Enabled   (1UL)
 
#define COMP_INTENCLR_CROSS_Clear   (1UL)
 
#define COMP_INTENCLR_UP_Pos   (2UL)
 
#define COMP_INTENCLR_UP_Msk   (0x1UL << COMP_INTENCLR_UP_Pos)
 
#define COMP_INTENCLR_UP_Disabled   (0UL)
 
#define COMP_INTENCLR_UP_Enabled   (1UL)
 
#define COMP_INTENCLR_UP_Clear   (1UL)
 
#define COMP_INTENCLR_DOWN_Pos   (1UL)
 
#define COMP_INTENCLR_DOWN_Msk   (0x1UL << COMP_INTENCLR_DOWN_Pos)
 
#define COMP_INTENCLR_DOWN_Disabled   (0UL)
 
#define COMP_INTENCLR_DOWN_Enabled   (1UL)
 
#define COMP_INTENCLR_DOWN_Clear   (1UL)
 
#define COMP_INTENCLR_READY_Pos   (0UL)
 
#define COMP_INTENCLR_READY_Msk   (0x1UL << COMP_INTENCLR_READY_Pos)
 
#define COMP_INTENCLR_READY_Disabled   (0UL)
 
#define COMP_INTENCLR_READY_Enabled   (1UL)
 
#define COMP_INTENCLR_READY_Clear   (1UL)
 
#define COMP_RESULT_RESULT_Pos   (0UL)
 
#define COMP_RESULT_RESULT_Msk   (0x1UL << COMP_RESULT_RESULT_Pos)
 
#define COMP_RESULT_RESULT_Below   (0UL)
 
#define COMP_RESULT_RESULT_Above   (1UL)
 
#define COMP_ENABLE_ENABLE_Pos   (0UL)
 
#define COMP_ENABLE_ENABLE_Msk   (0x3UL << COMP_ENABLE_ENABLE_Pos)
 
#define COMP_ENABLE_ENABLE_Disabled   (0UL)
 
#define COMP_ENABLE_ENABLE_Enabled   (2UL)
 
#define COMP_PSEL_PSEL_Pos   (0UL)
 
#define COMP_PSEL_PSEL_Msk   (0x7UL << COMP_PSEL_PSEL_Pos)
 
#define COMP_PSEL_PSEL_AnalogInput0   (0UL)
 
#define COMP_PSEL_PSEL_AnalogInput1   (1UL)
 
#define COMP_PSEL_PSEL_AnalogInput2   (2UL)
 
#define COMP_PSEL_PSEL_AnalogInput3   (3UL)
 
#define COMP_PSEL_PSEL_AnalogInput4   (4UL)
 
#define COMP_PSEL_PSEL_AnalogInput5   (5UL)
 
#define COMP_PSEL_PSEL_AnalogInput6   (6UL)
 
#define COMP_PSEL_PSEL_AnalogInput7   (7UL)
 
#define COMP_REFSEL_REFSEL_Pos   (0UL)
 
#define COMP_REFSEL_REFSEL_Msk   (0x7UL << COMP_REFSEL_REFSEL_Pos)
 
#define COMP_REFSEL_REFSEL_Int1V2   (0UL)
 
#define COMP_REFSEL_REFSEL_Int1V8   (1UL)
 
#define COMP_REFSEL_REFSEL_Int2V4   (2UL)
 
#define COMP_REFSEL_REFSEL_VDD   (4UL)
 
#define COMP_REFSEL_REFSEL_ARef   (7UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_Pos   (0UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_Msk   (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos)
 
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0   (0UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1   (1UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2   (2UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3   (3UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4   (4UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5   (5UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6   (6UL)
 
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7   (7UL)
 
#define COMP_TH_THUP_Pos   (8UL)
 
#define COMP_TH_THUP_Msk   (0x3FUL << COMP_TH_THUP_Pos)
 
#define COMP_TH_THDOWN_Pos   (0UL)
 
#define COMP_TH_THDOWN_Msk   (0x3FUL << COMP_TH_THDOWN_Pos)
 
#define COMP_MODE_MAIN_Pos   (8UL)
 
#define COMP_MODE_MAIN_Msk   (0x1UL << COMP_MODE_MAIN_Pos)
 
#define COMP_MODE_MAIN_SE   (0UL)
 
#define COMP_MODE_MAIN_Diff   (1UL)
 
#define COMP_MODE_SP_Pos   (0UL)
 
#define COMP_MODE_SP_Msk   (0x3UL << COMP_MODE_SP_Pos)
 
#define COMP_MODE_SP_Low   (0UL)
 
#define COMP_MODE_SP_Normal   (1UL)
 
#define COMP_MODE_SP_High   (2UL)
 
#define COMP_HYST_HYST_Pos   (0UL)
 
#define COMP_HYST_HYST_Msk   (0x1UL << COMP_HYST_HYST_Pos)
 
#define COMP_HYST_HYST_NoHyst   (0UL)
 
#define COMP_HYST_HYST_Hyst50mV   (1UL)
 
#define COMP_ISOURCE_ISOURCE_Pos   (0UL)
 
#define COMP_ISOURCE_ISOURCE_Msk   (0x3UL << COMP_ISOURCE_ISOURCE_Pos)
 
#define COMP_ISOURCE_ISOURCE_Off   (0UL)
 
#define COMP_ISOURCE_ISOURCE_Ien2mA5   (1UL)
 
#define COMP_ISOURCE_ISOURCE_Ien5mA   (2UL)
 
#define COMP_ISOURCE_ISOURCE_Ien10mA   (3UL)
 
#define ECB_INTENSET_ERRORECB_Pos   (1UL)
 
#define ECB_INTENSET_ERRORECB_Msk   (0x1UL << ECB_INTENSET_ERRORECB_Pos)
 
#define ECB_INTENSET_ERRORECB_Disabled   (0UL)
 
#define ECB_INTENSET_ERRORECB_Enabled   (1UL)
 
#define ECB_INTENSET_ERRORECB_Set   (1UL)
 
#define ECB_INTENSET_ENDECB_Pos   (0UL)
 
#define ECB_INTENSET_ENDECB_Msk   (0x1UL << ECB_INTENSET_ENDECB_Pos)
 
#define ECB_INTENSET_ENDECB_Disabled   (0UL)
 
#define ECB_INTENSET_ENDECB_Enabled   (1UL)
 
#define ECB_INTENSET_ENDECB_Set   (1UL)
 
#define ECB_INTENCLR_ERRORECB_Pos   (1UL)
 
#define ECB_INTENCLR_ERRORECB_Msk   (0x1UL << ECB_INTENCLR_ERRORECB_Pos)
 
#define ECB_INTENCLR_ERRORECB_Disabled   (0UL)
 
#define ECB_INTENCLR_ERRORECB_Enabled   (1UL)
 
#define ECB_INTENCLR_ERRORECB_Clear   (1UL)
 
#define ECB_INTENCLR_ENDECB_Pos   (0UL)
 
#define ECB_INTENCLR_ENDECB_Msk   (0x1UL << ECB_INTENCLR_ENDECB_Pos)
 
#define ECB_INTENCLR_ENDECB_Disabled   (0UL)
 
#define ECB_INTENCLR_ENDECB_Enabled   (1UL)
 
#define ECB_INTENCLR_ENDECB_Clear   (1UL)
 
#define ECB_ECBDATAPTR_ECBDATAPTR_Pos   (0UL)
 
#define ECB_ECBDATAPTR_ECBDATAPTR_Msk   (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos)
 
#define EGU_INTEN_TRIGGERED15_Pos   (15UL)
 
#define EGU_INTEN_TRIGGERED15_Msk   (0x1UL << EGU_INTEN_TRIGGERED15_Pos)
 
#define EGU_INTEN_TRIGGERED15_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED15_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED14_Pos   (14UL)
 
#define EGU_INTEN_TRIGGERED14_Msk   (0x1UL << EGU_INTEN_TRIGGERED14_Pos)
 
#define EGU_INTEN_TRIGGERED14_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED14_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED13_Pos   (13UL)
 
#define EGU_INTEN_TRIGGERED13_Msk   (0x1UL << EGU_INTEN_TRIGGERED13_Pos)
 
#define EGU_INTEN_TRIGGERED13_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED13_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED12_Pos   (12UL)
 
#define EGU_INTEN_TRIGGERED12_Msk   (0x1UL << EGU_INTEN_TRIGGERED12_Pos)
 
#define EGU_INTEN_TRIGGERED12_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED12_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED11_Pos   (11UL)
 
#define EGU_INTEN_TRIGGERED11_Msk   (0x1UL << EGU_INTEN_TRIGGERED11_Pos)
 
#define EGU_INTEN_TRIGGERED11_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED11_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED10_Pos   (10UL)
 
#define EGU_INTEN_TRIGGERED10_Msk   (0x1UL << EGU_INTEN_TRIGGERED10_Pos)
 
#define EGU_INTEN_TRIGGERED10_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED10_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED9_Pos   (9UL)
 
#define EGU_INTEN_TRIGGERED9_Msk   (0x1UL << EGU_INTEN_TRIGGERED9_Pos)
 
#define EGU_INTEN_TRIGGERED9_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED9_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED8_Pos   (8UL)
 
#define EGU_INTEN_TRIGGERED8_Msk   (0x1UL << EGU_INTEN_TRIGGERED8_Pos)
 
#define EGU_INTEN_TRIGGERED8_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED8_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED7_Pos   (7UL)
 
#define EGU_INTEN_TRIGGERED7_Msk   (0x1UL << EGU_INTEN_TRIGGERED7_Pos)
 
#define EGU_INTEN_TRIGGERED7_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED7_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED6_Pos   (6UL)
 
#define EGU_INTEN_TRIGGERED6_Msk   (0x1UL << EGU_INTEN_TRIGGERED6_Pos)
 
#define EGU_INTEN_TRIGGERED6_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED6_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED5_Pos   (5UL)
 
#define EGU_INTEN_TRIGGERED5_Msk   (0x1UL << EGU_INTEN_TRIGGERED5_Pos)
 
#define EGU_INTEN_TRIGGERED5_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED5_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED4_Pos   (4UL)
 
#define EGU_INTEN_TRIGGERED4_Msk   (0x1UL << EGU_INTEN_TRIGGERED4_Pos)
 
#define EGU_INTEN_TRIGGERED4_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED4_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED3_Pos   (3UL)
 
#define EGU_INTEN_TRIGGERED3_Msk   (0x1UL << EGU_INTEN_TRIGGERED3_Pos)
 
#define EGU_INTEN_TRIGGERED3_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED3_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED2_Pos   (2UL)
 
#define EGU_INTEN_TRIGGERED2_Msk   (0x1UL << EGU_INTEN_TRIGGERED2_Pos)
 
#define EGU_INTEN_TRIGGERED2_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED2_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED1_Pos   (1UL)
 
#define EGU_INTEN_TRIGGERED1_Msk   (0x1UL << EGU_INTEN_TRIGGERED1_Pos)
 
#define EGU_INTEN_TRIGGERED1_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED1_Enabled   (1UL)
 
#define EGU_INTEN_TRIGGERED0_Pos   (0UL)
 
#define EGU_INTEN_TRIGGERED0_Msk   (0x1UL << EGU_INTEN_TRIGGERED0_Pos)
 
#define EGU_INTEN_TRIGGERED0_Disabled   (0UL)
 
#define EGU_INTEN_TRIGGERED0_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED15_Pos   (15UL)
 
#define EGU_INTENSET_TRIGGERED15_Msk   (0x1UL << EGU_INTENSET_TRIGGERED15_Pos)
 
#define EGU_INTENSET_TRIGGERED15_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED15_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED15_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED14_Pos   (14UL)
 
#define EGU_INTENSET_TRIGGERED14_Msk   (0x1UL << EGU_INTENSET_TRIGGERED14_Pos)
 
#define EGU_INTENSET_TRIGGERED14_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED14_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED14_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED13_Pos   (13UL)
 
#define EGU_INTENSET_TRIGGERED13_Msk   (0x1UL << EGU_INTENSET_TRIGGERED13_Pos)
 
#define EGU_INTENSET_TRIGGERED13_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED13_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED13_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED12_Pos   (12UL)
 
#define EGU_INTENSET_TRIGGERED12_Msk   (0x1UL << EGU_INTENSET_TRIGGERED12_Pos)
 
#define EGU_INTENSET_TRIGGERED12_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED12_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED12_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED11_Pos   (11UL)
 
#define EGU_INTENSET_TRIGGERED11_Msk   (0x1UL << EGU_INTENSET_TRIGGERED11_Pos)
 
#define EGU_INTENSET_TRIGGERED11_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED11_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED11_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED10_Pos   (10UL)
 
#define EGU_INTENSET_TRIGGERED10_Msk   (0x1UL << EGU_INTENSET_TRIGGERED10_Pos)
 
#define EGU_INTENSET_TRIGGERED10_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED10_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED10_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED9_Pos   (9UL)
 
#define EGU_INTENSET_TRIGGERED9_Msk   (0x1UL << EGU_INTENSET_TRIGGERED9_Pos)
 
#define EGU_INTENSET_TRIGGERED9_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED9_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED9_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED8_Pos   (8UL)
 
#define EGU_INTENSET_TRIGGERED8_Msk   (0x1UL << EGU_INTENSET_TRIGGERED8_Pos)
 
#define EGU_INTENSET_TRIGGERED8_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED8_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED8_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED7_Pos   (7UL)
 
#define EGU_INTENSET_TRIGGERED7_Msk   (0x1UL << EGU_INTENSET_TRIGGERED7_Pos)
 
#define EGU_INTENSET_TRIGGERED7_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED7_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED7_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED6_Pos   (6UL)
 
#define EGU_INTENSET_TRIGGERED6_Msk   (0x1UL << EGU_INTENSET_TRIGGERED6_Pos)
 
#define EGU_INTENSET_TRIGGERED6_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED6_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED6_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED5_Pos   (5UL)
 
#define EGU_INTENSET_TRIGGERED5_Msk   (0x1UL << EGU_INTENSET_TRIGGERED5_Pos)
 
#define EGU_INTENSET_TRIGGERED5_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED5_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED5_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED4_Pos   (4UL)
 
#define EGU_INTENSET_TRIGGERED4_Msk   (0x1UL << EGU_INTENSET_TRIGGERED4_Pos)
 
#define EGU_INTENSET_TRIGGERED4_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED4_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED4_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED3_Pos   (3UL)
 
#define EGU_INTENSET_TRIGGERED3_Msk   (0x1UL << EGU_INTENSET_TRIGGERED3_Pos)
 
#define EGU_INTENSET_TRIGGERED3_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED3_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED3_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED2_Pos   (2UL)
 
#define EGU_INTENSET_TRIGGERED2_Msk   (0x1UL << EGU_INTENSET_TRIGGERED2_Pos)
 
#define EGU_INTENSET_TRIGGERED2_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED2_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED2_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED1_Pos   (1UL)
 
#define EGU_INTENSET_TRIGGERED1_Msk   (0x1UL << EGU_INTENSET_TRIGGERED1_Pos)
 
#define EGU_INTENSET_TRIGGERED1_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED1_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED1_Set   (1UL)
 
#define EGU_INTENSET_TRIGGERED0_Pos   (0UL)
 
#define EGU_INTENSET_TRIGGERED0_Msk   (0x1UL << EGU_INTENSET_TRIGGERED0_Pos)
 
#define EGU_INTENSET_TRIGGERED0_Disabled   (0UL)
 
#define EGU_INTENSET_TRIGGERED0_Enabled   (1UL)
 
#define EGU_INTENSET_TRIGGERED0_Set   (1UL)
 
#define EGU_INTENCLR_TRIGGERED15_Pos   (15UL)
 
#define EGU_INTENCLR_TRIGGERED15_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos)
 
#define EGU_INTENCLR_TRIGGERED15_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED15_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED15_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED14_Pos   (14UL)
 
#define EGU_INTENCLR_TRIGGERED14_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos)
 
#define EGU_INTENCLR_TRIGGERED14_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED14_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED14_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED13_Pos   (13UL)
 
#define EGU_INTENCLR_TRIGGERED13_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos)
 
#define EGU_INTENCLR_TRIGGERED13_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED13_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED13_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED12_Pos   (12UL)
 
#define EGU_INTENCLR_TRIGGERED12_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos)
 
#define EGU_INTENCLR_TRIGGERED12_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED12_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED12_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED11_Pos   (11UL)
 
#define EGU_INTENCLR_TRIGGERED11_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos)
 
#define EGU_INTENCLR_TRIGGERED11_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED11_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED11_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED10_Pos   (10UL)
 
#define EGU_INTENCLR_TRIGGERED10_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos)
 
#define EGU_INTENCLR_TRIGGERED10_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED10_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED10_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED9_Pos   (9UL)
 
#define EGU_INTENCLR_TRIGGERED9_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos)
 
#define EGU_INTENCLR_TRIGGERED9_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED9_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED9_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED8_Pos   (8UL)
 
#define EGU_INTENCLR_TRIGGERED8_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos)
 
#define EGU_INTENCLR_TRIGGERED8_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED8_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED8_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED7_Pos   (7UL)
 
#define EGU_INTENCLR_TRIGGERED7_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos)
 
#define EGU_INTENCLR_TRIGGERED7_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED7_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED7_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED6_Pos   (6UL)
 
#define EGU_INTENCLR_TRIGGERED6_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos)
 
#define EGU_INTENCLR_TRIGGERED6_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED6_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED6_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED5_Pos   (5UL)
 
#define EGU_INTENCLR_TRIGGERED5_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos)
 
#define EGU_INTENCLR_TRIGGERED5_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED5_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED5_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED4_Pos   (4UL)
 
#define EGU_INTENCLR_TRIGGERED4_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos)
 
#define EGU_INTENCLR_TRIGGERED4_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED4_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED4_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED3_Pos   (3UL)
 
#define EGU_INTENCLR_TRIGGERED3_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos)
 
#define EGU_INTENCLR_TRIGGERED3_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED3_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED3_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED2_Pos   (2UL)
 
#define EGU_INTENCLR_TRIGGERED2_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos)
 
#define EGU_INTENCLR_TRIGGERED2_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED2_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED2_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED1_Pos   (1UL)
 
#define EGU_INTENCLR_TRIGGERED1_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos)
 
#define EGU_INTENCLR_TRIGGERED1_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED1_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED1_Clear   (1UL)
 
#define EGU_INTENCLR_TRIGGERED0_Pos   (0UL)
 
#define EGU_INTENCLR_TRIGGERED0_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos)
 
#define EGU_INTENCLR_TRIGGERED0_Disabled   (0UL)
 
#define EGU_INTENCLR_TRIGGERED0_Enabled   (1UL)
 
#define EGU_INTENCLR_TRIGGERED0_Clear   (1UL)
 
#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos   (0UL)
 
#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk   (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos)
 
#define FICR_CODESIZE_CODESIZE_Pos   (0UL)
 
#define FICR_CODESIZE_CODESIZE_Msk   (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos)
 
#define FICR_DEVICEID_DEVICEID_Pos   (0UL)
 
#define FICR_DEVICEID_DEVICEID_Msk   (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos)
 
#define FICR_ER_ER_Pos   (0UL)
 
#define FICR_ER_ER_Msk   (0xFFFFFFFFUL << FICR_ER_ER_Pos)
 
#define FICR_IR_IR_Pos   (0UL)
 
#define FICR_IR_IR_Msk   (0xFFFFFFFFUL << FICR_IR_IR_Pos)
 
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos   (0UL)
 
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk   (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos)
 
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public   (0UL)
 
#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random   (1UL)
 
#define FICR_DEVICEADDR_DEVICEADDR_Pos   (0UL)
 
#define FICR_DEVICEADDR_DEVICEADDR_Msk   (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos)
 
#define FICR_INFO_PART_PART_Pos   (0UL)
 
#define FICR_INFO_PART_PART_Msk   (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos)
 
#define FICR_INFO_PART_PART_N52832   (0x52832UL)
 
#define FICR_INFO_PART_PART_Unspecified   (0xFFFFFFFFUL)
 
#define FICR_INFO_VARIANT_VARIANT_Pos   (0UL)
 
#define FICR_INFO_VARIANT_VARIANT_Msk   (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos)
 
#define FICR_INFO_VARIANT_VARIANT_AAAA   (0x41414141UL)
 
#define FICR_INFO_VARIANT_VARIANT_AAAB   (0x41414142UL)
 
#define FICR_INFO_VARIANT_VARIANT_AAB0   (0x41414230UL)
 
#define FICR_INFO_VARIANT_VARIANT_AABA   (0x41414241UL)
 
#define FICR_INFO_VARIANT_VARIANT_AABB   (0x41414242UL)
 
#define FICR_INFO_VARIANT_VARIANT_AAE0   (0x41414530UL)
 
#define FICR_INFO_VARIANT_VARIANT_Unspecified   (0xFFFFFFFFUL)
 
#define FICR_INFO_PACKAGE_PACKAGE_Pos   (0UL)
 
#define FICR_INFO_PACKAGE_PACKAGE_Msk   (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos)
 
#define FICR_INFO_PACKAGE_PACKAGE_QF   (0x2000UL)
 
#define FICR_INFO_PACKAGE_PACKAGE_CH   (0x2001UL)
 
#define FICR_INFO_PACKAGE_PACKAGE_CI   (0x2002UL)
 
#define FICR_INFO_PACKAGE_PACKAGE_CK   (0x2005UL)
 
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified   (0xFFFFFFFFUL)
 
#define FICR_INFO_RAM_RAM_Pos   (0UL)
 
#define FICR_INFO_RAM_RAM_Msk   (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos)
 
#define FICR_INFO_RAM_RAM_K16   (0x10UL)
 
#define FICR_INFO_RAM_RAM_K32   (0x20UL)
 
#define FICR_INFO_RAM_RAM_K64   (0x40UL)
 
#define FICR_INFO_RAM_RAM_Unspecified   (0xFFFFFFFFUL)
 
#define FICR_INFO_FLASH_FLASH_Pos   (0UL)
 
#define FICR_INFO_FLASH_FLASH_Msk   (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos)
 
#define FICR_INFO_FLASH_FLASH_K128   (0x80UL)
 
#define FICR_INFO_FLASH_FLASH_K256   (0x100UL)
 
#define FICR_INFO_FLASH_FLASH_K512   (0x200UL)
 
#define FICR_INFO_FLASH_FLASH_Unspecified   (0xFFFFFFFFUL)
 
#define FICR_TEMP_A0_A_Pos   (0UL)
 
#define FICR_TEMP_A0_A_Msk   (0xFFFUL << FICR_TEMP_A0_A_Pos)
 
#define FICR_TEMP_A1_A_Pos   (0UL)
 
#define FICR_TEMP_A1_A_Msk   (0xFFFUL << FICR_TEMP_A1_A_Pos)
 
#define FICR_TEMP_A2_A_Pos   (0UL)
 
#define FICR_TEMP_A2_A_Msk   (0xFFFUL << FICR_TEMP_A2_A_Pos)
 
#define FICR_TEMP_A3_A_Pos   (0UL)
 
#define FICR_TEMP_A3_A_Msk   (0xFFFUL << FICR_TEMP_A3_A_Pos)
 
#define FICR_TEMP_A4_A_Pos   (0UL)
 
#define FICR_TEMP_A4_A_Msk   (0xFFFUL << FICR_TEMP_A4_A_Pos)
 
#define FICR_TEMP_A5_A_Pos   (0UL)
 
#define FICR_TEMP_A5_A_Msk   (0xFFFUL << FICR_TEMP_A5_A_Pos)
 
#define FICR_TEMP_B0_B_Pos   (0UL)
 
#define FICR_TEMP_B0_B_Msk   (0x3FFFUL << FICR_TEMP_B0_B_Pos)
 
#define FICR_TEMP_B1_B_Pos   (0UL)
 
#define FICR_TEMP_B1_B_Msk   (0x3FFFUL << FICR_TEMP_B1_B_Pos)
 
#define FICR_TEMP_B2_B_Pos   (0UL)
 
#define FICR_TEMP_B2_B_Msk   (0x3FFFUL << FICR_TEMP_B2_B_Pos)
 
#define FICR_TEMP_B3_B_Pos   (0UL)
 
#define FICR_TEMP_B3_B_Msk   (0x3FFFUL << FICR_TEMP_B3_B_Pos)
 
#define FICR_TEMP_B4_B_Pos   (0UL)
 
#define FICR_TEMP_B4_B_Msk   (0x3FFFUL << FICR_TEMP_B4_B_Pos)
 
#define FICR_TEMP_B5_B_Pos   (0UL)
 
#define FICR_TEMP_B5_B_Msk   (0x3FFFUL << FICR_TEMP_B5_B_Pos)
 
#define FICR_TEMP_T0_T_Pos   (0UL)
 
#define FICR_TEMP_T0_T_Msk   (0xFFUL << FICR_TEMP_T0_T_Pos)
 
#define FICR_TEMP_T1_T_Pos   (0UL)
 
#define FICR_TEMP_T1_T_Msk   (0xFFUL << FICR_TEMP_T1_T_Pos)
 
#define FICR_TEMP_T2_T_Pos   (0UL)
 
#define FICR_TEMP_T2_T_Msk   (0xFFUL << FICR_TEMP_T2_T_Pos)
 
#define FICR_TEMP_T3_T_Pos   (0UL)
 
#define FICR_TEMP_T3_T_Msk   (0xFFUL << FICR_TEMP_T3_T_Pos)
 
#define FICR_TEMP_T4_T_Pos   (0UL)
 
#define FICR_TEMP_T4_T_Msk   (0xFFUL << FICR_TEMP_T4_T_Pos)
 
#define FICR_NFC_TAGHEADER0_UD3_Pos   (24UL)
 
#define FICR_NFC_TAGHEADER0_UD3_Msk   (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos)
 
#define FICR_NFC_TAGHEADER0_UD2_Pos   (16UL)
 
#define FICR_NFC_TAGHEADER0_UD2_Msk   (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos)
 
#define FICR_NFC_TAGHEADER0_UD1_Pos   (8UL)
 
#define FICR_NFC_TAGHEADER0_UD1_Msk   (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos)
 
#define FICR_NFC_TAGHEADER0_MFGID_Pos   (0UL)
 
#define FICR_NFC_TAGHEADER0_MFGID_Msk   (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos)
 
#define FICR_NFC_TAGHEADER1_UD7_Pos   (24UL)
 
#define FICR_NFC_TAGHEADER1_UD7_Msk   (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos)
 
#define FICR_NFC_TAGHEADER1_UD6_Pos   (16UL)
 
#define FICR_NFC_TAGHEADER1_UD6_Msk   (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos)
 
#define FICR_NFC_TAGHEADER1_UD5_Pos   (8UL)
 
#define FICR_NFC_TAGHEADER1_UD5_Msk   (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos)
 
#define FICR_NFC_TAGHEADER1_UD4_Pos   (0UL)
 
#define FICR_NFC_TAGHEADER1_UD4_Msk   (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos)
 
#define FICR_NFC_TAGHEADER2_UD11_Pos   (24UL)
 
#define FICR_NFC_TAGHEADER2_UD11_Msk   (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos)
 
#define FICR_NFC_TAGHEADER2_UD10_Pos   (16UL)
 
#define FICR_NFC_TAGHEADER2_UD10_Msk   (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos)
 
#define FICR_NFC_TAGHEADER2_UD9_Pos   (8UL)
 
#define FICR_NFC_TAGHEADER2_UD9_Msk   (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos)
 
#define FICR_NFC_TAGHEADER2_UD8_Pos   (0UL)
 
#define FICR_NFC_TAGHEADER2_UD8_Msk   (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos)
 
#define FICR_NFC_TAGHEADER3_UD15_Pos   (24UL)
 
#define FICR_NFC_TAGHEADER3_UD15_Msk   (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos)
 
#define FICR_NFC_TAGHEADER3_UD14_Pos   (16UL)
 
#define FICR_NFC_TAGHEADER3_UD14_Msk   (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos)
 
#define FICR_NFC_TAGHEADER3_UD13_Pos   (8UL)
 
#define FICR_NFC_TAGHEADER3_UD13_Msk   (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos)
 
#define FICR_NFC_TAGHEADER3_UD12_Pos   (0UL)
 
#define FICR_NFC_TAGHEADER3_UD12_Msk   (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos)
 
#define GPIOTE_INTENSET_PORT_Pos   (31UL)
 
#define GPIOTE_INTENSET_PORT_Msk   (0x1UL << GPIOTE_INTENSET_PORT_Pos)
 
#define GPIOTE_INTENSET_PORT_Disabled   (0UL)
 
#define GPIOTE_INTENSET_PORT_Enabled   (1UL)
 
#define GPIOTE_INTENSET_PORT_Set   (1UL)
 
#define GPIOTE_INTENSET_IN7_Pos   (7UL)
 
#define GPIOTE_INTENSET_IN7_Msk   (0x1UL << GPIOTE_INTENSET_IN7_Pos)
 
#define GPIOTE_INTENSET_IN7_Disabled   (0UL)
 
#define GPIOTE_INTENSET_IN7_Enabled   (1UL)
 
#define GPIOTE_INTENSET_IN7_Set   (1UL)
 
#define GPIOTE_INTENSET_IN6_Pos   (6UL)
 
#define GPIOTE_INTENSET_IN6_Msk   (0x1UL << GPIOTE_INTENSET_IN6_Pos)
 
#define GPIOTE_INTENSET_IN6_Disabled   (0UL)
 
#define GPIOTE_INTENSET_IN6_Enabled   (1UL)
 
#define GPIOTE_INTENSET_IN6_Set   (1UL)
 
#define GPIOTE_INTENSET_IN5_Pos   (5UL)
 
#define GPIOTE_INTENSET_IN5_Msk   (0x1UL << GPIOTE_INTENSET_IN5_Pos)
 
#define GPIOTE_INTENSET_IN5_Disabled   (0UL)
 
#define GPIOTE_INTENSET_IN5_Enabled   (1UL)
 
#define GPIOTE_INTENSET_IN5_Set   (1UL)
 
#define GPIOTE_INTENSET_IN4_Pos   (4UL)
 
#define GPIOTE_INTENSET_IN4_Msk   (0x1UL << GPIOTE_INTENSET_IN4_Pos)
 
#define GPIOTE_INTENSET_IN4_Disabled   (0UL)
 
#define GPIOTE_INTENSET_IN4_Enabled   (1UL)
 
#define GPIOTE_INTENSET_IN4_Set   (1UL)
 
#define GPIOTE_INTENSET_IN3_Pos   (3UL)
 
#define GPIOTE_INTENSET_IN3_Msk   (0x1UL << GPIOTE_INTENSET_IN3_Pos)
 
#define GPIOTE_INTENSET_IN3_Disabled   (0UL)
 
#define GPIOTE_INTENSET_IN3_Enabled   (1UL)
 
#define GPIOTE_INTENSET_IN3_Set   (1UL)
 
#define GPIOTE_INTENSET_IN2_Pos   (2UL)
 
#define GPIOTE_INTENSET_IN2_Msk   (0x1UL << GPIOTE_INTENSET_IN2_Pos)
 
#define GPIOTE_INTENSET_IN2_Disabled   (0UL)
 
#define GPIOTE_INTENSET_IN2_Enabled   (1UL)
 
#define GPIOTE_INTENSET_IN2_Set   (1UL)
 
#define GPIOTE_INTENSET_IN1_Pos   (1UL)
 
#define GPIOTE_INTENSET_IN1_Msk   (0x1UL << GPIOTE_INTENSET_IN1_Pos)
 
#define GPIOTE_INTENSET_IN1_Disabled   (0UL)
 
#define GPIOTE_INTENSET_IN1_Enabled   (1UL)
 
#define GPIOTE_INTENSET_IN1_Set   (1UL)
 
#define GPIOTE_INTENSET_IN0_Pos   (0UL)
 
#define GPIOTE_INTENSET_IN0_Msk   (0x1UL << GPIOTE_INTENSET_IN0_Pos)
 
#define GPIOTE_INTENSET_IN0_Disabled   (0UL)
 
#define GPIOTE_INTENSET_IN0_Enabled   (1UL)
 
#define GPIOTE_INTENSET_IN0_Set   (1UL)
 
#define GPIOTE_INTENCLR_PORT_Pos   (31UL)
 
#define GPIOTE_INTENCLR_PORT_Msk   (0x1UL << GPIOTE_INTENCLR_PORT_Pos)
 
#define GPIOTE_INTENCLR_PORT_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_PORT_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_PORT_Clear   (1UL)
 
#define GPIOTE_INTENCLR_IN7_Pos   (7UL)
 
#define GPIOTE_INTENCLR_IN7_Msk   (0x1UL << GPIOTE_INTENCLR_IN7_Pos)
 
#define GPIOTE_INTENCLR_IN7_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_IN7_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_IN7_Clear   (1UL)
 
#define GPIOTE_INTENCLR_IN6_Pos   (6UL)
 
#define GPIOTE_INTENCLR_IN6_Msk   (0x1UL << GPIOTE_INTENCLR_IN6_Pos)
 
#define GPIOTE_INTENCLR_IN6_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_IN6_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_IN6_Clear   (1UL)
 
#define GPIOTE_INTENCLR_IN5_Pos   (5UL)
 
#define GPIOTE_INTENCLR_IN5_Msk   (0x1UL << GPIOTE_INTENCLR_IN5_Pos)
 
#define GPIOTE_INTENCLR_IN5_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_IN5_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_IN5_Clear   (1UL)
 
#define GPIOTE_INTENCLR_IN4_Pos   (4UL)
 
#define GPIOTE_INTENCLR_IN4_Msk   (0x1UL << GPIOTE_INTENCLR_IN4_Pos)
 
#define GPIOTE_INTENCLR_IN4_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_IN4_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_IN4_Clear   (1UL)
 
#define GPIOTE_INTENCLR_IN3_Pos   (3UL)
 
#define GPIOTE_INTENCLR_IN3_Msk   (0x1UL << GPIOTE_INTENCLR_IN3_Pos)
 
#define GPIOTE_INTENCLR_IN3_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_IN3_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_IN3_Clear   (1UL)
 
#define GPIOTE_INTENCLR_IN2_Pos   (2UL)
 
#define GPIOTE_INTENCLR_IN2_Msk   (0x1UL << GPIOTE_INTENCLR_IN2_Pos)
 
#define GPIOTE_INTENCLR_IN2_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_IN2_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_IN2_Clear   (1UL)
 
#define GPIOTE_INTENCLR_IN1_Pos   (1UL)
 
#define GPIOTE_INTENCLR_IN1_Msk   (0x1UL << GPIOTE_INTENCLR_IN1_Pos)
 
#define GPIOTE_INTENCLR_IN1_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_IN1_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_IN1_Clear   (1UL)
 
#define GPIOTE_INTENCLR_IN0_Pos   (0UL)
 
#define GPIOTE_INTENCLR_IN0_Msk   (0x1UL << GPIOTE_INTENCLR_IN0_Pos)
 
#define GPIOTE_INTENCLR_IN0_Disabled   (0UL)
 
#define GPIOTE_INTENCLR_IN0_Enabled   (1UL)
 
#define GPIOTE_INTENCLR_IN0_Clear   (1UL)
 
#define GPIOTE_CONFIG_OUTINIT_Pos   (20UL)
 
#define GPIOTE_CONFIG_OUTINIT_Msk   (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos)
 
#define GPIOTE_CONFIG_OUTINIT_Low   (0UL)
 
#define GPIOTE_CONFIG_OUTINIT_High   (1UL)
 
#define GPIOTE_CONFIG_POLARITY_Pos   (16UL)
 
#define GPIOTE_CONFIG_POLARITY_Msk   (0x3UL << GPIOTE_CONFIG_POLARITY_Pos)
 
#define GPIOTE_CONFIG_POLARITY_None   (0UL)
 
#define GPIOTE_CONFIG_POLARITY_LoToHi   (1UL)
 
#define GPIOTE_CONFIG_POLARITY_HiToLo   (2UL)
 
#define GPIOTE_CONFIG_POLARITY_Toggle   (3UL)
 
#define GPIOTE_CONFIG_PSEL_Pos   (8UL)
 
#define GPIOTE_CONFIG_PSEL_Msk   (0x1FUL << GPIOTE_CONFIG_PSEL_Pos)
 
#define GPIOTE_CONFIG_MODE_Pos   (0UL)
 
#define GPIOTE_CONFIG_MODE_Msk   (0x3UL << GPIOTE_CONFIG_MODE_Pos)
 
#define GPIOTE_CONFIG_MODE_Disabled   (0UL)
 
#define GPIOTE_CONFIG_MODE_Event   (1UL)
 
#define GPIOTE_CONFIG_MODE_Task   (3UL)
 
#define I2S_INTEN_TXPTRUPD_Pos   (5UL)
 
#define I2S_INTEN_TXPTRUPD_Msk   (0x1UL << I2S_INTEN_TXPTRUPD_Pos)
 
#define I2S_INTEN_TXPTRUPD_Disabled   (0UL)
 
#define I2S_INTEN_TXPTRUPD_Enabled   (1UL)
 
#define I2S_INTEN_STOPPED_Pos   (2UL)
 
#define I2S_INTEN_STOPPED_Msk   (0x1UL << I2S_INTEN_STOPPED_Pos)
 
#define I2S_INTEN_STOPPED_Disabled   (0UL)
 
#define I2S_INTEN_STOPPED_Enabled   (1UL)
 
#define I2S_INTEN_RXPTRUPD_Pos   (1UL)
 
#define I2S_INTEN_RXPTRUPD_Msk   (0x1UL << I2S_INTEN_RXPTRUPD_Pos)
 
#define I2S_INTEN_RXPTRUPD_Disabled   (0UL)
 
#define I2S_INTEN_RXPTRUPD_Enabled   (1UL)
 
#define I2S_INTENSET_TXPTRUPD_Pos   (5UL)
 
#define I2S_INTENSET_TXPTRUPD_Msk   (0x1UL << I2S_INTENSET_TXPTRUPD_Pos)
 
#define I2S_INTENSET_TXPTRUPD_Disabled   (0UL)
 
#define I2S_INTENSET_TXPTRUPD_Enabled   (1UL)
 
#define I2S_INTENSET_TXPTRUPD_Set   (1UL)
 
#define I2S_INTENSET_STOPPED_Pos   (2UL)
 
#define I2S_INTENSET_STOPPED_Msk   (0x1UL << I2S_INTENSET_STOPPED_Pos)
 
#define I2S_INTENSET_STOPPED_Disabled   (0UL)
 
#define I2S_INTENSET_STOPPED_Enabled   (1UL)
 
#define I2S_INTENSET_STOPPED_Set   (1UL)
 
#define I2S_INTENSET_RXPTRUPD_Pos   (1UL)
 
#define I2S_INTENSET_RXPTRUPD_Msk   (0x1UL << I2S_INTENSET_RXPTRUPD_Pos)
 
#define I2S_INTENSET_RXPTRUPD_Disabled   (0UL)
 
#define I2S_INTENSET_RXPTRUPD_Enabled   (1UL)
 
#define I2S_INTENSET_RXPTRUPD_Set   (1UL)
 
#define I2S_INTENCLR_TXPTRUPD_Pos   (5UL)
 
#define I2S_INTENCLR_TXPTRUPD_Msk   (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos)
 
#define I2S_INTENCLR_TXPTRUPD_Disabled   (0UL)
 
#define I2S_INTENCLR_TXPTRUPD_Enabled   (1UL)
 
#define I2S_INTENCLR_TXPTRUPD_Clear   (1UL)
 
#define I2S_INTENCLR_STOPPED_Pos   (2UL)
 
#define I2S_INTENCLR_STOPPED_Msk   (0x1UL << I2S_INTENCLR_STOPPED_Pos)
 
#define I2S_INTENCLR_STOPPED_Disabled   (0UL)
 
#define I2S_INTENCLR_STOPPED_Enabled   (1UL)
 
#define I2S_INTENCLR_STOPPED_Clear   (1UL)
 
#define I2S_INTENCLR_RXPTRUPD_Pos   (1UL)
 
#define I2S_INTENCLR_RXPTRUPD_Msk   (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos)
 
#define I2S_INTENCLR_RXPTRUPD_Disabled   (0UL)
 
#define I2S_INTENCLR_RXPTRUPD_Enabled   (1UL)
 
#define I2S_INTENCLR_RXPTRUPD_Clear   (1UL)
 
#define I2S_ENABLE_ENABLE_Pos   (0UL)
 
#define I2S_ENABLE_ENABLE_Msk   (0x1UL << I2S_ENABLE_ENABLE_Pos)
 
#define I2S_ENABLE_ENABLE_Disabled   (0UL)
 
#define I2S_ENABLE_ENABLE_Enabled   (1UL)
 
#define I2S_CONFIG_MODE_MODE_Pos   (0UL)
 
#define I2S_CONFIG_MODE_MODE_Msk   (0x1UL << I2S_CONFIG_MODE_MODE_Pos)
 
#define I2S_CONFIG_MODE_MODE_Master   (0UL)
 
#define I2S_CONFIG_MODE_MODE_Slave   (1UL)
 
#define I2S_CONFIG_RXEN_RXEN_Pos   (0UL)
 
#define I2S_CONFIG_RXEN_RXEN_Msk   (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos)
 
#define I2S_CONFIG_RXEN_RXEN_Disabled   (0UL)
 
#define I2S_CONFIG_RXEN_RXEN_Enabled   (1UL)
 
#define I2S_CONFIG_TXEN_TXEN_Pos   (0UL)
 
#define I2S_CONFIG_TXEN_TXEN_Msk   (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos)
 
#define I2S_CONFIG_TXEN_TXEN_Disabled   (0UL)
 
#define I2S_CONFIG_TXEN_TXEN_Enabled   (1UL)
 
#define I2S_CONFIG_MCKEN_MCKEN_Pos   (0UL)
 
#define I2S_CONFIG_MCKEN_MCKEN_Msk   (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos)
 
#define I2S_CONFIG_MCKEN_MCKEN_Disabled   (0UL)
 
#define I2S_CONFIG_MCKEN_MCKEN_Enabled   (1UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos   (0UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk   (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125   (0x020C0000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63   (0x04100000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42   (0x06000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32   (0x08000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31   (0x08400000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30   (0x08800000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23   (0x0B000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21   (0x0C000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16   (0x10000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15   (0x11000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11   (0x16000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10   (0x18000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8   (0x20000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6   (0x28000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5   (0x30000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4   (0x40000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3   (0x50000000UL)
 
#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2   (0x80000000UL)
 
#define I2S_CONFIG_RATIO_RATIO_Pos   (0UL)
 
#define I2S_CONFIG_RATIO_RATIO_Msk   (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos)
 
#define I2S_CONFIG_RATIO_RATIO_32X   (0UL)
 
#define I2S_CONFIG_RATIO_RATIO_48X   (1UL)
 
#define I2S_CONFIG_RATIO_RATIO_64X   (2UL)
 
#define I2S_CONFIG_RATIO_RATIO_96X   (3UL)
 
#define I2S_CONFIG_RATIO_RATIO_128X   (4UL)
 
#define I2S_CONFIG_RATIO_RATIO_192X   (5UL)
 
#define I2S_CONFIG_RATIO_RATIO_256X   (6UL)
 
#define I2S_CONFIG_RATIO_RATIO_384X   (7UL)
 
#define I2S_CONFIG_RATIO_RATIO_512X   (8UL)
 
#define I2S_CONFIG_SWIDTH_SWIDTH_Pos   (0UL)
 
#define I2S_CONFIG_SWIDTH_SWIDTH_Msk   (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos)
 
#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit   (0UL)
 
#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit   (1UL)
 
#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit   (2UL)
 
#define I2S_CONFIG_ALIGN_ALIGN_Pos   (0UL)
 
#define I2S_CONFIG_ALIGN_ALIGN_Msk   (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos)
 
#define I2S_CONFIG_ALIGN_ALIGN_Left   (0UL)
 
#define I2S_CONFIG_ALIGN_ALIGN_Right   (1UL)
 
#define I2S_CONFIG_FORMAT_FORMAT_Pos   (0UL)
 
#define I2S_CONFIG_FORMAT_FORMAT_Msk   (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos)
 
#define I2S_CONFIG_FORMAT_FORMAT_I2S   (0UL)
 
#define I2S_CONFIG_FORMAT_FORMAT_Aligned   (1UL)
 
#define I2S_CONFIG_CHANNELS_CHANNELS_Pos   (0UL)
 
#define I2S_CONFIG_CHANNELS_CHANNELS_Msk   (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos)
 
#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo   (0UL)
 
#define I2S_CONFIG_CHANNELS_CHANNELS_Left   (1UL)
 
#define I2S_CONFIG_CHANNELS_CHANNELS_Right   (2UL)
 
#define I2S_RXD_PTR_PTR_Pos   (0UL)
 
#define I2S_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos)
 
#define I2S_TXD_PTR_PTR_Pos   (0UL)
 
#define I2S_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos)
 
#define I2S_RXTXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define I2S_RXTXD_MAXCNT_MAXCNT_Msk   (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos)
 
#define I2S_PSEL_MCK_CONNECT_Pos   (31UL)
 
#define I2S_PSEL_MCK_CONNECT_Msk   (0x1UL << I2S_PSEL_MCK_CONNECT_Pos)
 
#define I2S_PSEL_MCK_CONNECT_Connected   (0UL)
 
#define I2S_PSEL_MCK_CONNECT_Disconnected   (1UL)
 
#define I2S_PSEL_MCK_PIN_Pos   (0UL)
 
#define I2S_PSEL_MCK_PIN_Msk   (0x1FUL << I2S_PSEL_MCK_PIN_Pos)
 
#define I2S_PSEL_SCK_CONNECT_Pos   (31UL)
 
#define I2S_PSEL_SCK_CONNECT_Msk   (0x1UL << I2S_PSEL_SCK_CONNECT_Pos)
 
#define I2S_PSEL_SCK_CONNECT_Connected   (0UL)
 
#define I2S_PSEL_SCK_CONNECT_Disconnected   (1UL)
 
#define I2S_PSEL_SCK_PIN_Pos   (0UL)
 
#define I2S_PSEL_SCK_PIN_Msk   (0x1FUL << I2S_PSEL_SCK_PIN_Pos)
 
#define I2S_PSEL_LRCK_CONNECT_Pos   (31UL)
 
#define I2S_PSEL_LRCK_CONNECT_Msk   (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos)
 
#define I2S_PSEL_LRCK_CONNECT_Connected   (0UL)
 
#define I2S_PSEL_LRCK_CONNECT_Disconnected   (1UL)
 
#define I2S_PSEL_LRCK_PIN_Pos   (0UL)
 
#define I2S_PSEL_LRCK_PIN_Msk   (0x1FUL << I2S_PSEL_LRCK_PIN_Pos)
 
#define I2S_PSEL_SDIN_CONNECT_Pos   (31UL)
 
#define I2S_PSEL_SDIN_CONNECT_Msk   (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos)
 
#define I2S_PSEL_SDIN_CONNECT_Connected   (0UL)
 
#define I2S_PSEL_SDIN_CONNECT_Disconnected   (1UL)
 
#define I2S_PSEL_SDIN_PIN_Pos   (0UL)
 
#define I2S_PSEL_SDIN_PIN_Msk   (0x1FUL << I2S_PSEL_SDIN_PIN_Pos)
 
#define I2S_PSEL_SDOUT_CONNECT_Pos   (31UL)
 
#define I2S_PSEL_SDOUT_CONNECT_Msk   (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos)
 
#define I2S_PSEL_SDOUT_CONNECT_Connected   (0UL)
 
#define I2S_PSEL_SDOUT_CONNECT_Disconnected   (1UL)
 
#define I2S_PSEL_SDOUT_PIN_Pos   (0UL)
 
#define I2S_PSEL_SDOUT_PIN_Msk   (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos)
 
#define LPCOMP_SHORTS_CROSS_STOP_Pos   (4UL)
 
#define LPCOMP_SHORTS_CROSS_STOP_Msk   (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos)
 
#define LPCOMP_SHORTS_CROSS_STOP_Disabled   (0UL)
 
#define LPCOMP_SHORTS_CROSS_STOP_Enabled   (1UL)
 
#define LPCOMP_SHORTS_UP_STOP_Pos   (3UL)
 
#define LPCOMP_SHORTS_UP_STOP_Msk   (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos)
 
#define LPCOMP_SHORTS_UP_STOP_Disabled   (0UL)
 
#define LPCOMP_SHORTS_UP_STOP_Enabled   (1UL)
 
#define LPCOMP_SHORTS_DOWN_STOP_Pos   (2UL)
 
#define LPCOMP_SHORTS_DOWN_STOP_Msk   (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos)
 
#define LPCOMP_SHORTS_DOWN_STOP_Disabled   (0UL)
 
#define LPCOMP_SHORTS_DOWN_STOP_Enabled   (1UL)
 
#define LPCOMP_SHORTS_READY_STOP_Pos   (1UL)
 
#define LPCOMP_SHORTS_READY_STOP_Msk   (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos)
 
#define LPCOMP_SHORTS_READY_STOP_Disabled   (0UL)
 
#define LPCOMP_SHORTS_READY_STOP_Enabled   (1UL)
 
#define LPCOMP_SHORTS_READY_SAMPLE_Pos   (0UL)
 
#define LPCOMP_SHORTS_READY_SAMPLE_Msk   (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos)
 
#define LPCOMP_SHORTS_READY_SAMPLE_Disabled   (0UL)
 
#define LPCOMP_SHORTS_READY_SAMPLE_Enabled   (1UL)
 
#define LPCOMP_INTENSET_CROSS_Pos   (3UL)
 
#define LPCOMP_INTENSET_CROSS_Msk   (0x1UL << LPCOMP_INTENSET_CROSS_Pos)
 
#define LPCOMP_INTENSET_CROSS_Disabled   (0UL)
 
#define LPCOMP_INTENSET_CROSS_Enabled   (1UL)
 
#define LPCOMP_INTENSET_CROSS_Set   (1UL)
 
#define LPCOMP_INTENSET_UP_Pos   (2UL)
 
#define LPCOMP_INTENSET_UP_Msk   (0x1UL << LPCOMP_INTENSET_UP_Pos)
 
#define LPCOMP_INTENSET_UP_Disabled   (0UL)
 
#define LPCOMP_INTENSET_UP_Enabled   (1UL)
 
#define LPCOMP_INTENSET_UP_Set   (1UL)
 
#define LPCOMP_INTENSET_DOWN_Pos   (1UL)
 
#define LPCOMP_INTENSET_DOWN_Msk   (0x1UL << LPCOMP_INTENSET_DOWN_Pos)
 
#define LPCOMP_INTENSET_DOWN_Disabled   (0UL)
 
#define LPCOMP_INTENSET_DOWN_Enabled   (1UL)
 
#define LPCOMP_INTENSET_DOWN_Set   (1UL)
 
#define LPCOMP_INTENSET_READY_Pos   (0UL)
 
#define LPCOMP_INTENSET_READY_Msk   (0x1UL << LPCOMP_INTENSET_READY_Pos)
 
#define LPCOMP_INTENSET_READY_Disabled   (0UL)
 
#define LPCOMP_INTENSET_READY_Enabled   (1UL)
 
#define LPCOMP_INTENSET_READY_Set   (1UL)
 
#define LPCOMP_INTENCLR_CROSS_Pos   (3UL)
 
#define LPCOMP_INTENCLR_CROSS_Msk   (0x1UL << LPCOMP_INTENCLR_CROSS_Pos)
 
#define LPCOMP_INTENCLR_CROSS_Disabled   (0UL)
 
#define LPCOMP_INTENCLR_CROSS_Enabled   (1UL)
 
#define LPCOMP_INTENCLR_CROSS_Clear   (1UL)
 
#define LPCOMP_INTENCLR_UP_Pos   (2UL)
 
#define LPCOMP_INTENCLR_UP_Msk   (0x1UL << LPCOMP_INTENCLR_UP_Pos)
 
#define LPCOMP_INTENCLR_UP_Disabled   (0UL)
 
#define LPCOMP_INTENCLR_UP_Enabled   (1UL)
 
#define LPCOMP_INTENCLR_UP_Clear   (1UL)
 
#define LPCOMP_INTENCLR_DOWN_Pos   (1UL)
 
#define LPCOMP_INTENCLR_DOWN_Msk   (0x1UL << LPCOMP_INTENCLR_DOWN_Pos)
 
#define LPCOMP_INTENCLR_DOWN_Disabled   (0UL)
 
#define LPCOMP_INTENCLR_DOWN_Enabled   (1UL)
 
#define LPCOMP_INTENCLR_DOWN_Clear   (1UL)
 
#define LPCOMP_INTENCLR_READY_Pos   (0UL)
 
#define LPCOMP_INTENCLR_READY_Msk   (0x1UL << LPCOMP_INTENCLR_READY_Pos)
 
#define LPCOMP_INTENCLR_READY_Disabled   (0UL)
 
#define LPCOMP_INTENCLR_READY_Enabled   (1UL)
 
#define LPCOMP_INTENCLR_READY_Clear   (1UL)
 
#define LPCOMP_RESULT_RESULT_Pos   (0UL)
 
#define LPCOMP_RESULT_RESULT_Msk   (0x1UL << LPCOMP_RESULT_RESULT_Pos)
 
#define LPCOMP_RESULT_RESULT_Below   (0UL)
 
#define LPCOMP_RESULT_RESULT_Above   (1UL)
 
#define LPCOMP_ENABLE_ENABLE_Pos   (0UL)
 
#define LPCOMP_ENABLE_ENABLE_Msk   (0x3UL << LPCOMP_ENABLE_ENABLE_Pos)
 
#define LPCOMP_ENABLE_ENABLE_Disabled   (0UL)
 
#define LPCOMP_ENABLE_ENABLE_Enabled   (1UL)
 
#define LPCOMP_PSEL_PSEL_Pos   (0UL)
 
#define LPCOMP_PSEL_PSEL_Msk   (0x7UL << LPCOMP_PSEL_PSEL_Pos)
 
#define LPCOMP_PSEL_PSEL_AnalogInput0   (0UL)
 
#define LPCOMP_PSEL_PSEL_AnalogInput1   (1UL)
 
#define LPCOMP_PSEL_PSEL_AnalogInput2   (2UL)
 
#define LPCOMP_PSEL_PSEL_AnalogInput3   (3UL)
 
#define LPCOMP_PSEL_PSEL_AnalogInput4   (4UL)
 
#define LPCOMP_PSEL_PSEL_AnalogInput5   (5UL)
 
#define LPCOMP_PSEL_PSEL_AnalogInput6   (6UL)
 
#define LPCOMP_PSEL_PSEL_AnalogInput7   (7UL)
 
#define LPCOMP_REFSEL_REFSEL_Pos   (0UL)
 
#define LPCOMP_REFSEL_REFSEL_Msk   (0xFUL << LPCOMP_REFSEL_REFSEL_Pos)
 
#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd   (0UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd   (1UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd   (2UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd   (3UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd   (4UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd   (5UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd   (6UL)
 
#define LPCOMP_REFSEL_REFSEL_ARef   (7UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd   (8UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd   (9UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd   (10UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd   (11UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd   (12UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd   (13UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd   (14UL)
 
#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd   (15UL)
 
#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos   (0UL)
 
#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk   (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos)
 
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0   (0UL)
 
#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1   (1UL)
 
#define LPCOMP_ANADETECT_ANADETECT_Pos   (0UL)
 
#define LPCOMP_ANADETECT_ANADETECT_Msk   (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos)
 
#define LPCOMP_ANADETECT_ANADETECT_Cross   (0UL)
 
#define LPCOMP_ANADETECT_ANADETECT_Up   (1UL)
 
#define LPCOMP_ANADETECT_ANADETECT_Down   (2UL)
 
#define LPCOMP_HYST_HYST_Pos   (0UL)
 
#define LPCOMP_HYST_HYST_Msk   (0x1UL << LPCOMP_HYST_HYST_Pos)
 
#define LPCOMP_HYST_HYST_NoHyst   (0UL)
 
#define LPCOMP_HYST_HYST_Hyst50mV   (1UL)
 
#define MWU_INTEN_PREGION1RA_Pos   (27UL)
 
#define MWU_INTEN_PREGION1RA_Msk   (0x1UL << MWU_INTEN_PREGION1RA_Pos)
 
#define MWU_INTEN_PREGION1RA_Disabled   (0UL)
 
#define MWU_INTEN_PREGION1RA_Enabled   (1UL)
 
#define MWU_INTEN_PREGION1WA_Pos   (26UL)
 
#define MWU_INTEN_PREGION1WA_Msk   (0x1UL << MWU_INTEN_PREGION1WA_Pos)
 
#define MWU_INTEN_PREGION1WA_Disabled   (0UL)
 
#define MWU_INTEN_PREGION1WA_Enabled   (1UL)
 
#define MWU_INTEN_PREGION0RA_Pos   (25UL)
 
#define MWU_INTEN_PREGION0RA_Msk   (0x1UL << MWU_INTEN_PREGION0RA_Pos)
 
#define MWU_INTEN_PREGION0RA_Disabled   (0UL)
 
#define MWU_INTEN_PREGION0RA_Enabled   (1UL)
 
#define MWU_INTEN_PREGION0WA_Pos   (24UL)
 
#define MWU_INTEN_PREGION0WA_Msk   (0x1UL << MWU_INTEN_PREGION0WA_Pos)
 
#define MWU_INTEN_PREGION0WA_Disabled   (0UL)
 
#define MWU_INTEN_PREGION0WA_Enabled   (1UL)
 
#define MWU_INTEN_REGION3RA_Pos   (7UL)
 
#define MWU_INTEN_REGION3RA_Msk   (0x1UL << MWU_INTEN_REGION3RA_Pos)
 
#define MWU_INTEN_REGION3RA_Disabled   (0UL)
 
#define MWU_INTEN_REGION3RA_Enabled   (1UL)
 
#define MWU_INTEN_REGION3WA_Pos   (6UL)
 
#define MWU_INTEN_REGION3WA_Msk   (0x1UL << MWU_INTEN_REGION3WA_Pos)
 
#define MWU_INTEN_REGION3WA_Disabled   (0UL)
 
#define MWU_INTEN_REGION3WA_Enabled   (1UL)
 
#define MWU_INTEN_REGION2RA_Pos   (5UL)
 
#define MWU_INTEN_REGION2RA_Msk   (0x1UL << MWU_INTEN_REGION2RA_Pos)
 
#define MWU_INTEN_REGION2RA_Disabled   (0UL)
 
#define MWU_INTEN_REGION2RA_Enabled   (1UL)
 
#define MWU_INTEN_REGION2WA_Pos   (4UL)
 
#define MWU_INTEN_REGION2WA_Msk   (0x1UL << MWU_INTEN_REGION2WA_Pos)
 
#define MWU_INTEN_REGION2WA_Disabled   (0UL)
 
#define MWU_INTEN_REGION2WA_Enabled   (1UL)
 
#define MWU_INTEN_REGION1RA_Pos   (3UL)
 
#define MWU_INTEN_REGION1RA_Msk   (0x1UL << MWU_INTEN_REGION1RA_Pos)
 
#define MWU_INTEN_REGION1RA_Disabled   (0UL)
 
#define MWU_INTEN_REGION1RA_Enabled   (1UL)
 
#define MWU_INTEN_REGION1WA_Pos   (2UL)
 
#define MWU_INTEN_REGION1WA_Msk   (0x1UL << MWU_INTEN_REGION1WA_Pos)
 
#define MWU_INTEN_REGION1WA_Disabled   (0UL)
 
#define MWU_INTEN_REGION1WA_Enabled   (1UL)
 
#define MWU_INTEN_REGION0RA_Pos   (1UL)
 
#define MWU_INTEN_REGION0RA_Msk   (0x1UL << MWU_INTEN_REGION0RA_Pos)
 
#define MWU_INTEN_REGION0RA_Disabled   (0UL)
 
#define MWU_INTEN_REGION0RA_Enabled   (1UL)
 
#define MWU_INTEN_REGION0WA_Pos   (0UL)
 
#define MWU_INTEN_REGION0WA_Msk   (0x1UL << MWU_INTEN_REGION0WA_Pos)
 
#define MWU_INTEN_REGION0WA_Disabled   (0UL)
 
#define MWU_INTEN_REGION0WA_Enabled   (1UL)
 
#define MWU_INTENSET_PREGION1RA_Pos   (27UL)
 
#define MWU_INTENSET_PREGION1RA_Msk   (0x1UL << MWU_INTENSET_PREGION1RA_Pos)
 
#define MWU_INTENSET_PREGION1RA_Disabled   (0UL)
 
#define MWU_INTENSET_PREGION1RA_Enabled   (1UL)
 
#define MWU_INTENSET_PREGION1RA_Set   (1UL)
 
#define MWU_INTENSET_PREGION1WA_Pos   (26UL)
 
#define MWU_INTENSET_PREGION1WA_Msk   (0x1UL << MWU_INTENSET_PREGION1WA_Pos)
 
#define MWU_INTENSET_PREGION1WA_Disabled   (0UL)
 
#define MWU_INTENSET_PREGION1WA_Enabled   (1UL)
 
#define MWU_INTENSET_PREGION1WA_Set   (1UL)
 
#define MWU_INTENSET_PREGION0RA_Pos   (25UL)
 
#define MWU_INTENSET_PREGION0RA_Msk   (0x1UL << MWU_INTENSET_PREGION0RA_Pos)
 
#define MWU_INTENSET_PREGION0RA_Disabled   (0UL)
 
#define MWU_INTENSET_PREGION0RA_Enabled   (1UL)
 
#define MWU_INTENSET_PREGION0RA_Set   (1UL)
 
#define MWU_INTENSET_PREGION0WA_Pos   (24UL)
 
#define MWU_INTENSET_PREGION0WA_Msk   (0x1UL << MWU_INTENSET_PREGION0WA_Pos)
 
#define MWU_INTENSET_PREGION0WA_Disabled   (0UL)
 
#define MWU_INTENSET_PREGION0WA_Enabled   (1UL)
 
#define MWU_INTENSET_PREGION0WA_Set   (1UL)
 
#define MWU_INTENSET_REGION3RA_Pos   (7UL)
 
#define MWU_INTENSET_REGION3RA_Msk   (0x1UL << MWU_INTENSET_REGION3RA_Pos)
 
#define MWU_INTENSET_REGION3RA_Disabled   (0UL)
 
#define MWU_INTENSET_REGION3RA_Enabled   (1UL)
 
#define MWU_INTENSET_REGION3RA_Set   (1UL)
 
#define MWU_INTENSET_REGION3WA_Pos   (6UL)
 
#define MWU_INTENSET_REGION3WA_Msk   (0x1UL << MWU_INTENSET_REGION3WA_Pos)
 
#define MWU_INTENSET_REGION3WA_Disabled   (0UL)
 
#define MWU_INTENSET_REGION3WA_Enabled   (1UL)
 
#define MWU_INTENSET_REGION3WA_Set   (1UL)
 
#define MWU_INTENSET_REGION2RA_Pos   (5UL)
 
#define MWU_INTENSET_REGION2RA_Msk   (0x1UL << MWU_INTENSET_REGION2RA_Pos)
 
#define MWU_INTENSET_REGION2RA_Disabled   (0UL)
 
#define MWU_INTENSET_REGION2RA_Enabled   (1UL)
 
#define MWU_INTENSET_REGION2RA_Set   (1UL)
 
#define MWU_INTENSET_REGION2WA_Pos   (4UL)
 
#define MWU_INTENSET_REGION2WA_Msk   (0x1UL << MWU_INTENSET_REGION2WA_Pos)
 
#define MWU_INTENSET_REGION2WA_Disabled   (0UL)
 
#define MWU_INTENSET_REGION2WA_Enabled   (1UL)
 
#define MWU_INTENSET_REGION2WA_Set   (1UL)
 
#define MWU_INTENSET_REGION1RA_Pos   (3UL)
 
#define MWU_INTENSET_REGION1RA_Msk   (0x1UL << MWU_INTENSET_REGION1RA_Pos)
 
#define MWU_INTENSET_REGION1RA_Disabled   (0UL)
 
#define MWU_INTENSET_REGION1RA_Enabled   (1UL)
 
#define MWU_INTENSET_REGION1RA_Set   (1UL)
 
#define MWU_INTENSET_REGION1WA_Pos   (2UL)
 
#define MWU_INTENSET_REGION1WA_Msk   (0x1UL << MWU_INTENSET_REGION1WA_Pos)
 
#define MWU_INTENSET_REGION1WA_Disabled   (0UL)
 
#define MWU_INTENSET_REGION1WA_Enabled   (1UL)
 
#define MWU_INTENSET_REGION1WA_Set   (1UL)
 
#define MWU_INTENSET_REGION0RA_Pos   (1UL)
 
#define MWU_INTENSET_REGION0RA_Msk   (0x1UL << MWU_INTENSET_REGION0RA_Pos)
 
#define MWU_INTENSET_REGION0RA_Disabled   (0UL)
 
#define MWU_INTENSET_REGION0RA_Enabled   (1UL)
 
#define MWU_INTENSET_REGION0RA_Set   (1UL)
 
#define MWU_INTENSET_REGION0WA_Pos   (0UL)
 
#define MWU_INTENSET_REGION0WA_Msk   (0x1UL << MWU_INTENSET_REGION0WA_Pos)
 
#define MWU_INTENSET_REGION0WA_Disabled   (0UL)
 
#define MWU_INTENSET_REGION0WA_Enabled   (1UL)
 
#define MWU_INTENSET_REGION0WA_Set   (1UL)
 
#define MWU_INTENCLR_PREGION1RA_Pos   (27UL)
 
#define MWU_INTENCLR_PREGION1RA_Msk   (0x1UL << MWU_INTENCLR_PREGION1RA_Pos)
 
#define MWU_INTENCLR_PREGION1RA_Disabled   (0UL)
 
#define MWU_INTENCLR_PREGION1RA_Enabled   (1UL)
 
#define MWU_INTENCLR_PREGION1RA_Clear   (1UL)
 
#define MWU_INTENCLR_PREGION1WA_Pos   (26UL)
 
#define MWU_INTENCLR_PREGION1WA_Msk   (0x1UL << MWU_INTENCLR_PREGION1WA_Pos)
 
#define MWU_INTENCLR_PREGION1WA_Disabled   (0UL)
 
#define MWU_INTENCLR_PREGION1WA_Enabled   (1UL)
 
#define MWU_INTENCLR_PREGION1WA_Clear   (1UL)
 
#define MWU_INTENCLR_PREGION0RA_Pos   (25UL)
 
#define MWU_INTENCLR_PREGION0RA_Msk   (0x1UL << MWU_INTENCLR_PREGION0RA_Pos)
 
#define MWU_INTENCLR_PREGION0RA_Disabled   (0UL)
 
#define MWU_INTENCLR_PREGION0RA_Enabled   (1UL)
 
#define MWU_INTENCLR_PREGION0RA_Clear   (1UL)
 
#define MWU_INTENCLR_PREGION0WA_Pos   (24UL)
 
#define MWU_INTENCLR_PREGION0WA_Msk   (0x1UL << MWU_INTENCLR_PREGION0WA_Pos)
 
#define MWU_INTENCLR_PREGION0WA_Disabled   (0UL)
 
#define MWU_INTENCLR_PREGION0WA_Enabled   (1UL)
 
#define MWU_INTENCLR_PREGION0WA_Clear   (1UL)
 
#define MWU_INTENCLR_REGION3RA_Pos   (7UL)
 
#define MWU_INTENCLR_REGION3RA_Msk   (0x1UL << MWU_INTENCLR_REGION3RA_Pos)
 
#define MWU_INTENCLR_REGION3RA_Disabled   (0UL)
 
#define MWU_INTENCLR_REGION3RA_Enabled   (1UL)
 
#define MWU_INTENCLR_REGION3RA_Clear   (1UL)
 
#define MWU_INTENCLR_REGION3WA_Pos   (6UL)
 
#define MWU_INTENCLR_REGION3WA_Msk   (0x1UL << MWU_INTENCLR_REGION3WA_Pos)
 
#define MWU_INTENCLR_REGION3WA_Disabled   (0UL)
 
#define MWU_INTENCLR_REGION3WA_Enabled   (1UL)
 
#define MWU_INTENCLR_REGION3WA_Clear   (1UL)
 
#define MWU_INTENCLR_REGION2RA_Pos   (5UL)
 
#define MWU_INTENCLR_REGION2RA_Msk   (0x1UL << MWU_INTENCLR_REGION2RA_Pos)
 
#define MWU_INTENCLR_REGION2RA_Disabled   (0UL)
 
#define MWU_INTENCLR_REGION2RA_Enabled   (1UL)
 
#define MWU_INTENCLR_REGION2RA_Clear   (1UL)
 
#define MWU_INTENCLR_REGION2WA_Pos   (4UL)
 
#define MWU_INTENCLR_REGION2WA_Msk   (0x1UL << MWU_INTENCLR_REGION2WA_Pos)
 
#define MWU_INTENCLR_REGION2WA_Disabled   (0UL)
 
#define MWU_INTENCLR_REGION2WA_Enabled   (1UL)
 
#define MWU_INTENCLR_REGION2WA_Clear   (1UL)
 
#define MWU_INTENCLR_REGION1RA_Pos   (3UL)
 
#define MWU_INTENCLR_REGION1RA_Msk   (0x1UL << MWU_INTENCLR_REGION1RA_Pos)
 
#define MWU_INTENCLR_REGION1RA_Disabled   (0UL)
 
#define MWU_INTENCLR_REGION1RA_Enabled   (1UL)
 
#define MWU_INTENCLR_REGION1RA_Clear   (1UL)
 
#define MWU_INTENCLR_REGION1WA_Pos   (2UL)
 
#define MWU_INTENCLR_REGION1WA_Msk   (0x1UL << MWU_INTENCLR_REGION1WA_Pos)
 
#define MWU_INTENCLR_REGION1WA_Disabled   (0UL)
 
#define MWU_INTENCLR_REGION1WA_Enabled   (1UL)
 
#define MWU_INTENCLR_REGION1WA_Clear   (1UL)
 
#define MWU_INTENCLR_REGION0RA_Pos   (1UL)
 
#define MWU_INTENCLR_REGION0RA_Msk   (0x1UL << MWU_INTENCLR_REGION0RA_Pos)
 
#define MWU_INTENCLR_REGION0RA_Disabled   (0UL)
 
#define MWU_INTENCLR_REGION0RA_Enabled   (1UL)
 
#define MWU_INTENCLR_REGION0RA_Clear   (1UL)
 
#define MWU_INTENCLR_REGION0WA_Pos   (0UL)
 
#define MWU_INTENCLR_REGION0WA_Msk   (0x1UL << MWU_INTENCLR_REGION0WA_Pos)
 
#define MWU_INTENCLR_REGION0WA_Disabled   (0UL)
 
#define MWU_INTENCLR_REGION0WA_Enabled   (1UL)
 
#define MWU_INTENCLR_REGION0WA_Clear   (1UL)
 
#define MWU_NMIEN_PREGION1RA_Pos   (27UL)
 
#define MWU_NMIEN_PREGION1RA_Msk   (0x1UL << MWU_NMIEN_PREGION1RA_Pos)
 
#define MWU_NMIEN_PREGION1RA_Disabled   (0UL)
 
#define MWU_NMIEN_PREGION1RA_Enabled   (1UL)
 
#define MWU_NMIEN_PREGION1WA_Pos   (26UL)
 
#define MWU_NMIEN_PREGION1WA_Msk   (0x1UL << MWU_NMIEN_PREGION1WA_Pos)
 
#define MWU_NMIEN_PREGION1WA_Disabled   (0UL)
 
#define MWU_NMIEN_PREGION1WA_Enabled   (1UL)
 
#define MWU_NMIEN_PREGION0RA_Pos   (25UL)
 
#define MWU_NMIEN_PREGION0RA_Msk   (0x1UL << MWU_NMIEN_PREGION0RA_Pos)
 
#define MWU_NMIEN_PREGION0RA_Disabled   (0UL)
 
#define MWU_NMIEN_PREGION0RA_Enabled   (1UL)
 
#define MWU_NMIEN_PREGION0WA_Pos   (24UL)
 
#define MWU_NMIEN_PREGION0WA_Msk   (0x1UL << MWU_NMIEN_PREGION0WA_Pos)
 
#define MWU_NMIEN_PREGION0WA_Disabled   (0UL)
 
#define MWU_NMIEN_PREGION0WA_Enabled   (1UL)
 
#define MWU_NMIEN_REGION3RA_Pos   (7UL)
 
#define MWU_NMIEN_REGION3RA_Msk   (0x1UL << MWU_NMIEN_REGION3RA_Pos)
 
#define MWU_NMIEN_REGION3RA_Disabled   (0UL)
 
#define MWU_NMIEN_REGION3RA_Enabled   (1UL)
 
#define MWU_NMIEN_REGION3WA_Pos   (6UL)
 
#define MWU_NMIEN_REGION3WA_Msk   (0x1UL << MWU_NMIEN_REGION3WA_Pos)
 
#define MWU_NMIEN_REGION3WA_Disabled   (0UL)
 
#define MWU_NMIEN_REGION3WA_Enabled   (1UL)
 
#define MWU_NMIEN_REGION2RA_Pos   (5UL)
 
#define MWU_NMIEN_REGION2RA_Msk   (0x1UL << MWU_NMIEN_REGION2RA_Pos)
 
#define MWU_NMIEN_REGION2RA_Disabled   (0UL)
 
#define MWU_NMIEN_REGION2RA_Enabled   (1UL)
 
#define MWU_NMIEN_REGION2WA_Pos   (4UL)
 
#define MWU_NMIEN_REGION2WA_Msk   (0x1UL << MWU_NMIEN_REGION2WA_Pos)
 
#define MWU_NMIEN_REGION2WA_Disabled   (0UL)
 
#define MWU_NMIEN_REGION2WA_Enabled   (1UL)
 
#define MWU_NMIEN_REGION1RA_Pos   (3UL)
 
#define MWU_NMIEN_REGION1RA_Msk   (0x1UL << MWU_NMIEN_REGION1RA_Pos)
 
#define MWU_NMIEN_REGION1RA_Disabled   (0UL)
 
#define MWU_NMIEN_REGION1RA_Enabled   (1UL)
 
#define MWU_NMIEN_REGION1WA_Pos   (2UL)
 
#define MWU_NMIEN_REGION1WA_Msk   (0x1UL << MWU_NMIEN_REGION1WA_Pos)
 
#define MWU_NMIEN_REGION1WA_Disabled   (0UL)
 
#define MWU_NMIEN_REGION1WA_Enabled   (1UL)
 
#define MWU_NMIEN_REGION0RA_Pos   (1UL)
 
#define MWU_NMIEN_REGION0RA_Msk   (0x1UL << MWU_NMIEN_REGION0RA_Pos)
 
#define MWU_NMIEN_REGION0RA_Disabled   (0UL)
 
#define MWU_NMIEN_REGION0RA_Enabled   (1UL)
 
#define MWU_NMIEN_REGION0WA_Pos   (0UL)
 
#define MWU_NMIEN_REGION0WA_Msk   (0x1UL << MWU_NMIEN_REGION0WA_Pos)
 
#define MWU_NMIEN_REGION0WA_Disabled   (0UL)
 
#define MWU_NMIEN_REGION0WA_Enabled   (1UL)
 
#define MWU_NMIENSET_PREGION1RA_Pos   (27UL)
 
#define MWU_NMIENSET_PREGION1RA_Msk   (0x1UL << MWU_NMIENSET_PREGION1RA_Pos)
 
#define MWU_NMIENSET_PREGION1RA_Disabled   (0UL)
 
#define MWU_NMIENSET_PREGION1RA_Enabled   (1UL)
 
#define MWU_NMIENSET_PREGION1RA_Set   (1UL)
 
#define MWU_NMIENSET_PREGION1WA_Pos   (26UL)
 
#define MWU_NMIENSET_PREGION1WA_Msk   (0x1UL << MWU_NMIENSET_PREGION1WA_Pos)
 
#define MWU_NMIENSET_PREGION1WA_Disabled   (0UL)
 
#define MWU_NMIENSET_PREGION1WA_Enabled   (1UL)
 
#define MWU_NMIENSET_PREGION1WA_Set   (1UL)
 
#define MWU_NMIENSET_PREGION0RA_Pos   (25UL)
 
#define MWU_NMIENSET_PREGION0RA_Msk   (0x1UL << MWU_NMIENSET_PREGION0RA_Pos)
 
#define MWU_NMIENSET_PREGION0RA_Disabled   (0UL)
 
#define MWU_NMIENSET_PREGION0RA_Enabled   (1UL)
 
#define MWU_NMIENSET_PREGION0RA_Set   (1UL)
 
#define MWU_NMIENSET_PREGION0WA_Pos   (24UL)
 
#define MWU_NMIENSET_PREGION0WA_Msk   (0x1UL << MWU_NMIENSET_PREGION0WA_Pos)
 
#define MWU_NMIENSET_PREGION0WA_Disabled   (0UL)
 
#define MWU_NMIENSET_PREGION0WA_Enabled   (1UL)
 
#define MWU_NMIENSET_PREGION0WA_Set   (1UL)
 
#define MWU_NMIENSET_REGION3RA_Pos   (7UL)
 
#define MWU_NMIENSET_REGION3RA_Msk   (0x1UL << MWU_NMIENSET_REGION3RA_Pos)
 
#define MWU_NMIENSET_REGION3RA_Disabled   (0UL)
 
#define MWU_NMIENSET_REGION3RA_Enabled   (1UL)
 
#define MWU_NMIENSET_REGION3RA_Set   (1UL)
 
#define MWU_NMIENSET_REGION3WA_Pos   (6UL)
 
#define MWU_NMIENSET_REGION3WA_Msk   (0x1UL << MWU_NMIENSET_REGION3WA_Pos)
 
#define MWU_NMIENSET_REGION3WA_Disabled   (0UL)
 
#define MWU_NMIENSET_REGION3WA_Enabled   (1UL)
 
#define MWU_NMIENSET_REGION3WA_Set   (1UL)
 
#define MWU_NMIENSET_REGION2RA_Pos   (5UL)
 
#define MWU_NMIENSET_REGION2RA_Msk   (0x1UL << MWU_NMIENSET_REGION2RA_Pos)
 
#define MWU_NMIENSET_REGION2RA_Disabled   (0UL)
 
#define MWU_NMIENSET_REGION2RA_Enabled   (1UL)
 
#define MWU_NMIENSET_REGION2RA_Set   (1UL)
 
#define MWU_NMIENSET_REGION2WA_Pos   (4UL)
 
#define MWU_NMIENSET_REGION2WA_Msk   (0x1UL << MWU_NMIENSET_REGION2WA_Pos)
 
#define MWU_NMIENSET_REGION2WA_Disabled   (0UL)
 
#define MWU_NMIENSET_REGION2WA_Enabled   (1UL)
 
#define MWU_NMIENSET_REGION2WA_Set   (1UL)
 
#define MWU_NMIENSET_REGION1RA_Pos   (3UL)
 
#define MWU_NMIENSET_REGION1RA_Msk   (0x1UL << MWU_NMIENSET_REGION1RA_Pos)
 
#define MWU_NMIENSET_REGION1RA_Disabled   (0UL)
 
#define MWU_NMIENSET_REGION1RA_Enabled   (1UL)
 
#define MWU_NMIENSET_REGION1RA_Set   (1UL)
 
#define MWU_NMIENSET_REGION1WA_Pos   (2UL)
 
#define MWU_NMIENSET_REGION1WA_Msk   (0x1UL << MWU_NMIENSET_REGION1WA_Pos)
 
#define MWU_NMIENSET_REGION1WA_Disabled   (0UL)
 
#define MWU_NMIENSET_REGION1WA_Enabled   (1UL)
 
#define MWU_NMIENSET_REGION1WA_Set   (1UL)
 
#define MWU_NMIENSET_REGION0RA_Pos   (1UL)
 
#define MWU_NMIENSET_REGION0RA_Msk   (0x1UL << MWU_NMIENSET_REGION0RA_Pos)
 
#define MWU_NMIENSET_REGION0RA_Disabled   (0UL)
 
#define MWU_NMIENSET_REGION0RA_Enabled   (1UL)
 
#define MWU_NMIENSET_REGION0RA_Set   (1UL)
 
#define MWU_NMIENSET_REGION0WA_Pos   (0UL)
 
#define MWU_NMIENSET_REGION0WA_Msk   (0x1UL << MWU_NMIENSET_REGION0WA_Pos)
 
#define MWU_NMIENSET_REGION0WA_Disabled   (0UL)
 
#define MWU_NMIENSET_REGION0WA_Enabled   (1UL)
 
#define MWU_NMIENSET_REGION0WA_Set   (1UL)
 
#define MWU_NMIENCLR_PREGION1RA_Pos   (27UL)
 
#define MWU_NMIENCLR_PREGION1RA_Msk   (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos)
 
#define MWU_NMIENCLR_PREGION1RA_Disabled   (0UL)
 
#define MWU_NMIENCLR_PREGION1RA_Enabled   (1UL)
 
#define MWU_NMIENCLR_PREGION1RA_Clear   (1UL)
 
#define MWU_NMIENCLR_PREGION1WA_Pos   (26UL)
 
#define MWU_NMIENCLR_PREGION1WA_Msk   (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos)
 
#define MWU_NMIENCLR_PREGION1WA_Disabled   (0UL)
 
#define MWU_NMIENCLR_PREGION1WA_Enabled   (1UL)
 
#define MWU_NMIENCLR_PREGION1WA_Clear   (1UL)
 
#define MWU_NMIENCLR_PREGION0RA_Pos   (25UL)
 
#define MWU_NMIENCLR_PREGION0RA_Msk   (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos)
 
#define MWU_NMIENCLR_PREGION0RA_Disabled   (0UL)
 
#define MWU_NMIENCLR_PREGION0RA_Enabled   (1UL)
 
#define MWU_NMIENCLR_PREGION0RA_Clear   (1UL)
 
#define MWU_NMIENCLR_PREGION0WA_Pos   (24UL)
 
#define MWU_NMIENCLR_PREGION0WA_Msk   (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos)
 
#define MWU_NMIENCLR_PREGION0WA_Disabled   (0UL)
 
#define MWU_NMIENCLR_PREGION0WA_Enabled   (1UL)
 
#define MWU_NMIENCLR_PREGION0WA_Clear   (1UL)
 
#define MWU_NMIENCLR_REGION3RA_Pos   (7UL)
 
#define MWU_NMIENCLR_REGION3RA_Msk   (0x1UL << MWU_NMIENCLR_REGION3RA_Pos)
 
#define MWU_NMIENCLR_REGION3RA_Disabled   (0UL)
 
#define MWU_NMIENCLR_REGION3RA_Enabled   (1UL)
 
#define MWU_NMIENCLR_REGION3RA_Clear   (1UL)
 
#define MWU_NMIENCLR_REGION3WA_Pos   (6UL)
 
#define MWU_NMIENCLR_REGION3WA_Msk   (0x1UL << MWU_NMIENCLR_REGION3WA_Pos)
 
#define MWU_NMIENCLR_REGION3WA_Disabled   (0UL)
 
#define MWU_NMIENCLR_REGION3WA_Enabled   (1UL)
 
#define MWU_NMIENCLR_REGION3WA_Clear   (1UL)
 
#define MWU_NMIENCLR_REGION2RA_Pos   (5UL)
 
#define MWU_NMIENCLR_REGION2RA_Msk   (0x1UL << MWU_NMIENCLR_REGION2RA_Pos)
 
#define MWU_NMIENCLR_REGION2RA_Disabled   (0UL)
 
#define MWU_NMIENCLR_REGION2RA_Enabled   (1UL)
 
#define MWU_NMIENCLR_REGION2RA_Clear   (1UL)
 
#define MWU_NMIENCLR_REGION2WA_Pos   (4UL)
 
#define MWU_NMIENCLR_REGION2WA_Msk   (0x1UL << MWU_NMIENCLR_REGION2WA_Pos)
 
#define MWU_NMIENCLR_REGION2WA_Disabled   (0UL)
 
#define MWU_NMIENCLR_REGION2WA_Enabled   (1UL)
 
#define MWU_NMIENCLR_REGION2WA_Clear   (1UL)
 
#define MWU_NMIENCLR_REGION1RA_Pos   (3UL)
 
#define MWU_NMIENCLR_REGION1RA_Msk   (0x1UL << MWU_NMIENCLR_REGION1RA_Pos)
 
#define MWU_NMIENCLR_REGION1RA_Disabled   (0UL)
 
#define MWU_NMIENCLR_REGION1RA_Enabled   (1UL)
 
#define MWU_NMIENCLR_REGION1RA_Clear   (1UL)
 
#define MWU_NMIENCLR_REGION1WA_Pos   (2UL)
 
#define MWU_NMIENCLR_REGION1WA_Msk   (0x1UL << MWU_NMIENCLR_REGION1WA_Pos)
 
#define MWU_NMIENCLR_REGION1WA_Disabled   (0UL)
 
#define MWU_NMIENCLR_REGION1WA_Enabled   (1UL)
 
#define MWU_NMIENCLR_REGION1WA_Clear   (1UL)
 
#define MWU_NMIENCLR_REGION0RA_Pos   (1UL)
 
#define MWU_NMIENCLR_REGION0RA_Msk   (0x1UL << MWU_NMIENCLR_REGION0RA_Pos)
 
#define MWU_NMIENCLR_REGION0RA_Disabled   (0UL)
 
#define MWU_NMIENCLR_REGION0RA_Enabled   (1UL)
 
#define MWU_NMIENCLR_REGION0RA_Clear   (1UL)
 
#define MWU_NMIENCLR_REGION0WA_Pos   (0UL)
 
#define MWU_NMIENCLR_REGION0WA_Msk   (0x1UL << MWU_NMIENCLR_REGION0WA_Pos)
 
#define MWU_NMIENCLR_REGION0WA_Disabled   (0UL)
 
#define MWU_NMIENCLR_REGION0WA_Enabled   (1UL)
 
#define MWU_NMIENCLR_REGION0WA_Clear   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR31_Pos   (31UL)
 
#define MWU_PERREGION_SUBSTATWA_SR31_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR31_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR30_Pos   (30UL)
 
#define MWU_PERREGION_SUBSTATWA_SR30_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR30_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR29_Pos   (29UL)
 
#define MWU_PERREGION_SUBSTATWA_SR29_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR29_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR28_Pos   (28UL)
 
#define MWU_PERREGION_SUBSTATWA_SR28_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR28_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR27_Pos   (27UL)
 
#define MWU_PERREGION_SUBSTATWA_SR27_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR27_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR26_Pos   (26UL)
 
#define MWU_PERREGION_SUBSTATWA_SR26_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR26_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR25_Pos   (25UL)
 
#define MWU_PERREGION_SUBSTATWA_SR25_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR25_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR24_Pos   (24UL)
 
#define MWU_PERREGION_SUBSTATWA_SR24_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR24_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR23_Pos   (23UL)
 
#define MWU_PERREGION_SUBSTATWA_SR23_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR23_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR22_Pos   (22UL)
 
#define MWU_PERREGION_SUBSTATWA_SR22_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR22_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR21_Pos   (21UL)
 
#define MWU_PERREGION_SUBSTATWA_SR21_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR21_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR20_Pos   (20UL)
 
#define MWU_PERREGION_SUBSTATWA_SR20_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR20_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR19_Pos   (19UL)
 
#define MWU_PERREGION_SUBSTATWA_SR19_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR19_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR18_Pos   (18UL)
 
#define MWU_PERREGION_SUBSTATWA_SR18_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR18_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR17_Pos   (17UL)
 
#define MWU_PERREGION_SUBSTATWA_SR17_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR17_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR16_Pos   (16UL)
 
#define MWU_PERREGION_SUBSTATWA_SR16_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR16_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR15_Pos   (15UL)
 
#define MWU_PERREGION_SUBSTATWA_SR15_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR15_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR14_Pos   (14UL)
 
#define MWU_PERREGION_SUBSTATWA_SR14_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR14_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR13_Pos   (13UL)
 
#define MWU_PERREGION_SUBSTATWA_SR13_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR13_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR12_Pos   (12UL)
 
#define MWU_PERREGION_SUBSTATWA_SR12_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR12_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR11_Pos   (11UL)
 
#define MWU_PERREGION_SUBSTATWA_SR11_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR11_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR10_Pos   (10UL)
 
#define MWU_PERREGION_SUBSTATWA_SR10_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR10_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR9_Pos   (9UL)
 
#define MWU_PERREGION_SUBSTATWA_SR9_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR9_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR8_Pos   (8UL)
 
#define MWU_PERREGION_SUBSTATWA_SR8_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR8_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR7_Pos   (7UL)
 
#define MWU_PERREGION_SUBSTATWA_SR7_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR7_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR6_Pos   (6UL)
 
#define MWU_PERREGION_SUBSTATWA_SR6_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR6_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR5_Pos   (5UL)
 
#define MWU_PERREGION_SUBSTATWA_SR5_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR5_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR4_Pos   (4UL)
 
#define MWU_PERREGION_SUBSTATWA_SR4_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR4_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR3_Pos   (3UL)
 
#define MWU_PERREGION_SUBSTATWA_SR3_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR3_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR2_Pos   (2UL)
 
#define MWU_PERREGION_SUBSTATWA_SR2_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR2_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR1_Pos   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR1_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR1_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATWA_SR0_Pos   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR0_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos)
 
#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATWA_SR0_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR31_Pos   (31UL)
 
#define MWU_PERREGION_SUBSTATRA_SR31_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR31_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR30_Pos   (30UL)
 
#define MWU_PERREGION_SUBSTATRA_SR30_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR30_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR29_Pos   (29UL)
 
#define MWU_PERREGION_SUBSTATRA_SR29_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR29_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR28_Pos   (28UL)
 
#define MWU_PERREGION_SUBSTATRA_SR28_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR28_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR27_Pos   (27UL)
 
#define MWU_PERREGION_SUBSTATRA_SR27_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR27_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR26_Pos   (26UL)
 
#define MWU_PERREGION_SUBSTATRA_SR26_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR26_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR25_Pos   (25UL)
 
#define MWU_PERREGION_SUBSTATRA_SR25_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR25_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR24_Pos   (24UL)
 
#define MWU_PERREGION_SUBSTATRA_SR24_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR24_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR23_Pos   (23UL)
 
#define MWU_PERREGION_SUBSTATRA_SR23_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR23_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR22_Pos   (22UL)
 
#define MWU_PERREGION_SUBSTATRA_SR22_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR22_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR21_Pos   (21UL)
 
#define MWU_PERREGION_SUBSTATRA_SR21_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR21_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR20_Pos   (20UL)
 
#define MWU_PERREGION_SUBSTATRA_SR20_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR20_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR19_Pos   (19UL)
 
#define MWU_PERREGION_SUBSTATRA_SR19_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR19_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR18_Pos   (18UL)
 
#define MWU_PERREGION_SUBSTATRA_SR18_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR18_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR17_Pos   (17UL)
 
#define MWU_PERREGION_SUBSTATRA_SR17_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR17_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR16_Pos   (16UL)
 
#define MWU_PERREGION_SUBSTATRA_SR16_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR16_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR15_Pos   (15UL)
 
#define MWU_PERREGION_SUBSTATRA_SR15_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR15_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR14_Pos   (14UL)
 
#define MWU_PERREGION_SUBSTATRA_SR14_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR14_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR13_Pos   (13UL)
 
#define MWU_PERREGION_SUBSTATRA_SR13_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR13_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR12_Pos   (12UL)
 
#define MWU_PERREGION_SUBSTATRA_SR12_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR12_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR11_Pos   (11UL)
 
#define MWU_PERREGION_SUBSTATRA_SR11_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR11_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR10_Pos   (10UL)
 
#define MWU_PERREGION_SUBSTATRA_SR10_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR10_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR9_Pos   (9UL)
 
#define MWU_PERREGION_SUBSTATRA_SR9_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR9_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR8_Pos   (8UL)
 
#define MWU_PERREGION_SUBSTATRA_SR8_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR8_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR7_Pos   (7UL)
 
#define MWU_PERREGION_SUBSTATRA_SR7_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR7_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR6_Pos   (6UL)
 
#define MWU_PERREGION_SUBSTATRA_SR6_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR6_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR5_Pos   (5UL)
 
#define MWU_PERREGION_SUBSTATRA_SR5_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR5_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR4_Pos   (4UL)
 
#define MWU_PERREGION_SUBSTATRA_SR4_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR4_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR3_Pos   (3UL)
 
#define MWU_PERREGION_SUBSTATRA_SR3_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR3_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR2_Pos   (2UL)
 
#define MWU_PERREGION_SUBSTATRA_SR2_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR2_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR1_Pos   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR1_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR1_Access   (1UL)
 
#define MWU_PERREGION_SUBSTATRA_SR0_Pos   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR0_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos)
 
#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess   (0UL)
 
#define MWU_PERREGION_SUBSTATRA_SR0_Access   (1UL)
 
#define MWU_REGIONEN_PRGN1RA_Pos   (27UL)
 
#define MWU_REGIONEN_PRGN1RA_Msk   (0x1UL << MWU_REGIONEN_PRGN1RA_Pos)
 
#define MWU_REGIONEN_PRGN1RA_Disable   (0UL)
 
#define MWU_REGIONEN_PRGN1RA_Enable   (1UL)
 
#define MWU_REGIONEN_PRGN1WA_Pos   (26UL)
 
#define MWU_REGIONEN_PRGN1WA_Msk   (0x1UL << MWU_REGIONEN_PRGN1WA_Pos)
 
#define MWU_REGIONEN_PRGN1WA_Disable   (0UL)
 
#define MWU_REGIONEN_PRGN1WA_Enable   (1UL)
 
#define MWU_REGIONEN_PRGN0RA_Pos   (25UL)
 
#define MWU_REGIONEN_PRGN0RA_Msk   (0x1UL << MWU_REGIONEN_PRGN0RA_Pos)
 
#define MWU_REGIONEN_PRGN0RA_Disable   (0UL)
 
#define MWU_REGIONEN_PRGN0RA_Enable   (1UL)
 
#define MWU_REGIONEN_PRGN0WA_Pos   (24UL)
 
#define MWU_REGIONEN_PRGN0WA_Msk   (0x1UL << MWU_REGIONEN_PRGN0WA_Pos)
 
#define MWU_REGIONEN_PRGN0WA_Disable   (0UL)
 
#define MWU_REGIONEN_PRGN0WA_Enable   (1UL)
 
#define MWU_REGIONEN_RGN3RA_Pos   (7UL)
 
#define MWU_REGIONEN_RGN3RA_Msk   (0x1UL << MWU_REGIONEN_RGN3RA_Pos)
 
#define MWU_REGIONEN_RGN3RA_Disable   (0UL)
 
#define MWU_REGIONEN_RGN3RA_Enable   (1UL)
 
#define MWU_REGIONEN_RGN3WA_Pos   (6UL)
 
#define MWU_REGIONEN_RGN3WA_Msk   (0x1UL << MWU_REGIONEN_RGN3WA_Pos)
 
#define MWU_REGIONEN_RGN3WA_Disable   (0UL)
 
#define MWU_REGIONEN_RGN3WA_Enable   (1UL)
 
#define MWU_REGIONEN_RGN2RA_Pos   (5UL)
 
#define MWU_REGIONEN_RGN2RA_Msk   (0x1UL << MWU_REGIONEN_RGN2RA_Pos)
 
#define MWU_REGIONEN_RGN2RA_Disable   (0UL)
 
#define MWU_REGIONEN_RGN2RA_Enable   (1UL)
 
#define MWU_REGIONEN_RGN2WA_Pos   (4UL)
 
#define MWU_REGIONEN_RGN2WA_Msk   (0x1UL << MWU_REGIONEN_RGN2WA_Pos)
 
#define MWU_REGIONEN_RGN2WA_Disable   (0UL)
 
#define MWU_REGIONEN_RGN2WA_Enable   (1UL)
 
#define MWU_REGIONEN_RGN1RA_Pos   (3UL)
 
#define MWU_REGIONEN_RGN1RA_Msk   (0x1UL << MWU_REGIONEN_RGN1RA_Pos)
 
#define MWU_REGIONEN_RGN1RA_Disable   (0UL)
 
#define MWU_REGIONEN_RGN1RA_Enable   (1UL)
 
#define MWU_REGIONEN_RGN1WA_Pos   (2UL)
 
#define MWU_REGIONEN_RGN1WA_Msk   (0x1UL << MWU_REGIONEN_RGN1WA_Pos)
 
#define MWU_REGIONEN_RGN1WA_Disable   (0UL)
 
#define MWU_REGIONEN_RGN1WA_Enable   (1UL)
 
#define MWU_REGIONEN_RGN0RA_Pos   (1UL)
 
#define MWU_REGIONEN_RGN0RA_Msk   (0x1UL << MWU_REGIONEN_RGN0RA_Pos)
 
#define MWU_REGIONEN_RGN0RA_Disable   (0UL)
 
#define MWU_REGIONEN_RGN0RA_Enable   (1UL)
 
#define MWU_REGIONEN_RGN0WA_Pos   (0UL)
 
#define MWU_REGIONEN_RGN0WA_Msk   (0x1UL << MWU_REGIONEN_RGN0WA_Pos)
 
#define MWU_REGIONEN_RGN0WA_Disable   (0UL)
 
#define MWU_REGIONEN_RGN0WA_Enable   (1UL)
 
#define MWU_REGIONENSET_PRGN1RA_Pos   (27UL)
 
#define MWU_REGIONENSET_PRGN1RA_Msk   (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos)
 
#define MWU_REGIONENSET_PRGN1RA_Disabled   (0UL)
 
#define MWU_REGIONENSET_PRGN1RA_Enabled   (1UL)
 
#define MWU_REGIONENSET_PRGN1RA_Set   (1UL)
 
#define MWU_REGIONENSET_PRGN1WA_Pos   (26UL)
 
#define MWU_REGIONENSET_PRGN1WA_Msk   (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos)
 
#define MWU_REGIONENSET_PRGN1WA_Disabled   (0UL)
 
#define MWU_REGIONENSET_PRGN1WA_Enabled   (1UL)
 
#define MWU_REGIONENSET_PRGN1WA_Set   (1UL)
 
#define MWU_REGIONENSET_PRGN0RA_Pos   (25UL)
 
#define MWU_REGIONENSET_PRGN0RA_Msk   (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos)
 
#define MWU_REGIONENSET_PRGN0RA_Disabled   (0UL)
 
#define MWU_REGIONENSET_PRGN0RA_Enabled   (1UL)
 
#define MWU_REGIONENSET_PRGN0RA_Set   (1UL)
 
#define MWU_REGIONENSET_PRGN0WA_Pos   (24UL)
 
#define MWU_REGIONENSET_PRGN0WA_Msk   (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos)
 
#define MWU_REGIONENSET_PRGN0WA_Disabled   (0UL)
 
#define MWU_REGIONENSET_PRGN0WA_Enabled   (1UL)
 
#define MWU_REGIONENSET_PRGN0WA_Set   (1UL)
 
#define MWU_REGIONENSET_RGN3RA_Pos   (7UL)
 
#define MWU_REGIONENSET_RGN3RA_Msk   (0x1UL << MWU_REGIONENSET_RGN3RA_Pos)
 
#define MWU_REGIONENSET_RGN3RA_Disabled   (0UL)
 
#define MWU_REGIONENSET_RGN3RA_Enabled   (1UL)
 
#define MWU_REGIONENSET_RGN3RA_Set   (1UL)
 
#define MWU_REGIONENSET_RGN3WA_Pos   (6UL)
 
#define MWU_REGIONENSET_RGN3WA_Msk   (0x1UL << MWU_REGIONENSET_RGN3WA_Pos)
 
#define MWU_REGIONENSET_RGN3WA_Disabled   (0UL)
 
#define MWU_REGIONENSET_RGN3WA_Enabled   (1UL)
 
#define MWU_REGIONENSET_RGN3WA_Set   (1UL)
 
#define MWU_REGIONENSET_RGN2RA_Pos   (5UL)
 
#define MWU_REGIONENSET_RGN2RA_Msk   (0x1UL << MWU_REGIONENSET_RGN2RA_Pos)
 
#define MWU_REGIONENSET_RGN2RA_Disabled   (0UL)
 
#define MWU_REGIONENSET_RGN2RA_Enabled   (1UL)
 
#define MWU_REGIONENSET_RGN2RA_Set   (1UL)
 
#define MWU_REGIONENSET_RGN2WA_Pos   (4UL)
 
#define MWU_REGIONENSET_RGN2WA_Msk   (0x1UL << MWU_REGIONENSET_RGN2WA_Pos)
 
#define MWU_REGIONENSET_RGN2WA_Disabled   (0UL)
 
#define MWU_REGIONENSET_RGN2WA_Enabled   (1UL)
 
#define MWU_REGIONENSET_RGN2WA_Set   (1UL)
 
#define MWU_REGIONENSET_RGN1RA_Pos   (3UL)
 
#define MWU_REGIONENSET_RGN1RA_Msk   (0x1UL << MWU_REGIONENSET_RGN1RA_Pos)
 
#define MWU_REGIONENSET_RGN1RA_Disabled   (0UL)
 
#define MWU_REGIONENSET_RGN1RA_Enabled   (1UL)
 
#define MWU_REGIONENSET_RGN1RA_Set   (1UL)
 
#define MWU_REGIONENSET_RGN1WA_Pos   (2UL)
 
#define MWU_REGIONENSET_RGN1WA_Msk   (0x1UL << MWU_REGIONENSET_RGN1WA_Pos)
 
#define MWU_REGIONENSET_RGN1WA_Disabled   (0UL)
 
#define MWU_REGIONENSET_RGN1WA_Enabled   (1UL)
 
#define MWU_REGIONENSET_RGN1WA_Set   (1UL)
 
#define MWU_REGIONENSET_RGN0RA_Pos   (1UL)
 
#define MWU_REGIONENSET_RGN0RA_Msk   (0x1UL << MWU_REGIONENSET_RGN0RA_Pos)
 
#define MWU_REGIONENSET_RGN0RA_Disabled   (0UL)
 
#define MWU_REGIONENSET_RGN0RA_Enabled   (1UL)
 
#define MWU_REGIONENSET_RGN0RA_Set   (1UL)
 
#define MWU_REGIONENSET_RGN0WA_Pos   (0UL)
 
#define MWU_REGIONENSET_RGN0WA_Msk   (0x1UL << MWU_REGIONENSET_RGN0WA_Pos)
 
#define MWU_REGIONENSET_RGN0WA_Disabled   (0UL)
 
#define MWU_REGIONENSET_RGN0WA_Enabled   (1UL)
 
#define MWU_REGIONENSET_RGN0WA_Set   (1UL)
 
#define MWU_REGIONENCLR_PRGN1RA_Pos   (27UL)
 
#define MWU_REGIONENCLR_PRGN1RA_Msk   (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos)
 
#define MWU_REGIONENCLR_PRGN1RA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_PRGN1RA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_PRGN1RA_Clear   (1UL)
 
#define MWU_REGIONENCLR_PRGN1WA_Pos   (26UL)
 
#define MWU_REGIONENCLR_PRGN1WA_Msk   (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos)
 
#define MWU_REGIONENCLR_PRGN1WA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_PRGN1WA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_PRGN1WA_Clear   (1UL)
 
#define MWU_REGIONENCLR_PRGN0RA_Pos   (25UL)
 
#define MWU_REGIONENCLR_PRGN0RA_Msk   (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos)
 
#define MWU_REGIONENCLR_PRGN0RA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_PRGN0RA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_PRGN0RA_Clear   (1UL)
 
#define MWU_REGIONENCLR_PRGN0WA_Pos   (24UL)
 
#define MWU_REGIONENCLR_PRGN0WA_Msk   (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos)
 
#define MWU_REGIONENCLR_PRGN0WA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_PRGN0WA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_PRGN0WA_Clear   (1UL)
 
#define MWU_REGIONENCLR_RGN3RA_Pos   (7UL)
 
#define MWU_REGIONENCLR_RGN3RA_Msk   (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos)
 
#define MWU_REGIONENCLR_RGN3RA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_RGN3RA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_RGN3RA_Clear   (1UL)
 
#define MWU_REGIONENCLR_RGN3WA_Pos   (6UL)
 
#define MWU_REGIONENCLR_RGN3WA_Msk   (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos)
 
#define MWU_REGIONENCLR_RGN3WA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_RGN3WA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_RGN3WA_Clear   (1UL)
 
#define MWU_REGIONENCLR_RGN2RA_Pos   (5UL)
 
#define MWU_REGIONENCLR_RGN2RA_Msk   (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos)
 
#define MWU_REGIONENCLR_RGN2RA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_RGN2RA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_RGN2RA_Clear   (1UL)
 
#define MWU_REGIONENCLR_RGN2WA_Pos   (4UL)
 
#define MWU_REGIONENCLR_RGN2WA_Msk   (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos)
 
#define MWU_REGIONENCLR_RGN2WA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_RGN2WA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_RGN2WA_Clear   (1UL)
 
#define MWU_REGIONENCLR_RGN1RA_Pos   (3UL)
 
#define MWU_REGIONENCLR_RGN1RA_Msk   (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos)
 
#define MWU_REGIONENCLR_RGN1RA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_RGN1RA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_RGN1RA_Clear   (1UL)
 
#define MWU_REGIONENCLR_RGN1WA_Pos   (2UL)
 
#define MWU_REGIONENCLR_RGN1WA_Msk   (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos)
 
#define MWU_REGIONENCLR_RGN1WA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_RGN1WA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_RGN1WA_Clear   (1UL)
 
#define MWU_REGIONENCLR_RGN0RA_Pos   (1UL)
 
#define MWU_REGIONENCLR_RGN0RA_Msk   (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos)
 
#define MWU_REGIONENCLR_RGN0RA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_RGN0RA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_RGN0RA_Clear   (1UL)
 
#define MWU_REGIONENCLR_RGN0WA_Pos   (0UL)
 
#define MWU_REGIONENCLR_RGN0WA_Msk   (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos)
 
#define MWU_REGIONENCLR_RGN0WA_Disabled   (0UL)
 
#define MWU_REGIONENCLR_RGN0WA_Enabled   (1UL)
 
#define MWU_REGIONENCLR_RGN0WA_Clear   (1UL)
 
#define MWU_REGION_START_START_Pos   (0UL)
 
#define MWU_REGION_START_START_Msk   (0xFFFFFFFFUL << MWU_REGION_START_START_Pos)
 
#define MWU_REGION_END_END_Pos   (0UL)
 
#define MWU_REGION_END_END_Msk   (0xFFFFFFFFUL << MWU_REGION_END_END_Pos)
 
#define MWU_PREGION_START_START_Pos   (0UL)
 
#define MWU_PREGION_START_START_Msk   (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos)
 
#define MWU_PREGION_END_END_Pos   (0UL)
 
#define MWU_PREGION_END_END_Msk   (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos)
 
#define MWU_PREGION_SUBS_SR31_Pos   (31UL)
 
#define MWU_PREGION_SUBS_SR31_Msk   (0x1UL << MWU_PREGION_SUBS_SR31_Pos)
 
#define MWU_PREGION_SUBS_SR31_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR31_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR30_Pos   (30UL)
 
#define MWU_PREGION_SUBS_SR30_Msk   (0x1UL << MWU_PREGION_SUBS_SR30_Pos)
 
#define MWU_PREGION_SUBS_SR30_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR30_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR29_Pos   (29UL)
 
#define MWU_PREGION_SUBS_SR29_Msk   (0x1UL << MWU_PREGION_SUBS_SR29_Pos)
 
#define MWU_PREGION_SUBS_SR29_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR29_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR28_Pos   (28UL)
 
#define MWU_PREGION_SUBS_SR28_Msk   (0x1UL << MWU_PREGION_SUBS_SR28_Pos)
 
#define MWU_PREGION_SUBS_SR28_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR28_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR27_Pos   (27UL)
 
#define MWU_PREGION_SUBS_SR27_Msk   (0x1UL << MWU_PREGION_SUBS_SR27_Pos)
 
#define MWU_PREGION_SUBS_SR27_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR27_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR26_Pos   (26UL)
 
#define MWU_PREGION_SUBS_SR26_Msk   (0x1UL << MWU_PREGION_SUBS_SR26_Pos)
 
#define MWU_PREGION_SUBS_SR26_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR26_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR25_Pos   (25UL)
 
#define MWU_PREGION_SUBS_SR25_Msk   (0x1UL << MWU_PREGION_SUBS_SR25_Pos)
 
#define MWU_PREGION_SUBS_SR25_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR25_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR24_Pos   (24UL)
 
#define MWU_PREGION_SUBS_SR24_Msk   (0x1UL << MWU_PREGION_SUBS_SR24_Pos)
 
#define MWU_PREGION_SUBS_SR24_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR24_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR23_Pos   (23UL)
 
#define MWU_PREGION_SUBS_SR23_Msk   (0x1UL << MWU_PREGION_SUBS_SR23_Pos)
 
#define MWU_PREGION_SUBS_SR23_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR23_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR22_Pos   (22UL)
 
#define MWU_PREGION_SUBS_SR22_Msk   (0x1UL << MWU_PREGION_SUBS_SR22_Pos)
 
#define MWU_PREGION_SUBS_SR22_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR22_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR21_Pos   (21UL)
 
#define MWU_PREGION_SUBS_SR21_Msk   (0x1UL << MWU_PREGION_SUBS_SR21_Pos)
 
#define MWU_PREGION_SUBS_SR21_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR21_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR20_Pos   (20UL)
 
#define MWU_PREGION_SUBS_SR20_Msk   (0x1UL << MWU_PREGION_SUBS_SR20_Pos)
 
#define MWU_PREGION_SUBS_SR20_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR20_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR19_Pos   (19UL)
 
#define MWU_PREGION_SUBS_SR19_Msk   (0x1UL << MWU_PREGION_SUBS_SR19_Pos)
 
#define MWU_PREGION_SUBS_SR19_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR19_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR18_Pos   (18UL)
 
#define MWU_PREGION_SUBS_SR18_Msk   (0x1UL << MWU_PREGION_SUBS_SR18_Pos)
 
#define MWU_PREGION_SUBS_SR18_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR18_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR17_Pos   (17UL)
 
#define MWU_PREGION_SUBS_SR17_Msk   (0x1UL << MWU_PREGION_SUBS_SR17_Pos)
 
#define MWU_PREGION_SUBS_SR17_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR17_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR16_Pos   (16UL)
 
#define MWU_PREGION_SUBS_SR16_Msk   (0x1UL << MWU_PREGION_SUBS_SR16_Pos)
 
#define MWU_PREGION_SUBS_SR16_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR16_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR15_Pos   (15UL)
 
#define MWU_PREGION_SUBS_SR15_Msk   (0x1UL << MWU_PREGION_SUBS_SR15_Pos)
 
#define MWU_PREGION_SUBS_SR15_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR15_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR14_Pos   (14UL)
 
#define MWU_PREGION_SUBS_SR14_Msk   (0x1UL << MWU_PREGION_SUBS_SR14_Pos)
 
#define MWU_PREGION_SUBS_SR14_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR14_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR13_Pos   (13UL)
 
#define MWU_PREGION_SUBS_SR13_Msk   (0x1UL << MWU_PREGION_SUBS_SR13_Pos)
 
#define MWU_PREGION_SUBS_SR13_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR13_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR12_Pos   (12UL)
 
#define MWU_PREGION_SUBS_SR12_Msk   (0x1UL << MWU_PREGION_SUBS_SR12_Pos)
 
#define MWU_PREGION_SUBS_SR12_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR12_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR11_Pos   (11UL)
 
#define MWU_PREGION_SUBS_SR11_Msk   (0x1UL << MWU_PREGION_SUBS_SR11_Pos)
 
#define MWU_PREGION_SUBS_SR11_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR11_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR10_Pos   (10UL)
 
#define MWU_PREGION_SUBS_SR10_Msk   (0x1UL << MWU_PREGION_SUBS_SR10_Pos)
 
#define MWU_PREGION_SUBS_SR10_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR10_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR9_Pos   (9UL)
 
#define MWU_PREGION_SUBS_SR9_Msk   (0x1UL << MWU_PREGION_SUBS_SR9_Pos)
 
#define MWU_PREGION_SUBS_SR9_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR9_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR8_Pos   (8UL)
 
#define MWU_PREGION_SUBS_SR8_Msk   (0x1UL << MWU_PREGION_SUBS_SR8_Pos)
 
#define MWU_PREGION_SUBS_SR8_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR8_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR7_Pos   (7UL)
 
#define MWU_PREGION_SUBS_SR7_Msk   (0x1UL << MWU_PREGION_SUBS_SR7_Pos)
 
#define MWU_PREGION_SUBS_SR7_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR7_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR6_Pos   (6UL)
 
#define MWU_PREGION_SUBS_SR6_Msk   (0x1UL << MWU_PREGION_SUBS_SR6_Pos)
 
#define MWU_PREGION_SUBS_SR6_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR6_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR5_Pos   (5UL)
 
#define MWU_PREGION_SUBS_SR5_Msk   (0x1UL << MWU_PREGION_SUBS_SR5_Pos)
 
#define MWU_PREGION_SUBS_SR5_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR5_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR4_Pos   (4UL)
 
#define MWU_PREGION_SUBS_SR4_Msk   (0x1UL << MWU_PREGION_SUBS_SR4_Pos)
 
#define MWU_PREGION_SUBS_SR4_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR4_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR3_Pos   (3UL)
 
#define MWU_PREGION_SUBS_SR3_Msk   (0x1UL << MWU_PREGION_SUBS_SR3_Pos)
 
#define MWU_PREGION_SUBS_SR3_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR3_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR2_Pos   (2UL)
 
#define MWU_PREGION_SUBS_SR2_Msk   (0x1UL << MWU_PREGION_SUBS_SR2_Pos)
 
#define MWU_PREGION_SUBS_SR2_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR2_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR1_Pos   (1UL)
 
#define MWU_PREGION_SUBS_SR1_Msk   (0x1UL << MWU_PREGION_SUBS_SR1_Pos)
 
#define MWU_PREGION_SUBS_SR1_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR1_Include   (1UL)
 
#define MWU_PREGION_SUBS_SR0_Pos   (0UL)
 
#define MWU_PREGION_SUBS_SR0_Msk   (0x1UL << MWU_PREGION_SUBS_SR0_Pos)
 
#define MWU_PREGION_SUBS_SR0_Exclude   (0UL)
 
#define MWU_PREGION_SUBS_SR0_Include   (1UL)
 
#define NFCT_SHORTS_FIELDLOST_SENSE_Pos   (1UL)
 
#define NFCT_SHORTS_FIELDLOST_SENSE_Msk   (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos)
 
#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled   (0UL)
 
#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled   (1UL)
 
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos   (0UL)
 
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk   (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos)
 
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled   (0UL)
 
#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled   (1UL)
 
#define NFCT_INTEN_STARTED_Pos   (20UL)
 
#define NFCT_INTEN_STARTED_Msk   (0x1UL << NFCT_INTEN_STARTED_Pos)
 
#define NFCT_INTEN_STARTED_Disabled   (0UL)
 
#define NFCT_INTEN_STARTED_Enabled   (1UL)
 
#define NFCT_INTEN_SELECTED_Pos   (19UL)
 
#define NFCT_INTEN_SELECTED_Msk   (0x1UL << NFCT_INTEN_SELECTED_Pos)
 
#define NFCT_INTEN_SELECTED_Disabled   (0UL)
 
#define NFCT_INTEN_SELECTED_Enabled   (1UL)
 
#define NFCT_INTEN_COLLISION_Pos   (18UL)
 
#define NFCT_INTEN_COLLISION_Msk   (0x1UL << NFCT_INTEN_COLLISION_Pos)
 
#define NFCT_INTEN_COLLISION_Disabled   (0UL)
 
#define NFCT_INTEN_COLLISION_Enabled   (1UL)
 
#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos   (14UL)
 
#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk   (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos)
 
#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled   (0UL)
 
#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled   (1UL)
 
#define NFCT_INTEN_ENDTX_Pos   (12UL)
 
#define NFCT_INTEN_ENDTX_Msk   (0x1UL << NFCT_INTEN_ENDTX_Pos)
 
#define NFCT_INTEN_ENDTX_Disabled   (0UL)
 
#define NFCT_INTEN_ENDTX_Enabled   (1UL)
 
#define NFCT_INTEN_ENDRX_Pos   (11UL)
 
#define NFCT_INTEN_ENDRX_Msk   (0x1UL << NFCT_INTEN_ENDRX_Pos)
 
#define NFCT_INTEN_ENDRX_Disabled   (0UL)
 
#define NFCT_INTEN_ENDRX_Enabled   (1UL)
 
#define NFCT_INTEN_RXERROR_Pos   (10UL)
 
#define NFCT_INTEN_RXERROR_Msk   (0x1UL << NFCT_INTEN_RXERROR_Pos)
 
#define NFCT_INTEN_RXERROR_Disabled   (0UL)
 
#define NFCT_INTEN_RXERROR_Enabled   (1UL)
 
#define NFCT_INTEN_ERROR_Pos   (7UL)
 
#define NFCT_INTEN_ERROR_Msk   (0x1UL << NFCT_INTEN_ERROR_Pos)
 
#define NFCT_INTEN_ERROR_Disabled   (0UL)
 
#define NFCT_INTEN_ERROR_Enabled   (1UL)
 
#define NFCT_INTEN_RXFRAMEEND_Pos   (6UL)
 
#define NFCT_INTEN_RXFRAMEEND_Msk   (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos)
 
#define NFCT_INTEN_RXFRAMEEND_Disabled   (0UL)
 
#define NFCT_INTEN_RXFRAMEEND_Enabled   (1UL)
 
#define NFCT_INTEN_RXFRAMESTART_Pos   (5UL)
 
#define NFCT_INTEN_RXFRAMESTART_Msk   (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos)
 
#define NFCT_INTEN_RXFRAMESTART_Disabled   (0UL)
 
#define NFCT_INTEN_RXFRAMESTART_Enabled   (1UL)
 
#define NFCT_INTEN_TXFRAMEEND_Pos   (4UL)
 
#define NFCT_INTEN_TXFRAMEEND_Msk   (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos)
 
#define NFCT_INTEN_TXFRAMEEND_Disabled   (0UL)
 
#define NFCT_INTEN_TXFRAMEEND_Enabled   (1UL)
 
#define NFCT_INTEN_TXFRAMESTART_Pos   (3UL)
 
#define NFCT_INTEN_TXFRAMESTART_Msk   (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos)
 
#define NFCT_INTEN_TXFRAMESTART_Disabled   (0UL)
 
#define NFCT_INTEN_TXFRAMESTART_Enabled   (1UL)
 
#define NFCT_INTEN_FIELDLOST_Pos   (2UL)
 
#define NFCT_INTEN_FIELDLOST_Msk   (0x1UL << NFCT_INTEN_FIELDLOST_Pos)
 
#define NFCT_INTEN_FIELDLOST_Disabled   (0UL)
 
#define NFCT_INTEN_FIELDLOST_Enabled   (1UL)
 
#define NFCT_INTEN_FIELDDETECTED_Pos   (1UL)
 
#define NFCT_INTEN_FIELDDETECTED_Msk   (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos)
 
#define NFCT_INTEN_FIELDDETECTED_Disabled   (0UL)
 
#define NFCT_INTEN_FIELDDETECTED_Enabled   (1UL)
 
#define NFCT_INTEN_READY_Pos   (0UL)
 
#define NFCT_INTEN_READY_Msk   (0x1UL << NFCT_INTEN_READY_Pos)
 
#define NFCT_INTEN_READY_Disabled   (0UL)
 
#define NFCT_INTEN_READY_Enabled   (1UL)
 
#define NFCT_INTENSET_STARTED_Pos   (20UL)
 
#define NFCT_INTENSET_STARTED_Msk   (0x1UL << NFCT_INTENSET_STARTED_Pos)
 
#define NFCT_INTENSET_STARTED_Disabled   (0UL)
 
#define NFCT_INTENSET_STARTED_Enabled   (1UL)
 
#define NFCT_INTENSET_STARTED_Set   (1UL)
 
#define NFCT_INTENSET_SELECTED_Pos   (19UL)
 
#define NFCT_INTENSET_SELECTED_Msk   (0x1UL << NFCT_INTENSET_SELECTED_Pos)
 
#define NFCT_INTENSET_SELECTED_Disabled   (0UL)
 
#define NFCT_INTENSET_SELECTED_Enabled   (1UL)
 
#define NFCT_INTENSET_SELECTED_Set   (1UL)
 
#define NFCT_INTENSET_COLLISION_Pos   (18UL)
 
#define NFCT_INTENSET_COLLISION_Msk   (0x1UL << NFCT_INTENSET_COLLISION_Pos)
 
#define NFCT_INTENSET_COLLISION_Disabled   (0UL)
 
#define NFCT_INTENSET_COLLISION_Enabled   (1UL)
 
#define NFCT_INTENSET_COLLISION_Set   (1UL)
 
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos   (14UL)
 
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk   (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos)
 
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled   (0UL)
 
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled   (1UL)
 
#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set   (1UL)
 
#define NFCT_INTENSET_ENDTX_Pos   (12UL)
 
#define NFCT_INTENSET_ENDTX_Msk   (0x1UL << NFCT_INTENSET_ENDTX_Pos)
 
#define NFCT_INTENSET_ENDTX_Disabled   (0UL)
 
#define NFCT_INTENSET_ENDTX_Enabled   (1UL)
 
#define NFCT_INTENSET_ENDTX_Set   (1UL)
 
#define NFCT_INTENSET_ENDRX_Pos   (11UL)
 
#define NFCT_INTENSET_ENDRX_Msk   (0x1UL << NFCT_INTENSET_ENDRX_Pos)
 
#define NFCT_INTENSET_ENDRX_Disabled   (0UL)
 
#define NFCT_INTENSET_ENDRX_Enabled   (1UL)
 
#define NFCT_INTENSET_ENDRX_Set   (1UL)
 
#define NFCT_INTENSET_RXERROR_Pos   (10UL)
 
#define NFCT_INTENSET_RXERROR_Msk   (0x1UL << NFCT_INTENSET_RXERROR_Pos)
 
#define NFCT_INTENSET_RXERROR_Disabled   (0UL)
 
#define NFCT_INTENSET_RXERROR_Enabled   (1UL)
 
#define NFCT_INTENSET_RXERROR_Set   (1UL)
 
#define NFCT_INTENSET_ERROR_Pos   (7UL)
 
#define NFCT_INTENSET_ERROR_Msk   (0x1UL << NFCT_INTENSET_ERROR_Pos)
 
#define NFCT_INTENSET_ERROR_Disabled   (0UL)
 
#define NFCT_INTENSET_ERROR_Enabled   (1UL)
 
#define NFCT_INTENSET_ERROR_Set   (1UL)
 
#define NFCT_INTENSET_RXFRAMEEND_Pos   (6UL)
 
#define NFCT_INTENSET_RXFRAMEEND_Msk   (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos)
 
#define NFCT_INTENSET_RXFRAMEEND_Disabled   (0UL)
 
#define NFCT_INTENSET_RXFRAMEEND_Enabled   (1UL)
 
#define NFCT_INTENSET_RXFRAMEEND_Set   (1UL)
 
#define NFCT_INTENSET_RXFRAMESTART_Pos   (5UL)
 
#define NFCT_INTENSET_RXFRAMESTART_Msk   (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos)
 
#define NFCT_INTENSET_RXFRAMESTART_Disabled   (0UL)
 
#define NFCT_INTENSET_RXFRAMESTART_Enabled   (1UL)
 
#define NFCT_INTENSET_RXFRAMESTART_Set   (1UL)
 
#define NFCT_INTENSET_TXFRAMEEND_Pos   (4UL)
 
#define NFCT_INTENSET_TXFRAMEEND_Msk   (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos)
 
#define NFCT_INTENSET_TXFRAMEEND_Disabled   (0UL)
 
#define NFCT_INTENSET_TXFRAMEEND_Enabled   (1UL)
 
#define NFCT_INTENSET_TXFRAMEEND_Set   (1UL)
 
#define NFCT_INTENSET_TXFRAMESTART_Pos   (3UL)
 
#define NFCT_INTENSET_TXFRAMESTART_Msk   (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos)
 
#define NFCT_INTENSET_TXFRAMESTART_Disabled   (0UL)
 
#define NFCT_INTENSET_TXFRAMESTART_Enabled   (1UL)
 
#define NFCT_INTENSET_TXFRAMESTART_Set   (1UL)
 
#define NFCT_INTENSET_FIELDLOST_Pos   (2UL)
 
#define NFCT_INTENSET_FIELDLOST_Msk   (0x1UL << NFCT_INTENSET_FIELDLOST_Pos)
 
#define NFCT_INTENSET_FIELDLOST_Disabled   (0UL)
 
#define NFCT_INTENSET_FIELDLOST_Enabled   (1UL)
 
#define NFCT_INTENSET_FIELDLOST_Set   (1UL)
 
#define NFCT_INTENSET_FIELDDETECTED_Pos   (1UL)
 
#define NFCT_INTENSET_FIELDDETECTED_Msk   (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos)
 
#define NFCT_INTENSET_FIELDDETECTED_Disabled   (0UL)
 
#define NFCT_INTENSET_FIELDDETECTED_Enabled   (1UL)
 
#define NFCT_INTENSET_FIELDDETECTED_Set   (1UL)
 
#define NFCT_INTENSET_READY_Pos   (0UL)
 
#define NFCT_INTENSET_READY_Msk   (0x1UL << NFCT_INTENSET_READY_Pos)
 
#define NFCT_INTENSET_READY_Disabled   (0UL)
 
#define NFCT_INTENSET_READY_Enabled   (1UL)
 
#define NFCT_INTENSET_READY_Set   (1UL)
 
#define NFCT_INTENCLR_STARTED_Pos   (20UL)
 
#define NFCT_INTENCLR_STARTED_Msk   (0x1UL << NFCT_INTENCLR_STARTED_Pos)
 
#define NFCT_INTENCLR_STARTED_Disabled   (0UL)
 
#define NFCT_INTENCLR_STARTED_Enabled   (1UL)
 
#define NFCT_INTENCLR_STARTED_Clear   (1UL)
 
#define NFCT_INTENCLR_SELECTED_Pos   (19UL)
 
#define NFCT_INTENCLR_SELECTED_Msk   (0x1UL << NFCT_INTENCLR_SELECTED_Pos)
 
#define NFCT_INTENCLR_SELECTED_Disabled   (0UL)
 
#define NFCT_INTENCLR_SELECTED_Enabled   (1UL)
 
#define NFCT_INTENCLR_SELECTED_Clear   (1UL)
 
#define NFCT_INTENCLR_COLLISION_Pos   (18UL)
 
#define NFCT_INTENCLR_COLLISION_Msk   (0x1UL << NFCT_INTENCLR_COLLISION_Pos)
 
#define NFCT_INTENCLR_COLLISION_Disabled   (0UL)
 
#define NFCT_INTENCLR_COLLISION_Enabled   (1UL)
 
#define NFCT_INTENCLR_COLLISION_Clear   (1UL)
 
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos   (14UL)
 
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk   (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos)
 
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled   (0UL)
 
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled   (1UL)
 
#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear   (1UL)
 
#define NFCT_INTENCLR_ENDTX_Pos   (12UL)
 
#define NFCT_INTENCLR_ENDTX_Msk   (0x1UL << NFCT_INTENCLR_ENDTX_Pos)
 
#define NFCT_INTENCLR_ENDTX_Disabled   (0UL)
 
#define NFCT_INTENCLR_ENDTX_Enabled   (1UL)
 
#define NFCT_INTENCLR_ENDTX_Clear   (1UL)
 
#define NFCT_INTENCLR_ENDRX_Pos   (11UL)
 
#define NFCT_INTENCLR_ENDRX_Msk   (0x1UL << NFCT_INTENCLR_ENDRX_Pos)
 
#define NFCT_INTENCLR_ENDRX_Disabled   (0UL)
 
#define NFCT_INTENCLR_ENDRX_Enabled   (1UL)
 
#define NFCT_INTENCLR_ENDRX_Clear   (1UL)
 
#define NFCT_INTENCLR_RXERROR_Pos   (10UL)
 
#define NFCT_INTENCLR_RXERROR_Msk   (0x1UL << NFCT_INTENCLR_RXERROR_Pos)
 
#define NFCT_INTENCLR_RXERROR_Disabled   (0UL)
 
#define NFCT_INTENCLR_RXERROR_Enabled   (1UL)
 
#define NFCT_INTENCLR_RXERROR_Clear   (1UL)
 
#define NFCT_INTENCLR_ERROR_Pos   (7UL)
 
#define NFCT_INTENCLR_ERROR_Msk   (0x1UL << NFCT_INTENCLR_ERROR_Pos)
 
#define NFCT_INTENCLR_ERROR_Disabled   (0UL)
 
#define NFCT_INTENCLR_ERROR_Enabled   (1UL)
 
#define NFCT_INTENCLR_ERROR_Clear   (1UL)
 
#define NFCT_INTENCLR_RXFRAMEEND_Pos   (6UL)
 
#define NFCT_INTENCLR_RXFRAMEEND_Msk   (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos)
 
#define NFCT_INTENCLR_RXFRAMEEND_Disabled   (0UL)
 
#define NFCT_INTENCLR_RXFRAMEEND_Enabled   (1UL)
 
#define NFCT_INTENCLR_RXFRAMEEND_Clear   (1UL)
 
#define NFCT_INTENCLR_RXFRAMESTART_Pos   (5UL)
 
#define NFCT_INTENCLR_RXFRAMESTART_Msk   (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos)
 
#define NFCT_INTENCLR_RXFRAMESTART_Disabled   (0UL)
 
#define NFCT_INTENCLR_RXFRAMESTART_Enabled   (1UL)
 
#define NFCT_INTENCLR_RXFRAMESTART_Clear   (1UL)
 
#define NFCT_INTENCLR_TXFRAMEEND_Pos   (4UL)
 
#define NFCT_INTENCLR_TXFRAMEEND_Msk   (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos)
 
#define NFCT_INTENCLR_TXFRAMEEND_Disabled   (0UL)
 
#define NFCT_INTENCLR_TXFRAMEEND_Enabled   (1UL)
 
#define NFCT_INTENCLR_TXFRAMEEND_Clear   (1UL)
 
#define NFCT_INTENCLR_TXFRAMESTART_Pos   (3UL)
 
#define NFCT_INTENCLR_TXFRAMESTART_Msk   (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos)
 
#define NFCT_INTENCLR_TXFRAMESTART_Disabled   (0UL)
 
#define NFCT_INTENCLR_TXFRAMESTART_Enabled   (1UL)
 
#define NFCT_INTENCLR_TXFRAMESTART_Clear   (1UL)
 
#define NFCT_INTENCLR_FIELDLOST_Pos   (2UL)
 
#define NFCT_INTENCLR_FIELDLOST_Msk   (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos)
 
#define NFCT_INTENCLR_FIELDLOST_Disabled   (0UL)
 
#define NFCT_INTENCLR_FIELDLOST_Enabled   (1UL)
 
#define NFCT_INTENCLR_FIELDLOST_Clear   (1UL)
 
#define NFCT_INTENCLR_FIELDDETECTED_Pos   (1UL)
 
#define NFCT_INTENCLR_FIELDDETECTED_Msk   (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos)
 
#define NFCT_INTENCLR_FIELDDETECTED_Disabled   (0UL)
 
#define NFCT_INTENCLR_FIELDDETECTED_Enabled   (1UL)
 
#define NFCT_INTENCLR_FIELDDETECTED_Clear   (1UL)
 
#define NFCT_INTENCLR_READY_Pos   (0UL)
 
#define NFCT_INTENCLR_READY_Msk   (0x1UL << NFCT_INTENCLR_READY_Pos)
 
#define NFCT_INTENCLR_READY_Disabled   (0UL)
 
#define NFCT_INTENCLR_READY_Enabled   (1UL)
 
#define NFCT_INTENCLR_READY_Clear   (1UL)
 
#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos   (3UL)
 
#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk   (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos)
 
#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos   (2UL)
 
#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk   (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos)
 
#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos   (0UL)
 
#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk   (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos)
 
#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos   (3UL)
 
#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk   (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos)
 
#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun   (0UL)
 
#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun   (1UL)
 
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos   (2UL)
 
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk   (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos)
 
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK   (0UL)
 
#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError   (1UL)
 
#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos   (0UL)
 
#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk   (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos)
 
#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect   (0UL)
 
#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError   (1UL)
 
#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos   (0UL)
 
#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk   (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos)
 
#define NFCT_FIELDPRESENT_LOCKDETECT_Pos   (1UL)
 
#define NFCT_FIELDPRESENT_LOCKDETECT_Msk   (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos)
 
#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked   (0UL)
 
#define NFCT_FIELDPRESENT_LOCKDETECT_Locked   (1UL)
 
#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos   (0UL)
 
#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk   (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos)
 
#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField   (0UL)
 
#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent   (1UL)
 
#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos   (0UL)
 
#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk   (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos)
 
#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos   (0UL)
 
#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk   (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos)
 
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos   (0UL)
 
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk   (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos)
 
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun   (0UL)
 
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window   (1UL)
 
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal   (2UL)
 
#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid   (3UL)
 
#define NFCT_PACKETPTR_PTR_Pos   (0UL)
 
#define NFCT_PACKETPTR_PTR_Msk   (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos)
 
#define NFCT_MAXLEN_MAXLEN_Pos   (0UL)
 
#define NFCT_MAXLEN_MAXLEN_Msk   (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos)
 
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos   (4UL)
 
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk   (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos)
 
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX   (0UL)
 
#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX   (1UL)
 
#define NFCT_TXD_FRAMECONFIG_SOF_Pos   (2UL)
 
#define NFCT_TXD_FRAMECONFIG_SOF_Msk   (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos)
 
#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF   (0UL)
 
#define NFCT_TXD_FRAMECONFIG_SOF_SoF   (1UL)
 
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos   (1UL)
 
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk   (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos)
 
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd   (0UL)
 
#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart   (1UL)
 
#define NFCT_TXD_FRAMECONFIG_PARITY_Pos   (0UL)
 
#define NFCT_TXD_FRAMECONFIG_PARITY_Msk   (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos)
 
#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity   (0UL)
 
#define NFCT_TXD_FRAMECONFIG_PARITY_Parity   (1UL)
 
#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos   (3UL)
 
#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk   (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos)
 
#define NFCT_TXD_AMOUNT_TXDATABITS_Pos   (0UL)
 
#define NFCT_TXD_AMOUNT_TXDATABITS_Msk   (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos)
 
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos   (4UL)
 
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk   (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos)
 
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX   (0UL)
 
#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX   (1UL)
 
#define NFCT_RXD_FRAMECONFIG_SOF_Pos   (2UL)
 
#define NFCT_RXD_FRAMECONFIG_SOF_Msk   (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos)
 
#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF   (0UL)
 
#define NFCT_RXD_FRAMECONFIG_SOF_SoF   (1UL)
 
#define NFCT_RXD_FRAMECONFIG_PARITY_Pos   (0UL)
 
#define NFCT_RXD_FRAMECONFIG_PARITY_Msk   (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos)
 
#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity   (0UL)
 
#define NFCT_RXD_FRAMECONFIG_PARITY_Parity   (1UL)
 
#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos   (3UL)
 
#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk   (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos)
 
#define NFCT_RXD_AMOUNT_RXDATABITS_Pos   (0UL)
 
#define NFCT_RXD_AMOUNT_RXDATABITS_Msk   (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos)
 
#define NFCT_NFCID1_LAST_NFCID1_W_Pos   (24UL)
 
#define NFCT_NFCID1_LAST_NFCID1_W_Msk   (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos)
 
#define NFCT_NFCID1_LAST_NFCID1_X_Pos   (16UL)
 
#define NFCT_NFCID1_LAST_NFCID1_X_Msk   (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos)
 
#define NFCT_NFCID1_LAST_NFCID1_Y_Pos   (8UL)
 
#define NFCT_NFCID1_LAST_NFCID1_Y_Msk   (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos)
 
#define NFCT_NFCID1_LAST_NFCID1_Z_Pos   (0UL)
 
#define NFCT_NFCID1_LAST_NFCID1_Z_Msk   (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos)
 
#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos   (16UL)
 
#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk   (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos)
 
#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos   (8UL)
 
#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk   (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos)
 
#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos   (0UL)
 
#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk   (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos)
 
#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos   (16UL)
 
#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk   (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos)
 
#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos   (8UL)
 
#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk   (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos)
 
#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos   (0UL)
 
#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk   (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos)
 
#define NFCT_SENSRES_RFU74_Pos   (12UL)
 
#define NFCT_SENSRES_RFU74_Msk   (0xFUL << NFCT_SENSRES_RFU74_Pos)
 
#define NFCT_SENSRES_PLATFCONFIG_Pos   (8UL)
 
#define NFCT_SENSRES_PLATFCONFIG_Msk   (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos)
 
#define NFCT_SENSRES_NFCIDSIZE_Pos   (6UL)
 
#define NFCT_SENSRES_NFCIDSIZE_Msk   (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos)
 
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single   (0UL)
 
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double   (1UL)
 
#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple   (2UL)
 
#define NFCT_SENSRES_RFU5_Pos   (5UL)
 
#define NFCT_SENSRES_RFU5_Msk   (0x1UL << NFCT_SENSRES_RFU5_Pos)
 
#define NFCT_SENSRES_BITFRAMESDD_Pos   (0UL)
 
#define NFCT_SENSRES_BITFRAMESDD_Msk   (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos)
 
#define NFCT_SENSRES_BITFRAMESDD_SDD00000   (0UL)
 
#define NFCT_SENSRES_BITFRAMESDD_SDD00001   (1UL)
 
#define NFCT_SENSRES_BITFRAMESDD_SDD00010   (2UL)
 
#define NFCT_SENSRES_BITFRAMESDD_SDD00100   (4UL)
 
#define NFCT_SENSRES_BITFRAMESDD_SDD01000   (8UL)
 
#define NFCT_SENSRES_BITFRAMESDD_SDD10000   (16UL)
 
#define NFCT_SELRES_RFU7_Pos   (7UL)
 
#define NFCT_SELRES_RFU7_Msk   (0x1UL << NFCT_SELRES_RFU7_Pos)
 
#define NFCT_SELRES_PROTOCOL_Pos   (5UL)
 
#define NFCT_SELRES_PROTOCOL_Msk   (0x3UL << NFCT_SELRES_PROTOCOL_Pos)
 
#define NFCT_SELRES_RFU43_Pos   (3UL)
 
#define NFCT_SELRES_RFU43_Msk   (0x3UL << NFCT_SELRES_RFU43_Pos)
 
#define NFCT_SELRES_CASCADE_Pos   (2UL)
 
#define NFCT_SELRES_CASCADE_Msk   (0x1UL << NFCT_SELRES_CASCADE_Pos)
 
#define NFCT_SELRES_CASCADE_Complete   (0UL)
 
#define NFCT_SELRES_CASCADE_NotComplete   (1UL)
 
#define NFCT_SELRES_RFU10_Pos   (0UL)
 
#define NFCT_SELRES_RFU10_Msk   (0x3UL << NFCT_SELRES_RFU10_Pos)
 
#define NVMC_READY_READY_Pos   (0UL)
 
#define NVMC_READY_READY_Msk   (0x1UL << NVMC_READY_READY_Pos)
 
#define NVMC_READY_READY_Busy   (0UL)
 
#define NVMC_READY_READY_Ready   (1UL)
 
#define NVMC_CONFIG_WEN_Pos   (0UL)
 
#define NVMC_CONFIG_WEN_Msk   (0x3UL << NVMC_CONFIG_WEN_Pos)
 
#define NVMC_CONFIG_WEN_Ren   (0UL)
 
#define NVMC_CONFIG_WEN_Wen   (1UL)
 
#define NVMC_CONFIG_WEN_Een   (2UL)
 
#define NVMC_ERASEPAGE_ERASEPAGE_Pos   (0UL)
 
#define NVMC_ERASEPAGE_ERASEPAGE_Msk   (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos)
 
#define NVMC_ERASEPCR1_ERASEPCR1_Pos   (0UL)
 
#define NVMC_ERASEPCR1_ERASEPCR1_Msk   (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos)
 
#define NVMC_ERASEALL_ERASEALL_Pos   (0UL)
 
#define NVMC_ERASEALL_ERASEALL_Msk   (0x1UL << NVMC_ERASEALL_ERASEALL_Pos)
 
#define NVMC_ERASEALL_ERASEALL_NoOperation   (0UL)
 
#define NVMC_ERASEALL_ERASEALL_Erase   (1UL)
 
#define NVMC_ERASEPCR0_ERASEPCR0_Pos   (0UL)
 
#define NVMC_ERASEPCR0_ERASEPCR0_Msk   (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos)
 
#define NVMC_ERASEUICR_ERASEUICR_Pos   (0UL)
 
#define NVMC_ERASEUICR_ERASEUICR_Msk   (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos)
 
#define NVMC_ERASEUICR_ERASEUICR_NoOperation   (0UL)
 
#define NVMC_ERASEUICR_ERASEUICR_Erase   (1UL)
 
#define NVMC_ICACHECNF_CACHEPROFEN_Pos   (8UL)
 
#define NVMC_ICACHECNF_CACHEPROFEN_Msk   (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos)
 
#define NVMC_ICACHECNF_CACHEPROFEN_Disabled   (0UL)
 
#define NVMC_ICACHECNF_CACHEPROFEN_Enabled   (1UL)
 
#define NVMC_ICACHECNF_CACHEEN_Pos   (0UL)
 
#define NVMC_ICACHECNF_CACHEEN_Msk   (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos)
 
#define NVMC_ICACHECNF_CACHEEN_Disabled   (0UL)
 
#define NVMC_ICACHECNF_CACHEEN_Enabled   (1UL)
 
#define NVMC_IHIT_HITS_Pos   (0UL)
 
#define NVMC_IHIT_HITS_Msk   (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos)
 
#define NVMC_IMISS_MISSES_Pos   (0UL)
 
#define NVMC_IMISS_MISSES_Msk   (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos)
 
#define GPIO_OUT_PIN31_Pos   (31UL)
 
#define GPIO_OUT_PIN31_Msk   (0x1UL << GPIO_OUT_PIN31_Pos)
 
#define GPIO_OUT_PIN31_Low   (0UL)
 
#define GPIO_OUT_PIN31_High   (1UL)
 
#define GPIO_OUT_PIN30_Pos   (30UL)
 
#define GPIO_OUT_PIN30_Msk   (0x1UL << GPIO_OUT_PIN30_Pos)
 
#define GPIO_OUT_PIN30_Low   (0UL)
 
#define GPIO_OUT_PIN30_High   (1UL)
 
#define GPIO_OUT_PIN29_Pos   (29UL)
 
#define GPIO_OUT_PIN29_Msk   (0x1UL << GPIO_OUT_PIN29_Pos)
 
#define GPIO_OUT_PIN29_Low   (0UL)
 
#define GPIO_OUT_PIN29_High   (1UL)
 
#define GPIO_OUT_PIN28_Pos   (28UL)
 
#define GPIO_OUT_PIN28_Msk   (0x1UL << GPIO_OUT_PIN28_Pos)
 
#define GPIO_OUT_PIN28_Low   (0UL)
 
#define GPIO_OUT_PIN28_High   (1UL)
 
#define GPIO_OUT_PIN27_Pos   (27UL)
 
#define GPIO_OUT_PIN27_Msk   (0x1UL << GPIO_OUT_PIN27_Pos)
 
#define GPIO_OUT_PIN27_Low   (0UL)
 
#define GPIO_OUT_PIN27_High   (1UL)
 
#define GPIO_OUT_PIN26_Pos   (26UL)
 
#define GPIO_OUT_PIN26_Msk   (0x1UL << GPIO_OUT_PIN26_Pos)
 
#define GPIO_OUT_PIN26_Low   (0UL)
 
#define GPIO_OUT_PIN26_High   (1UL)
 
#define GPIO_OUT_PIN25_Pos   (25UL)
 
#define GPIO_OUT_PIN25_Msk   (0x1UL << GPIO_OUT_PIN25_Pos)
 
#define GPIO_OUT_PIN25_Low   (0UL)
 
#define GPIO_OUT_PIN25_High   (1UL)
 
#define GPIO_OUT_PIN24_Pos   (24UL)
 
#define GPIO_OUT_PIN24_Msk   (0x1UL << GPIO_OUT_PIN24_Pos)
 
#define GPIO_OUT_PIN24_Low   (0UL)
 
#define GPIO_OUT_PIN24_High   (1UL)
 
#define GPIO_OUT_PIN23_Pos   (23UL)
 
#define GPIO_OUT_PIN23_Msk   (0x1UL << GPIO_OUT_PIN23_Pos)
 
#define GPIO_OUT_PIN23_Low   (0UL)
 
#define GPIO_OUT_PIN23_High   (1UL)
 
#define GPIO_OUT_PIN22_Pos   (22UL)
 
#define GPIO_OUT_PIN22_Msk   (0x1UL << GPIO_OUT_PIN22_Pos)
 
#define GPIO_OUT_PIN22_Low   (0UL)
 
#define GPIO_OUT_PIN22_High   (1UL)
 
#define GPIO_OUT_PIN21_Pos   (21UL)
 
#define GPIO_OUT_PIN21_Msk   (0x1UL << GPIO_OUT_PIN21_Pos)
 
#define GPIO_OUT_PIN21_Low   (0UL)
 
#define GPIO_OUT_PIN21_High   (1UL)
 
#define GPIO_OUT_PIN20_Pos   (20UL)
 
#define GPIO_OUT_PIN20_Msk   (0x1UL << GPIO_OUT_PIN20_Pos)
 
#define GPIO_OUT_PIN20_Low   (0UL)
 
#define GPIO_OUT_PIN20_High   (1UL)
 
#define GPIO_OUT_PIN19_Pos   (19UL)
 
#define GPIO_OUT_PIN19_Msk   (0x1UL << GPIO_OUT_PIN19_Pos)
 
#define GPIO_OUT_PIN19_Low   (0UL)
 
#define GPIO_OUT_PIN19_High   (1UL)
 
#define GPIO_OUT_PIN18_Pos   (18UL)
 
#define GPIO_OUT_PIN18_Msk   (0x1UL << GPIO_OUT_PIN18_Pos)
 
#define GPIO_OUT_PIN18_Low   (0UL)
 
#define GPIO_OUT_PIN18_High   (1UL)
 
#define GPIO_OUT_PIN17_Pos   (17UL)
 
#define GPIO_OUT_PIN17_Msk   (0x1UL << GPIO_OUT_PIN17_Pos)
 
#define GPIO_OUT_PIN17_Low   (0UL)
 
#define GPIO_OUT_PIN17_High   (1UL)
 
#define GPIO_OUT_PIN16_Pos   (16UL)
 
#define GPIO_OUT_PIN16_Msk   (0x1UL << GPIO_OUT_PIN16_Pos)
 
#define GPIO_OUT_PIN16_Low   (0UL)
 
#define GPIO_OUT_PIN16_High   (1UL)
 
#define GPIO_OUT_PIN15_Pos   (15UL)
 
#define GPIO_OUT_PIN15_Msk   (0x1UL << GPIO_OUT_PIN15_Pos)
 
#define GPIO_OUT_PIN15_Low   (0UL)
 
#define GPIO_OUT_PIN15_High   (1UL)
 
#define GPIO_OUT_PIN14_Pos   (14UL)
 
#define GPIO_OUT_PIN14_Msk   (0x1UL << GPIO_OUT_PIN14_Pos)
 
#define GPIO_OUT_PIN14_Low   (0UL)
 
#define GPIO_OUT_PIN14_High   (1UL)
 
#define GPIO_OUT_PIN13_Pos   (13UL)
 
#define GPIO_OUT_PIN13_Msk   (0x1UL << GPIO_OUT_PIN13_Pos)
 
#define GPIO_OUT_PIN13_Low   (0UL)
 
#define GPIO_OUT_PIN13_High   (1UL)
 
#define GPIO_OUT_PIN12_Pos   (12UL)
 
#define GPIO_OUT_PIN12_Msk   (0x1UL << GPIO_OUT_PIN12_Pos)
 
#define GPIO_OUT_PIN12_Low   (0UL)
 
#define GPIO_OUT_PIN12_High   (1UL)
 
#define GPIO_OUT_PIN11_Pos   (11UL)
 
#define GPIO_OUT_PIN11_Msk   (0x1UL << GPIO_OUT_PIN11_Pos)
 
#define GPIO_OUT_PIN11_Low   (0UL)
 
#define GPIO_OUT_PIN11_High   (1UL)
 
#define GPIO_OUT_PIN10_Pos   (10UL)
 
#define GPIO_OUT_PIN10_Msk   (0x1UL << GPIO_OUT_PIN10_Pos)
 
#define GPIO_OUT_PIN10_Low   (0UL)
 
#define GPIO_OUT_PIN10_High   (1UL)
 
#define GPIO_OUT_PIN9_Pos   (9UL)
 
#define GPIO_OUT_PIN9_Msk   (0x1UL << GPIO_OUT_PIN9_Pos)
 
#define GPIO_OUT_PIN9_Low   (0UL)
 
#define GPIO_OUT_PIN9_High   (1UL)
 
#define GPIO_OUT_PIN8_Pos   (8UL)
 
#define GPIO_OUT_PIN8_Msk   (0x1UL << GPIO_OUT_PIN8_Pos)
 
#define GPIO_OUT_PIN8_Low   (0UL)
 
#define GPIO_OUT_PIN8_High   (1UL)
 
#define GPIO_OUT_PIN7_Pos   (7UL)
 
#define GPIO_OUT_PIN7_Msk   (0x1UL << GPIO_OUT_PIN7_Pos)
 
#define GPIO_OUT_PIN7_Low   (0UL)
 
#define GPIO_OUT_PIN7_High   (1UL)
 
#define GPIO_OUT_PIN6_Pos   (6UL)
 
#define GPIO_OUT_PIN6_Msk   (0x1UL << GPIO_OUT_PIN6_Pos)
 
#define GPIO_OUT_PIN6_Low   (0UL)
 
#define GPIO_OUT_PIN6_High   (1UL)
 
#define GPIO_OUT_PIN5_Pos   (5UL)
 
#define GPIO_OUT_PIN5_Msk   (0x1UL << GPIO_OUT_PIN5_Pos)
 
#define GPIO_OUT_PIN5_Low   (0UL)
 
#define GPIO_OUT_PIN5_High   (1UL)
 
#define GPIO_OUT_PIN4_Pos   (4UL)
 
#define GPIO_OUT_PIN4_Msk   (0x1UL << GPIO_OUT_PIN4_Pos)
 
#define GPIO_OUT_PIN4_Low   (0UL)
 
#define GPIO_OUT_PIN4_High   (1UL)
 
#define GPIO_OUT_PIN3_Pos   (3UL)
 
#define GPIO_OUT_PIN3_Msk   (0x1UL << GPIO_OUT_PIN3_Pos)
 
#define GPIO_OUT_PIN3_Low   (0UL)
 
#define GPIO_OUT_PIN3_High   (1UL)
 
#define GPIO_OUT_PIN2_Pos   (2UL)
 
#define GPIO_OUT_PIN2_Msk   (0x1UL << GPIO_OUT_PIN2_Pos)
 
#define GPIO_OUT_PIN2_Low   (0UL)
 
#define GPIO_OUT_PIN2_High   (1UL)
 
#define GPIO_OUT_PIN1_Pos   (1UL)
 
#define GPIO_OUT_PIN1_Msk   (0x1UL << GPIO_OUT_PIN1_Pos)
 
#define GPIO_OUT_PIN1_Low   (0UL)
 
#define GPIO_OUT_PIN1_High   (1UL)
 
#define GPIO_OUT_PIN0_Pos   (0UL)
 
#define GPIO_OUT_PIN0_Msk   (0x1UL << GPIO_OUT_PIN0_Pos)
 
#define GPIO_OUT_PIN0_Low   (0UL)
 
#define GPIO_OUT_PIN0_High   (1UL)
 
#define GPIO_OUTSET_PIN31_Pos   (31UL)
 
#define GPIO_OUTSET_PIN31_Msk   (0x1UL << GPIO_OUTSET_PIN31_Pos)
 
#define GPIO_OUTSET_PIN31_Low   (0UL)
 
#define GPIO_OUTSET_PIN31_High   (1UL)
 
#define GPIO_OUTSET_PIN31_Set   (1UL)
 
#define GPIO_OUTSET_PIN30_Pos   (30UL)
 
#define GPIO_OUTSET_PIN30_Msk   (0x1UL << GPIO_OUTSET_PIN30_Pos)
 
#define GPIO_OUTSET_PIN30_Low   (0UL)
 
#define GPIO_OUTSET_PIN30_High   (1UL)
 
#define GPIO_OUTSET_PIN30_Set   (1UL)
 
#define GPIO_OUTSET_PIN29_Pos   (29UL)
 
#define GPIO_OUTSET_PIN29_Msk   (0x1UL << GPIO_OUTSET_PIN29_Pos)
 
#define GPIO_OUTSET_PIN29_Low   (0UL)
 
#define GPIO_OUTSET_PIN29_High   (1UL)
 
#define GPIO_OUTSET_PIN29_Set   (1UL)
 
#define GPIO_OUTSET_PIN28_Pos   (28UL)
 
#define GPIO_OUTSET_PIN28_Msk   (0x1UL << GPIO_OUTSET_PIN28_Pos)
 
#define GPIO_OUTSET_PIN28_Low   (0UL)
 
#define GPIO_OUTSET_PIN28_High   (1UL)
 
#define GPIO_OUTSET_PIN28_Set   (1UL)
 
#define GPIO_OUTSET_PIN27_Pos   (27UL)
 
#define GPIO_OUTSET_PIN27_Msk   (0x1UL << GPIO_OUTSET_PIN27_Pos)
 
#define GPIO_OUTSET_PIN27_Low   (0UL)
 
#define GPIO_OUTSET_PIN27_High   (1UL)
 
#define GPIO_OUTSET_PIN27_Set   (1UL)
 
#define GPIO_OUTSET_PIN26_Pos   (26UL)
 
#define GPIO_OUTSET_PIN26_Msk   (0x1UL << GPIO_OUTSET_PIN26_Pos)
 
#define GPIO_OUTSET_PIN26_Low   (0UL)
 
#define GPIO_OUTSET_PIN26_High   (1UL)
 
#define GPIO_OUTSET_PIN26_Set   (1UL)
 
#define GPIO_OUTSET_PIN25_Pos   (25UL)
 
#define GPIO_OUTSET_PIN25_Msk   (0x1UL << GPIO_OUTSET_PIN25_Pos)
 
#define GPIO_OUTSET_PIN25_Low   (0UL)
 
#define GPIO_OUTSET_PIN25_High   (1UL)
 
#define GPIO_OUTSET_PIN25_Set   (1UL)
 
#define GPIO_OUTSET_PIN24_Pos   (24UL)
 
#define GPIO_OUTSET_PIN24_Msk   (0x1UL << GPIO_OUTSET_PIN24_Pos)
 
#define GPIO_OUTSET_PIN24_Low   (0UL)
 
#define GPIO_OUTSET_PIN24_High   (1UL)
 
#define GPIO_OUTSET_PIN24_Set   (1UL)
 
#define GPIO_OUTSET_PIN23_Pos   (23UL)
 
#define GPIO_OUTSET_PIN23_Msk   (0x1UL << GPIO_OUTSET_PIN23_Pos)
 
#define GPIO_OUTSET_PIN23_Low   (0UL)
 
#define GPIO_OUTSET_PIN23_High   (1UL)
 
#define GPIO_OUTSET_PIN23_Set   (1UL)
 
#define GPIO_OUTSET_PIN22_Pos   (22UL)
 
#define GPIO_OUTSET_PIN22_Msk   (0x1UL << GPIO_OUTSET_PIN22_Pos)
 
#define GPIO_OUTSET_PIN22_Low   (0UL)
 
#define GPIO_OUTSET_PIN22_High   (1UL)
 
#define GPIO_OUTSET_PIN22_Set   (1UL)
 
#define GPIO_OUTSET_PIN21_Pos   (21UL)
 
#define GPIO_OUTSET_PIN21_Msk   (0x1UL << GPIO_OUTSET_PIN21_Pos)
 
#define GPIO_OUTSET_PIN21_Low   (0UL)
 
#define GPIO_OUTSET_PIN21_High   (1UL)
 
#define GPIO_OUTSET_PIN21_Set   (1UL)
 
#define GPIO_OUTSET_PIN20_Pos   (20UL)
 
#define GPIO_OUTSET_PIN20_Msk   (0x1UL << GPIO_OUTSET_PIN20_Pos)
 
#define GPIO_OUTSET_PIN20_Low   (0UL)
 
#define GPIO_OUTSET_PIN20_High   (1UL)
 
#define GPIO_OUTSET_PIN20_Set   (1UL)
 
#define GPIO_OUTSET_PIN19_Pos   (19UL)
 
#define GPIO_OUTSET_PIN19_Msk   (0x1UL << GPIO_OUTSET_PIN19_Pos)
 
#define GPIO_OUTSET_PIN19_Low   (0UL)
 
#define GPIO_OUTSET_PIN19_High   (1UL)
 
#define GPIO_OUTSET_PIN19_Set   (1UL)
 
#define GPIO_OUTSET_PIN18_Pos   (18UL)
 
#define GPIO_OUTSET_PIN18_Msk   (0x1UL << GPIO_OUTSET_PIN18_Pos)
 
#define GPIO_OUTSET_PIN18_Low   (0UL)
 
#define GPIO_OUTSET_PIN18_High   (1UL)
 
#define GPIO_OUTSET_PIN18_Set   (1UL)
 
#define GPIO_OUTSET_PIN17_Pos   (17UL)
 
#define GPIO_OUTSET_PIN17_Msk   (0x1UL << GPIO_OUTSET_PIN17_Pos)
 
#define GPIO_OUTSET_PIN17_Low   (0UL)
 
#define GPIO_OUTSET_PIN17_High   (1UL)
 
#define GPIO_OUTSET_PIN17_Set   (1UL)
 
#define GPIO_OUTSET_PIN16_Pos   (16UL)
 
#define GPIO_OUTSET_PIN16_Msk   (0x1UL << GPIO_OUTSET_PIN16_Pos)
 
#define GPIO_OUTSET_PIN16_Low   (0UL)
 
#define GPIO_OUTSET_PIN16_High   (1UL)
 
#define GPIO_OUTSET_PIN16_Set   (1UL)
 
#define GPIO_OUTSET_PIN15_Pos   (15UL)
 
#define GPIO_OUTSET_PIN15_Msk   (0x1UL << GPIO_OUTSET_PIN15_Pos)
 
#define GPIO_OUTSET_PIN15_Low   (0UL)
 
#define GPIO_OUTSET_PIN15_High   (1UL)
 
#define GPIO_OUTSET_PIN15_Set   (1UL)
 
#define GPIO_OUTSET_PIN14_Pos   (14UL)
 
#define GPIO_OUTSET_PIN14_Msk   (0x1UL << GPIO_OUTSET_PIN14_Pos)
 
#define GPIO_OUTSET_PIN14_Low   (0UL)
 
#define GPIO_OUTSET_PIN14_High   (1UL)
 
#define GPIO_OUTSET_PIN14_Set   (1UL)
 
#define GPIO_OUTSET_PIN13_Pos   (13UL)
 
#define GPIO_OUTSET_PIN13_Msk   (0x1UL << GPIO_OUTSET_PIN13_Pos)
 
#define GPIO_OUTSET_PIN13_Low   (0UL)
 
#define GPIO_OUTSET_PIN13_High   (1UL)
 
#define GPIO_OUTSET_PIN13_Set   (1UL)
 
#define GPIO_OUTSET_PIN12_Pos   (12UL)
 
#define GPIO_OUTSET_PIN12_Msk   (0x1UL << GPIO_OUTSET_PIN12_Pos)
 
#define GPIO_OUTSET_PIN12_Low   (0UL)
 
#define GPIO_OUTSET_PIN12_High   (1UL)
 
#define GPIO_OUTSET_PIN12_Set   (1UL)
 
#define GPIO_OUTSET_PIN11_Pos   (11UL)
 
#define GPIO_OUTSET_PIN11_Msk   (0x1UL << GPIO_OUTSET_PIN11_Pos)
 
#define GPIO_OUTSET_PIN11_Low   (0UL)
 
#define GPIO_OUTSET_PIN11_High   (1UL)
 
#define GPIO_OUTSET_PIN11_Set   (1UL)
 
#define GPIO_OUTSET_PIN10_Pos   (10UL)
 
#define GPIO_OUTSET_PIN10_Msk   (0x1UL << GPIO_OUTSET_PIN10_Pos)
 
#define GPIO_OUTSET_PIN10_Low   (0UL)
 
#define GPIO_OUTSET_PIN10_High   (1UL)
 
#define GPIO_OUTSET_PIN10_Set   (1UL)
 
#define GPIO_OUTSET_PIN9_Pos   (9UL)
 
#define GPIO_OUTSET_PIN9_Msk   (0x1UL << GPIO_OUTSET_PIN9_Pos)
 
#define GPIO_OUTSET_PIN9_Low   (0UL)
 
#define GPIO_OUTSET_PIN9_High   (1UL)
 
#define GPIO_OUTSET_PIN9_Set   (1UL)
 
#define GPIO_OUTSET_PIN8_Pos   (8UL)
 
#define GPIO_OUTSET_PIN8_Msk   (0x1UL << GPIO_OUTSET_PIN8_Pos)
 
#define GPIO_OUTSET_PIN8_Low   (0UL)
 
#define GPIO_OUTSET_PIN8_High   (1UL)
 
#define GPIO_OUTSET_PIN8_Set   (1UL)
 
#define GPIO_OUTSET_PIN7_Pos   (7UL)
 
#define GPIO_OUTSET_PIN7_Msk   (0x1UL << GPIO_OUTSET_PIN7_Pos)
 
#define GPIO_OUTSET_PIN7_Low   (0UL)
 
#define GPIO_OUTSET_PIN7_High   (1UL)
 
#define GPIO_OUTSET_PIN7_Set   (1UL)
 
#define GPIO_OUTSET_PIN6_Pos   (6UL)
 
#define GPIO_OUTSET_PIN6_Msk   (0x1UL << GPIO_OUTSET_PIN6_Pos)
 
#define GPIO_OUTSET_PIN6_Low   (0UL)
 
#define GPIO_OUTSET_PIN6_High   (1UL)
 
#define GPIO_OUTSET_PIN6_Set   (1UL)
 
#define GPIO_OUTSET_PIN5_Pos   (5UL)
 
#define GPIO_OUTSET_PIN5_Msk   (0x1UL << GPIO_OUTSET_PIN5_Pos)
 
#define GPIO_OUTSET_PIN5_Low   (0UL)
 
#define GPIO_OUTSET_PIN5_High   (1UL)
 
#define GPIO_OUTSET_PIN5_Set   (1UL)
 
#define GPIO_OUTSET_PIN4_Pos   (4UL)
 
#define GPIO_OUTSET_PIN4_Msk   (0x1UL << GPIO_OUTSET_PIN4_Pos)
 
#define GPIO_OUTSET_PIN4_Low   (0UL)
 
#define GPIO_OUTSET_PIN4_High   (1UL)
 
#define GPIO_OUTSET_PIN4_Set   (1UL)
 
#define GPIO_OUTSET_PIN3_Pos   (3UL)
 
#define GPIO_OUTSET_PIN3_Msk   (0x1UL << GPIO_OUTSET_PIN3_Pos)
 
#define GPIO_OUTSET_PIN3_Low   (0UL)
 
#define GPIO_OUTSET_PIN3_High   (1UL)
 
#define GPIO_OUTSET_PIN3_Set   (1UL)
 
#define GPIO_OUTSET_PIN2_Pos   (2UL)
 
#define GPIO_OUTSET_PIN2_Msk   (0x1UL << GPIO_OUTSET_PIN2_Pos)
 
#define GPIO_OUTSET_PIN2_Low   (0UL)
 
#define GPIO_OUTSET_PIN2_High   (1UL)
 
#define GPIO_OUTSET_PIN2_Set   (1UL)
 
#define GPIO_OUTSET_PIN1_Pos   (1UL)
 
#define GPIO_OUTSET_PIN1_Msk   (0x1UL << GPIO_OUTSET_PIN1_Pos)
 
#define GPIO_OUTSET_PIN1_Low   (0UL)
 
#define GPIO_OUTSET_PIN1_High   (1UL)
 
#define GPIO_OUTSET_PIN1_Set   (1UL)
 
#define GPIO_OUTSET_PIN0_Pos   (0UL)
 
#define GPIO_OUTSET_PIN0_Msk   (0x1UL << GPIO_OUTSET_PIN0_Pos)
 
#define GPIO_OUTSET_PIN0_Low   (0UL)
 
#define GPIO_OUTSET_PIN0_High   (1UL)
 
#define GPIO_OUTSET_PIN0_Set   (1UL)
 
#define GPIO_OUTCLR_PIN31_Pos   (31UL)
 
#define GPIO_OUTCLR_PIN31_Msk   (0x1UL << GPIO_OUTCLR_PIN31_Pos)
 
#define GPIO_OUTCLR_PIN31_Low   (0UL)
 
#define GPIO_OUTCLR_PIN31_High   (1UL)
 
#define GPIO_OUTCLR_PIN31_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN30_Pos   (30UL)
 
#define GPIO_OUTCLR_PIN30_Msk   (0x1UL << GPIO_OUTCLR_PIN30_Pos)
 
#define GPIO_OUTCLR_PIN30_Low   (0UL)
 
#define GPIO_OUTCLR_PIN30_High   (1UL)
 
#define GPIO_OUTCLR_PIN30_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN29_Pos   (29UL)
 
#define GPIO_OUTCLR_PIN29_Msk   (0x1UL << GPIO_OUTCLR_PIN29_Pos)
 
#define GPIO_OUTCLR_PIN29_Low   (0UL)
 
#define GPIO_OUTCLR_PIN29_High   (1UL)
 
#define GPIO_OUTCLR_PIN29_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN28_Pos   (28UL)
 
#define GPIO_OUTCLR_PIN28_Msk   (0x1UL << GPIO_OUTCLR_PIN28_Pos)
 
#define GPIO_OUTCLR_PIN28_Low   (0UL)
 
#define GPIO_OUTCLR_PIN28_High   (1UL)
 
#define GPIO_OUTCLR_PIN28_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN27_Pos   (27UL)
 
#define GPIO_OUTCLR_PIN27_Msk   (0x1UL << GPIO_OUTCLR_PIN27_Pos)
 
#define GPIO_OUTCLR_PIN27_Low   (0UL)
 
#define GPIO_OUTCLR_PIN27_High   (1UL)
 
#define GPIO_OUTCLR_PIN27_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN26_Pos   (26UL)
 
#define GPIO_OUTCLR_PIN26_Msk   (0x1UL << GPIO_OUTCLR_PIN26_Pos)
 
#define GPIO_OUTCLR_PIN26_Low   (0UL)
 
#define GPIO_OUTCLR_PIN26_High   (1UL)
 
#define GPIO_OUTCLR_PIN26_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN25_Pos   (25UL)
 
#define GPIO_OUTCLR_PIN25_Msk   (0x1UL << GPIO_OUTCLR_PIN25_Pos)
 
#define GPIO_OUTCLR_PIN25_Low   (0UL)
 
#define GPIO_OUTCLR_PIN25_High   (1UL)
 
#define GPIO_OUTCLR_PIN25_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN24_Pos   (24UL)
 
#define GPIO_OUTCLR_PIN24_Msk   (0x1UL << GPIO_OUTCLR_PIN24_Pos)
 
#define GPIO_OUTCLR_PIN24_Low   (0UL)
 
#define GPIO_OUTCLR_PIN24_High   (1UL)
 
#define GPIO_OUTCLR_PIN24_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN23_Pos   (23UL)
 
#define GPIO_OUTCLR_PIN23_Msk   (0x1UL << GPIO_OUTCLR_PIN23_Pos)
 
#define GPIO_OUTCLR_PIN23_Low   (0UL)
 
#define GPIO_OUTCLR_PIN23_High   (1UL)
 
#define GPIO_OUTCLR_PIN23_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN22_Pos   (22UL)
 
#define GPIO_OUTCLR_PIN22_Msk   (0x1UL << GPIO_OUTCLR_PIN22_Pos)
 
#define GPIO_OUTCLR_PIN22_Low   (0UL)
 
#define GPIO_OUTCLR_PIN22_High   (1UL)
 
#define GPIO_OUTCLR_PIN22_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN21_Pos   (21UL)
 
#define GPIO_OUTCLR_PIN21_Msk   (0x1UL << GPIO_OUTCLR_PIN21_Pos)
 
#define GPIO_OUTCLR_PIN21_Low   (0UL)
 
#define GPIO_OUTCLR_PIN21_High   (1UL)
 
#define GPIO_OUTCLR_PIN21_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN20_Pos   (20UL)
 
#define GPIO_OUTCLR_PIN20_Msk   (0x1UL << GPIO_OUTCLR_PIN20_Pos)
 
#define GPIO_OUTCLR_PIN20_Low   (0UL)
 
#define GPIO_OUTCLR_PIN20_High   (1UL)
 
#define GPIO_OUTCLR_PIN20_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN19_Pos   (19UL)
 
#define GPIO_OUTCLR_PIN19_Msk   (0x1UL << GPIO_OUTCLR_PIN19_Pos)
 
#define GPIO_OUTCLR_PIN19_Low   (0UL)
 
#define GPIO_OUTCLR_PIN19_High   (1UL)
 
#define GPIO_OUTCLR_PIN19_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN18_Pos   (18UL)
 
#define GPIO_OUTCLR_PIN18_Msk   (0x1UL << GPIO_OUTCLR_PIN18_Pos)
 
#define GPIO_OUTCLR_PIN18_Low   (0UL)
 
#define GPIO_OUTCLR_PIN18_High   (1UL)
 
#define GPIO_OUTCLR_PIN18_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN17_Pos   (17UL)
 
#define GPIO_OUTCLR_PIN17_Msk   (0x1UL << GPIO_OUTCLR_PIN17_Pos)
 
#define GPIO_OUTCLR_PIN17_Low   (0UL)
 
#define GPIO_OUTCLR_PIN17_High   (1UL)
 
#define GPIO_OUTCLR_PIN17_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN16_Pos   (16UL)
 
#define GPIO_OUTCLR_PIN16_Msk   (0x1UL << GPIO_OUTCLR_PIN16_Pos)
 
#define GPIO_OUTCLR_PIN16_Low   (0UL)
 
#define GPIO_OUTCLR_PIN16_High   (1UL)
 
#define GPIO_OUTCLR_PIN16_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN15_Pos   (15UL)
 
#define GPIO_OUTCLR_PIN15_Msk   (0x1UL << GPIO_OUTCLR_PIN15_Pos)
 
#define GPIO_OUTCLR_PIN15_Low   (0UL)
 
#define GPIO_OUTCLR_PIN15_High   (1UL)
 
#define GPIO_OUTCLR_PIN15_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN14_Pos   (14UL)
 
#define GPIO_OUTCLR_PIN14_Msk   (0x1UL << GPIO_OUTCLR_PIN14_Pos)
 
#define GPIO_OUTCLR_PIN14_Low   (0UL)
 
#define GPIO_OUTCLR_PIN14_High   (1UL)
 
#define GPIO_OUTCLR_PIN14_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN13_Pos   (13UL)
 
#define GPIO_OUTCLR_PIN13_Msk   (0x1UL << GPIO_OUTCLR_PIN13_Pos)
 
#define GPIO_OUTCLR_PIN13_Low   (0UL)
 
#define GPIO_OUTCLR_PIN13_High   (1UL)
 
#define GPIO_OUTCLR_PIN13_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN12_Pos   (12UL)
 
#define GPIO_OUTCLR_PIN12_Msk   (0x1UL << GPIO_OUTCLR_PIN12_Pos)
 
#define GPIO_OUTCLR_PIN12_Low   (0UL)
 
#define GPIO_OUTCLR_PIN12_High   (1UL)
 
#define GPIO_OUTCLR_PIN12_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN11_Pos   (11UL)
 
#define GPIO_OUTCLR_PIN11_Msk   (0x1UL << GPIO_OUTCLR_PIN11_Pos)
 
#define GPIO_OUTCLR_PIN11_Low   (0UL)
 
#define GPIO_OUTCLR_PIN11_High   (1UL)
 
#define GPIO_OUTCLR_PIN11_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN10_Pos   (10UL)
 
#define GPIO_OUTCLR_PIN10_Msk   (0x1UL << GPIO_OUTCLR_PIN10_Pos)
 
#define GPIO_OUTCLR_PIN10_Low   (0UL)
 
#define GPIO_OUTCLR_PIN10_High   (1UL)
 
#define GPIO_OUTCLR_PIN10_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN9_Pos   (9UL)
 
#define GPIO_OUTCLR_PIN9_Msk   (0x1UL << GPIO_OUTCLR_PIN9_Pos)
 
#define GPIO_OUTCLR_PIN9_Low   (0UL)
 
#define GPIO_OUTCLR_PIN9_High   (1UL)
 
#define GPIO_OUTCLR_PIN9_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN8_Pos   (8UL)
 
#define GPIO_OUTCLR_PIN8_Msk   (0x1UL << GPIO_OUTCLR_PIN8_Pos)
 
#define GPIO_OUTCLR_PIN8_Low   (0UL)
 
#define GPIO_OUTCLR_PIN8_High   (1UL)
 
#define GPIO_OUTCLR_PIN8_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN7_Pos   (7UL)
 
#define GPIO_OUTCLR_PIN7_Msk   (0x1UL << GPIO_OUTCLR_PIN7_Pos)
 
#define GPIO_OUTCLR_PIN7_Low   (0UL)
 
#define GPIO_OUTCLR_PIN7_High   (1UL)
 
#define GPIO_OUTCLR_PIN7_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN6_Pos   (6UL)
 
#define GPIO_OUTCLR_PIN6_Msk   (0x1UL << GPIO_OUTCLR_PIN6_Pos)
 
#define GPIO_OUTCLR_PIN6_Low   (0UL)
 
#define GPIO_OUTCLR_PIN6_High   (1UL)
 
#define GPIO_OUTCLR_PIN6_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN5_Pos   (5UL)
 
#define GPIO_OUTCLR_PIN5_Msk   (0x1UL << GPIO_OUTCLR_PIN5_Pos)
 
#define GPIO_OUTCLR_PIN5_Low   (0UL)
 
#define GPIO_OUTCLR_PIN5_High   (1UL)
 
#define GPIO_OUTCLR_PIN5_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN4_Pos   (4UL)
 
#define GPIO_OUTCLR_PIN4_Msk   (0x1UL << GPIO_OUTCLR_PIN4_Pos)
 
#define GPIO_OUTCLR_PIN4_Low   (0UL)
 
#define GPIO_OUTCLR_PIN4_High   (1UL)
 
#define GPIO_OUTCLR_PIN4_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN3_Pos   (3UL)
 
#define GPIO_OUTCLR_PIN3_Msk   (0x1UL << GPIO_OUTCLR_PIN3_Pos)
 
#define GPIO_OUTCLR_PIN3_Low   (0UL)
 
#define GPIO_OUTCLR_PIN3_High   (1UL)
 
#define GPIO_OUTCLR_PIN3_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN2_Pos   (2UL)
 
#define GPIO_OUTCLR_PIN2_Msk   (0x1UL << GPIO_OUTCLR_PIN2_Pos)
 
#define GPIO_OUTCLR_PIN2_Low   (0UL)
 
#define GPIO_OUTCLR_PIN2_High   (1UL)
 
#define GPIO_OUTCLR_PIN2_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN1_Pos   (1UL)
 
#define GPIO_OUTCLR_PIN1_Msk   (0x1UL << GPIO_OUTCLR_PIN1_Pos)
 
#define GPIO_OUTCLR_PIN1_Low   (0UL)
 
#define GPIO_OUTCLR_PIN1_High   (1UL)
 
#define GPIO_OUTCLR_PIN1_Clear   (1UL)
 
#define GPIO_OUTCLR_PIN0_Pos   (0UL)
 
#define GPIO_OUTCLR_PIN0_Msk   (0x1UL << GPIO_OUTCLR_PIN0_Pos)
 
#define GPIO_OUTCLR_PIN0_Low   (0UL)
 
#define GPIO_OUTCLR_PIN0_High   (1UL)
 
#define GPIO_OUTCLR_PIN0_Clear   (1UL)
 
#define GPIO_IN_PIN31_Pos   (31UL)
 
#define GPIO_IN_PIN31_Msk   (0x1UL << GPIO_IN_PIN31_Pos)
 
#define GPIO_IN_PIN31_Low   (0UL)
 
#define GPIO_IN_PIN31_High   (1UL)
 
#define GPIO_IN_PIN30_Pos   (30UL)
 
#define GPIO_IN_PIN30_Msk   (0x1UL << GPIO_IN_PIN30_Pos)
 
#define GPIO_IN_PIN30_Low   (0UL)
 
#define GPIO_IN_PIN30_High   (1UL)
 
#define GPIO_IN_PIN29_Pos   (29UL)
 
#define GPIO_IN_PIN29_Msk   (0x1UL << GPIO_IN_PIN29_Pos)
 
#define GPIO_IN_PIN29_Low   (0UL)
 
#define GPIO_IN_PIN29_High   (1UL)
 
#define GPIO_IN_PIN28_Pos   (28UL)
 
#define GPIO_IN_PIN28_Msk   (0x1UL << GPIO_IN_PIN28_Pos)
 
#define GPIO_IN_PIN28_Low   (0UL)
 
#define GPIO_IN_PIN28_High   (1UL)
 
#define GPIO_IN_PIN27_Pos   (27UL)
 
#define GPIO_IN_PIN27_Msk   (0x1UL << GPIO_IN_PIN27_Pos)
 
#define GPIO_IN_PIN27_Low   (0UL)
 
#define GPIO_IN_PIN27_High   (1UL)
 
#define GPIO_IN_PIN26_Pos   (26UL)
 
#define GPIO_IN_PIN26_Msk   (0x1UL << GPIO_IN_PIN26_Pos)
 
#define GPIO_IN_PIN26_Low   (0UL)
 
#define GPIO_IN_PIN26_High   (1UL)
 
#define GPIO_IN_PIN25_Pos   (25UL)
 
#define GPIO_IN_PIN25_Msk   (0x1UL << GPIO_IN_PIN25_Pos)
 
#define GPIO_IN_PIN25_Low   (0UL)
 
#define GPIO_IN_PIN25_High   (1UL)
 
#define GPIO_IN_PIN24_Pos   (24UL)
 
#define GPIO_IN_PIN24_Msk   (0x1UL << GPIO_IN_PIN24_Pos)
 
#define GPIO_IN_PIN24_Low   (0UL)
 
#define GPIO_IN_PIN24_High   (1UL)
 
#define GPIO_IN_PIN23_Pos   (23UL)
 
#define GPIO_IN_PIN23_Msk   (0x1UL << GPIO_IN_PIN23_Pos)
 
#define GPIO_IN_PIN23_Low   (0UL)
 
#define GPIO_IN_PIN23_High   (1UL)
 
#define GPIO_IN_PIN22_Pos   (22UL)
 
#define GPIO_IN_PIN22_Msk   (0x1UL << GPIO_IN_PIN22_Pos)
 
#define GPIO_IN_PIN22_Low   (0UL)
 
#define GPIO_IN_PIN22_High   (1UL)
 
#define GPIO_IN_PIN21_Pos   (21UL)
 
#define GPIO_IN_PIN21_Msk   (0x1UL << GPIO_IN_PIN21_Pos)
 
#define GPIO_IN_PIN21_Low   (0UL)
 
#define GPIO_IN_PIN21_High   (1UL)
 
#define GPIO_IN_PIN20_Pos   (20UL)
 
#define GPIO_IN_PIN20_Msk   (0x1UL << GPIO_IN_PIN20_Pos)
 
#define GPIO_IN_PIN20_Low   (0UL)
 
#define GPIO_IN_PIN20_High   (1UL)
 
#define GPIO_IN_PIN19_Pos   (19UL)
 
#define GPIO_IN_PIN19_Msk   (0x1UL << GPIO_IN_PIN19_Pos)
 
#define GPIO_IN_PIN19_Low   (0UL)
 
#define GPIO_IN_PIN19_High   (1UL)
 
#define GPIO_IN_PIN18_Pos   (18UL)
 
#define GPIO_IN_PIN18_Msk   (0x1UL << GPIO_IN_PIN18_Pos)
 
#define GPIO_IN_PIN18_Low   (0UL)
 
#define GPIO_IN_PIN18_High   (1UL)
 
#define GPIO_IN_PIN17_Pos   (17UL)
 
#define GPIO_IN_PIN17_Msk   (0x1UL << GPIO_IN_PIN17_Pos)
 
#define GPIO_IN_PIN17_Low   (0UL)
 
#define GPIO_IN_PIN17_High   (1UL)
 
#define GPIO_IN_PIN16_Pos   (16UL)
 
#define GPIO_IN_PIN16_Msk   (0x1UL << GPIO_IN_PIN16_Pos)
 
#define GPIO_IN_PIN16_Low   (0UL)
 
#define GPIO_IN_PIN16_High   (1UL)
 
#define GPIO_IN_PIN15_Pos   (15UL)
 
#define GPIO_IN_PIN15_Msk   (0x1UL << GPIO_IN_PIN15_Pos)
 
#define GPIO_IN_PIN15_Low   (0UL)
 
#define GPIO_IN_PIN15_High   (1UL)
 
#define GPIO_IN_PIN14_Pos   (14UL)
 
#define GPIO_IN_PIN14_Msk   (0x1UL << GPIO_IN_PIN14_Pos)
 
#define GPIO_IN_PIN14_Low   (0UL)
 
#define GPIO_IN_PIN14_High   (1UL)
 
#define GPIO_IN_PIN13_Pos   (13UL)
 
#define GPIO_IN_PIN13_Msk   (0x1UL << GPIO_IN_PIN13_Pos)
 
#define GPIO_IN_PIN13_Low   (0UL)
 
#define GPIO_IN_PIN13_High   (1UL)
 
#define GPIO_IN_PIN12_Pos   (12UL)
 
#define GPIO_IN_PIN12_Msk   (0x1UL << GPIO_IN_PIN12_Pos)
 
#define GPIO_IN_PIN12_Low   (0UL)
 
#define GPIO_IN_PIN12_High   (1UL)
 
#define GPIO_IN_PIN11_Pos   (11UL)
 
#define GPIO_IN_PIN11_Msk   (0x1UL << GPIO_IN_PIN11_Pos)
 
#define GPIO_IN_PIN11_Low   (0UL)
 
#define GPIO_IN_PIN11_High   (1UL)
 
#define GPIO_IN_PIN10_Pos   (10UL)
 
#define GPIO_IN_PIN10_Msk   (0x1UL << GPIO_IN_PIN10_Pos)
 
#define GPIO_IN_PIN10_Low   (0UL)
 
#define GPIO_IN_PIN10_High   (1UL)
 
#define GPIO_IN_PIN9_Pos   (9UL)
 
#define GPIO_IN_PIN9_Msk   (0x1UL << GPIO_IN_PIN9_Pos)
 
#define GPIO_IN_PIN9_Low   (0UL)
 
#define GPIO_IN_PIN9_High   (1UL)
 
#define GPIO_IN_PIN8_Pos   (8UL)
 
#define GPIO_IN_PIN8_Msk   (0x1UL << GPIO_IN_PIN8_Pos)
 
#define GPIO_IN_PIN8_Low   (0UL)
 
#define GPIO_IN_PIN8_High   (1UL)
 
#define GPIO_IN_PIN7_Pos   (7UL)
 
#define GPIO_IN_PIN7_Msk   (0x1UL << GPIO_IN_PIN7_Pos)
 
#define GPIO_IN_PIN7_Low   (0UL)
 
#define GPIO_IN_PIN7_High   (1UL)
 
#define GPIO_IN_PIN6_Pos   (6UL)
 
#define GPIO_IN_PIN6_Msk   (0x1UL << GPIO_IN_PIN6_Pos)
 
#define GPIO_IN_PIN6_Low   (0UL)
 
#define GPIO_IN_PIN6_High   (1UL)
 
#define GPIO_IN_PIN5_Pos   (5UL)
 
#define GPIO_IN_PIN5_Msk   (0x1UL << GPIO_IN_PIN5_Pos)
 
#define GPIO_IN_PIN5_Low   (0UL)
 
#define GPIO_IN_PIN5_High   (1UL)
 
#define GPIO_IN_PIN4_Pos   (4UL)
 
#define GPIO_IN_PIN4_Msk   (0x1UL << GPIO_IN_PIN4_Pos)
 
#define GPIO_IN_PIN4_Low   (0UL)
 
#define GPIO_IN_PIN4_High   (1UL)
 
#define GPIO_IN_PIN3_Pos   (3UL)
 
#define GPIO_IN_PIN3_Msk   (0x1UL << GPIO_IN_PIN3_Pos)
 
#define GPIO_IN_PIN3_Low   (0UL)
 
#define GPIO_IN_PIN3_High   (1UL)
 
#define GPIO_IN_PIN2_Pos   (2UL)
 
#define GPIO_IN_PIN2_Msk   (0x1UL << GPIO_IN_PIN2_Pos)
 
#define GPIO_IN_PIN2_Low   (0UL)
 
#define GPIO_IN_PIN2_High   (1UL)
 
#define GPIO_IN_PIN1_Pos   (1UL)
 
#define GPIO_IN_PIN1_Msk   (0x1UL << GPIO_IN_PIN1_Pos)
 
#define GPIO_IN_PIN1_Low   (0UL)
 
#define GPIO_IN_PIN1_High   (1UL)
 
#define GPIO_IN_PIN0_Pos   (0UL)
 
#define GPIO_IN_PIN0_Msk   (0x1UL << GPIO_IN_PIN0_Pos)
 
#define GPIO_IN_PIN0_Low   (0UL)
 
#define GPIO_IN_PIN0_High   (1UL)
 
#define GPIO_DIR_PIN31_Pos   (31UL)
 
#define GPIO_DIR_PIN31_Msk   (0x1UL << GPIO_DIR_PIN31_Pos)
 
#define GPIO_DIR_PIN31_Input   (0UL)
 
#define GPIO_DIR_PIN31_Output   (1UL)
 
#define GPIO_DIR_PIN30_Pos   (30UL)
 
#define GPIO_DIR_PIN30_Msk   (0x1UL << GPIO_DIR_PIN30_Pos)
 
#define GPIO_DIR_PIN30_Input   (0UL)
 
#define GPIO_DIR_PIN30_Output   (1UL)
 
#define GPIO_DIR_PIN29_Pos   (29UL)
 
#define GPIO_DIR_PIN29_Msk   (0x1UL << GPIO_DIR_PIN29_Pos)
 
#define GPIO_DIR_PIN29_Input   (0UL)
 
#define GPIO_DIR_PIN29_Output   (1UL)
 
#define GPIO_DIR_PIN28_Pos   (28UL)
 
#define GPIO_DIR_PIN28_Msk   (0x1UL << GPIO_DIR_PIN28_Pos)
 
#define GPIO_DIR_PIN28_Input   (0UL)
 
#define GPIO_DIR_PIN28_Output   (1UL)
 
#define GPIO_DIR_PIN27_Pos   (27UL)
 
#define GPIO_DIR_PIN27_Msk   (0x1UL << GPIO_DIR_PIN27_Pos)
 
#define GPIO_DIR_PIN27_Input   (0UL)
 
#define GPIO_DIR_PIN27_Output   (1UL)
 
#define GPIO_DIR_PIN26_Pos   (26UL)
 
#define GPIO_DIR_PIN26_Msk   (0x1UL << GPIO_DIR_PIN26_Pos)
 
#define GPIO_DIR_PIN26_Input   (0UL)
 
#define GPIO_DIR_PIN26_Output   (1UL)
 
#define GPIO_DIR_PIN25_Pos   (25UL)
 
#define GPIO_DIR_PIN25_Msk   (0x1UL << GPIO_DIR_PIN25_Pos)
 
#define GPIO_DIR_PIN25_Input   (0UL)
 
#define GPIO_DIR_PIN25_Output   (1UL)
 
#define GPIO_DIR_PIN24_Pos   (24UL)
 
#define GPIO_DIR_PIN24_Msk   (0x1UL << GPIO_DIR_PIN24_Pos)
 
#define GPIO_DIR_PIN24_Input   (0UL)
 
#define GPIO_DIR_PIN24_Output   (1UL)
 
#define GPIO_DIR_PIN23_Pos   (23UL)
 
#define GPIO_DIR_PIN23_Msk   (0x1UL << GPIO_DIR_PIN23_Pos)
 
#define GPIO_DIR_PIN23_Input   (0UL)
 
#define GPIO_DIR_PIN23_Output   (1UL)
 
#define GPIO_DIR_PIN22_Pos   (22UL)
 
#define GPIO_DIR_PIN22_Msk   (0x1UL << GPIO_DIR_PIN22_Pos)
 
#define GPIO_DIR_PIN22_Input   (0UL)
 
#define GPIO_DIR_PIN22_Output   (1UL)
 
#define GPIO_DIR_PIN21_Pos   (21UL)
 
#define GPIO_DIR_PIN21_Msk   (0x1UL << GPIO_DIR_PIN21_Pos)
 
#define GPIO_DIR_PIN21_Input   (0UL)
 
#define GPIO_DIR_PIN21_Output   (1UL)
 
#define GPIO_DIR_PIN20_Pos   (20UL)
 
#define GPIO_DIR_PIN20_Msk   (0x1UL << GPIO_DIR_PIN20_Pos)
 
#define GPIO_DIR_PIN20_Input   (0UL)
 
#define GPIO_DIR_PIN20_Output   (1UL)
 
#define GPIO_DIR_PIN19_Pos   (19UL)
 
#define GPIO_DIR_PIN19_Msk   (0x1UL << GPIO_DIR_PIN19_Pos)
 
#define GPIO_DIR_PIN19_Input   (0UL)
 
#define GPIO_DIR_PIN19_Output   (1UL)
 
#define GPIO_DIR_PIN18_Pos   (18UL)
 
#define GPIO_DIR_PIN18_Msk   (0x1UL << GPIO_DIR_PIN18_Pos)
 
#define GPIO_DIR_PIN18_Input   (0UL)
 
#define GPIO_DIR_PIN18_Output   (1UL)
 
#define GPIO_DIR_PIN17_Pos   (17UL)
 
#define GPIO_DIR_PIN17_Msk   (0x1UL << GPIO_DIR_PIN17_Pos)
 
#define GPIO_DIR_PIN17_Input   (0UL)
 
#define GPIO_DIR_PIN17_Output   (1UL)
 
#define GPIO_DIR_PIN16_Pos   (16UL)
 
#define GPIO_DIR_PIN16_Msk   (0x1UL << GPIO_DIR_PIN16_Pos)
 
#define GPIO_DIR_PIN16_Input   (0UL)
 
#define GPIO_DIR_PIN16_Output   (1UL)
 
#define GPIO_DIR_PIN15_Pos   (15UL)
 
#define GPIO_DIR_PIN15_Msk   (0x1UL << GPIO_DIR_PIN15_Pos)
 
#define GPIO_DIR_PIN15_Input   (0UL)
 
#define GPIO_DIR_PIN15_Output   (1UL)
 
#define GPIO_DIR_PIN14_Pos   (14UL)
 
#define GPIO_DIR_PIN14_Msk   (0x1UL << GPIO_DIR_PIN14_Pos)
 
#define GPIO_DIR_PIN14_Input   (0UL)
 
#define GPIO_DIR_PIN14_Output   (1UL)
 
#define GPIO_DIR_PIN13_Pos   (13UL)
 
#define GPIO_DIR_PIN13_Msk   (0x1UL << GPIO_DIR_PIN13_Pos)
 
#define GPIO_DIR_PIN13_Input   (0UL)
 
#define GPIO_DIR_PIN13_Output   (1UL)
 
#define GPIO_DIR_PIN12_Pos   (12UL)
 
#define GPIO_DIR_PIN12_Msk   (0x1UL << GPIO_DIR_PIN12_Pos)
 
#define GPIO_DIR_PIN12_Input   (0UL)
 
#define GPIO_DIR_PIN12_Output   (1UL)
 
#define GPIO_DIR_PIN11_Pos   (11UL)
 
#define GPIO_DIR_PIN11_Msk   (0x1UL << GPIO_DIR_PIN11_Pos)
 
#define GPIO_DIR_PIN11_Input   (0UL)
 
#define GPIO_DIR_PIN11_Output   (1UL)
 
#define GPIO_DIR_PIN10_Pos   (10UL)
 
#define GPIO_DIR_PIN10_Msk   (0x1UL << GPIO_DIR_PIN10_Pos)
 
#define GPIO_DIR_PIN10_Input   (0UL)
 
#define GPIO_DIR_PIN10_Output   (1UL)
 
#define GPIO_DIR_PIN9_Pos   (9UL)
 
#define GPIO_DIR_PIN9_Msk   (0x1UL << GPIO_DIR_PIN9_Pos)
 
#define GPIO_DIR_PIN9_Input   (0UL)
 
#define GPIO_DIR_PIN9_Output   (1UL)
 
#define GPIO_DIR_PIN8_Pos   (8UL)
 
#define GPIO_DIR_PIN8_Msk   (0x1UL << GPIO_DIR_PIN8_Pos)
 
#define GPIO_DIR_PIN8_Input   (0UL)
 
#define GPIO_DIR_PIN8_Output   (1UL)
 
#define GPIO_DIR_PIN7_Pos   (7UL)
 
#define GPIO_DIR_PIN7_Msk   (0x1UL << GPIO_DIR_PIN7_Pos)
 
#define GPIO_DIR_PIN7_Input   (0UL)
 
#define GPIO_DIR_PIN7_Output   (1UL)
 
#define GPIO_DIR_PIN6_Pos   (6UL)
 
#define GPIO_DIR_PIN6_Msk   (0x1UL << GPIO_DIR_PIN6_Pos)
 
#define GPIO_DIR_PIN6_Input   (0UL)
 
#define GPIO_DIR_PIN6_Output   (1UL)
 
#define GPIO_DIR_PIN5_Pos   (5UL)
 
#define GPIO_DIR_PIN5_Msk   (0x1UL << GPIO_DIR_PIN5_Pos)
 
#define GPIO_DIR_PIN5_Input   (0UL)
 
#define GPIO_DIR_PIN5_Output   (1UL)
 
#define GPIO_DIR_PIN4_Pos   (4UL)
 
#define GPIO_DIR_PIN4_Msk   (0x1UL << GPIO_DIR_PIN4_Pos)
 
#define GPIO_DIR_PIN4_Input   (0UL)
 
#define GPIO_DIR_PIN4_Output   (1UL)
 
#define GPIO_DIR_PIN3_Pos   (3UL)
 
#define GPIO_DIR_PIN3_Msk   (0x1UL << GPIO_DIR_PIN3_Pos)
 
#define GPIO_DIR_PIN3_Input   (0UL)
 
#define GPIO_DIR_PIN3_Output   (1UL)
 
#define GPIO_DIR_PIN2_Pos   (2UL)
 
#define GPIO_DIR_PIN2_Msk   (0x1UL << GPIO_DIR_PIN2_Pos)
 
#define GPIO_DIR_PIN2_Input   (0UL)
 
#define GPIO_DIR_PIN2_Output   (1UL)
 
#define GPIO_DIR_PIN1_Pos   (1UL)
 
#define GPIO_DIR_PIN1_Msk   (0x1UL << GPIO_DIR_PIN1_Pos)
 
#define GPIO_DIR_PIN1_Input   (0UL)
 
#define GPIO_DIR_PIN1_Output   (1UL)
 
#define GPIO_DIR_PIN0_Pos   (0UL)
 
#define GPIO_DIR_PIN0_Msk   (0x1UL << GPIO_DIR_PIN0_Pos)
 
#define GPIO_DIR_PIN0_Input   (0UL)
 
#define GPIO_DIR_PIN0_Output   (1UL)
 
#define GPIO_DIRSET_PIN31_Pos   (31UL)
 
#define GPIO_DIRSET_PIN31_Msk   (0x1UL << GPIO_DIRSET_PIN31_Pos)
 
#define GPIO_DIRSET_PIN31_Input   (0UL)
 
#define GPIO_DIRSET_PIN31_Output   (1UL)
 
#define GPIO_DIRSET_PIN31_Set   (1UL)
 
#define GPIO_DIRSET_PIN30_Pos   (30UL)
 
#define GPIO_DIRSET_PIN30_Msk   (0x1UL << GPIO_DIRSET_PIN30_Pos)
 
#define GPIO_DIRSET_PIN30_Input   (0UL)
 
#define GPIO_DIRSET_PIN30_Output   (1UL)
 
#define GPIO_DIRSET_PIN30_Set   (1UL)
 
#define GPIO_DIRSET_PIN29_Pos   (29UL)
 
#define GPIO_DIRSET_PIN29_Msk   (0x1UL << GPIO_DIRSET_PIN29_Pos)
 
#define GPIO_DIRSET_PIN29_Input   (0UL)
 
#define GPIO_DIRSET_PIN29_Output   (1UL)
 
#define GPIO_DIRSET_PIN29_Set   (1UL)
 
#define GPIO_DIRSET_PIN28_Pos   (28UL)
 
#define GPIO_DIRSET_PIN28_Msk   (0x1UL << GPIO_DIRSET_PIN28_Pos)
 
#define GPIO_DIRSET_PIN28_Input   (0UL)
 
#define GPIO_DIRSET_PIN28_Output   (1UL)
 
#define GPIO_DIRSET_PIN28_Set   (1UL)
 
#define GPIO_DIRSET_PIN27_Pos   (27UL)
 
#define GPIO_DIRSET_PIN27_Msk   (0x1UL << GPIO_DIRSET_PIN27_Pos)
 
#define GPIO_DIRSET_PIN27_Input   (0UL)
 
#define GPIO_DIRSET_PIN27_Output   (1UL)
 
#define GPIO_DIRSET_PIN27_Set   (1UL)
 
#define GPIO_DIRSET_PIN26_Pos   (26UL)
 
#define GPIO_DIRSET_PIN26_Msk   (0x1UL << GPIO_DIRSET_PIN26_Pos)
 
#define GPIO_DIRSET_PIN26_Input   (0UL)
 
#define GPIO_DIRSET_PIN26_Output   (1UL)
 
#define GPIO_DIRSET_PIN26_Set   (1UL)
 
#define GPIO_DIRSET_PIN25_Pos   (25UL)
 
#define GPIO_DIRSET_PIN25_Msk   (0x1UL << GPIO_DIRSET_PIN25_Pos)
 
#define GPIO_DIRSET_PIN25_Input   (0UL)
 
#define GPIO_DIRSET_PIN25_Output   (1UL)
 
#define GPIO_DIRSET_PIN25_Set   (1UL)
 
#define GPIO_DIRSET_PIN24_Pos   (24UL)
 
#define GPIO_DIRSET_PIN24_Msk   (0x1UL << GPIO_DIRSET_PIN24_Pos)
 
#define GPIO_DIRSET_PIN24_Input   (0UL)
 
#define GPIO_DIRSET_PIN24_Output   (1UL)
 
#define GPIO_DIRSET_PIN24_Set   (1UL)
 
#define GPIO_DIRSET_PIN23_Pos   (23UL)
 
#define GPIO_DIRSET_PIN23_Msk   (0x1UL << GPIO_DIRSET_PIN23_Pos)
 
#define GPIO_DIRSET_PIN23_Input   (0UL)
 
#define GPIO_DIRSET_PIN23_Output   (1UL)
 
#define GPIO_DIRSET_PIN23_Set   (1UL)
 
#define GPIO_DIRSET_PIN22_Pos   (22UL)
 
#define GPIO_DIRSET_PIN22_Msk   (0x1UL << GPIO_DIRSET_PIN22_Pos)
 
#define GPIO_DIRSET_PIN22_Input   (0UL)
 
#define GPIO_DIRSET_PIN22_Output   (1UL)
 
#define GPIO_DIRSET_PIN22_Set   (1UL)
 
#define GPIO_DIRSET_PIN21_Pos   (21UL)
 
#define GPIO_DIRSET_PIN21_Msk   (0x1UL << GPIO_DIRSET_PIN21_Pos)
 
#define GPIO_DIRSET_PIN21_Input   (0UL)
 
#define GPIO_DIRSET_PIN21_Output   (1UL)
 
#define GPIO_DIRSET_PIN21_Set   (1UL)
 
#define GPIO_DIRSET_PIN20_Pos   (20UL)
 
#define GPIO_DIRSET_PIN20_Msk   (0x1UL << GPIO_DIRSET_PIN20_Pos)
 
#define GPIO_DIRSET_PIN20_Input   (0UL)
 
#define GPIO_DIRSET_PIN20_Output   (1UL)
 
#define GPIO_DIRSET_PIN20_Set   (1UL)
 
#define GPIO_DIRSET_PIN19_Pos   (19UL)
 
#define GPIO_DIRSET_PIN19_Msk   (0x1UL << GPIO_DIRSET_PIN19_Pos)
 
#define GPIO_DIRSET_PIN19_Input   (0UL)
 
#define GPIO_DIRSET_PIN19_Output   (1UL)
 
#define GPIO_DIRSET_PIN19_Set   (1UL)
 
#define GPIO_DIRSET_PIN18_Pos   (18UL)
 
#define GPIO_DIRSET_PIN18_Msk   (0x1UL << GPIO_DIRSET_PIN18_Pos)
 
#define GPIO_DIRSET_PIN18_Input   (0UL)
 
#define GPIO_DIRSET_PIN18_Output   (1UL)
 
#define GPIO_DIRSET_PIN18_Set   (1UL)
 
#define GPIO_DIRSET_PIN17_Pos   (17UL)
 
#define GPIO_DIRSET_PIN17_Msk   (0x1UL << GPIO_DIRSET_PIN17_Pos)
 
#define GPIO_DIRSET_PIN17_Input   (0UL)
 
#define GPIO_DIRSET_PIN17_Output   (1UL)
 
#define GPIO_DIRSET_PIN17_Set   (1UL)
 
#define GPIO_DIRSET_PIN16_Pos   (16UL)
 
#define GPIO_DIRSET_PIN16_Msk   (0x1UL << GPIO_DIRSET_PIN16_Pos)
 
#define GPIO_DIRSET_PIN16_Input   (0UL)
 
#define GPIO_DIRSET_PIN16_Output   (1UL)
 
#define GPIO_DIRSET_PIN16_Set   (1UL)
 
#define GPIO_DIRSET_PIN15_Pos   (15UL)
 
#define GPIO_DIRSET_PIN15_Msk   (0x1UL << GPIO_DIRSET_PIN15_Pos)
 
#define GPIO_DIRSET_PIN15_Input   (0UL)
 
#define GPIO_DIRSET_PIN15_Output   (1UL)
 
#define GPIO_DIRSET_PIN15_Set   (1UL)
 
#define GPIO_DIRSET_PIN14_Pos   (14UL)
 
#define GPIO_DIRSET_PIN14_Msk   (0x1UL << GPIO_DIRSET_PIN14_Pos)
 
#define GPIO_DIRSET_PIN14_Input   (0UL)
 
#define GPIO_DIRSET_PIN14_Output   (1UL)
 
#define GPIO_DIRSET_PIN14_Set   (1UL)
 
#define GPIO_DIRSET_PIN13_Pos   (13UL)
 
#define GPIO_DIRSET_PIN13_Msk   (0x1UL << GPIO_DIRSET_PIN13_Pos)
 
#define GPIO_DIRSET_PIN13_Input   (0UL)
 
#define GPIO_DIRSET_PIN13_Output   (1UL)
 
#define GPIO_DIRSET_PIN13_Set   (1UL)
 
#define GPIO_DIRSET_PIN12_Pos   (12UL)
 
#define GPIO_DIRSET_PIN12_Msk   (0x1UL << GPIO_DIRSET_PIN12_Pos)
 
#define GPIO_DIRSET_PIN12_Input   (0UL)
 
#define GPIO_DIRSET_PIN12_Output   (1UL)
 
#define GPIO_DIRSET_PIN12_Set   (1UL)
 
#define GPIO_DIRSET_PIN11_Pos   (11UL)
 
#define GPIO_DIRSET_PIN11_Msk   (0x1UL << GPIO_DIRSET_PIN11_Pos)
 
#define GPIO_DIRSET_PIN11_Input   (0UL)
 
#define GPIO_DIRSET_PIN11_Output   (1UL)
 
#define GPIO_DIRSET_PIN11_Set   (1UL)
 
#define GPIO_DIRSET_PIN10_Pos   (10UL)
 
#define GPIO_DIRSET_PIN10_Msk   (0x1UL << GPIO_DIRSET_PIN10_Pos)
 
#define GPIO_DIRSET_PIN10_Input   (0UL)
 
#define GPIO_DIRSET_PIN10_Output   (1UL)
 
#define GPIO_DIRSET_PIN10_Set   (1UL)
 
#define GPIO_DIRSET_PIN9_Pos   (9UL)
 
#define GPIO_DIRSET_PIN9_Msk   (0x1UL << GPIO_DIRSET_PIN9_Pos)
 
#define GPIO_DIRSET_PIN9_Input   (0UL)
 
#define GPIO_DIRSET_PIN9_Output   (1UL)
 
#define GPIO_DIRSET_PIN9_Set   (1UL)
 
#define GPIO_DIRSET_PIN8_Pos   (8UL)
 
#define GPIO_DIRSET_PIN8_Msk   (0x1UL << GPIO_DIRSET_PIN8_Pos)
 
#define GPIO_DIRSET_PIN8_Input   (0UL)
 
#define GPIO_DIRSET_PIN8_Output   (1UL)
 
#define GPIO_DIRSET_PIN8_Set   (1UL)
 
#define GPIO_DIRSET_PIN7_Pos   (7UL)
 
#define GPIO_DIRSET_PIN7_Msk   (0x1UL << GPIO_DIRSET_PIN7_Pos)
 
#define GPIO_DIRSET_PIN7_Input   (0UL)
 
#define GPIO_DIRSET_PIN7_Output   (1UL)
 
#define GPIO_DIRSET_PIN7_Set   (1UL)
 
#define GPIO_DIRSET_PIN6_Pos   (6UL)
 
#define GPIO_DIRSET_PIN6_Msk   (0x1UL << GPIO_DIRSET_PIN6_Pos)
 
#define GPIO_DIRSET_PIN6_Input   (0UL)
 
#define GPIO_DIRSET_PIN6_Output   (1UL)
 
#define GPIO_DIRSET_PIN6_Set   (1UL)
 
#define GPIO_DIRSET_PIN5_Pos   (5UL)
 
#define GPIO_DIRSET_PIN5_Msk   (0x1UL << GPIO_DIRSET_PIN5_Pos)
 
#define GPIO_DIRSET_PIN5_Input   (0UL)
 
#define GPIO_DIRSET_PIN5_Output   (1UL)
 
#define GPIO_DIRSET_PIN5_Set   (1UL)
 
#define GPIO_DIRSET_PIN4_Pos   (4UL)
 
#define GPIO_DIRSET_PIN4_Msk   (0x1UL << GPIO_DIRSET_PIN4_Pos)
 
#define GPIO_DIRSET_PIN4_Input   (0UL)
 
#define GPIO_DIRSET_PIN4_Output   (1UL)
 
#define GPIO_DIRSET_PIN4_Set   (1UL)
 
#define GPIO_DIRSET_PIN3_Pos   (3UL)
 
#define GPIO_DIRSET_PIN3_Msk   (0x1UL << GPIO_DIRSET_PIN3_Pos)
 
#define GPIO_DIRSET_PIN3_Input   (0UL)
 
#define GPIO_DIRSET_PIN3_Output   (1UL)
 
#define GPIO_DIRSET_PIN3_Set   (1UL)
 
#define GPIO_DIRSET_PIN2_Pos   (2UL)
 
#define GPIO_DIRSET_PIN2_Msk   (0x1UL << GPIO_DIRSET_PIN2_Pos)
 
#define GPIO_DIRSET_PIN2_Input   (0UL)
 
#define GPIO_DIRSET_PIN2_Output   (1UL)
 
#define GPIO_DIRSET_PIN2_Set   (1UL)
 
#define GPIO_DIRSET_PIN1_Pos   (1UL)
 
#define GPIO_DIRSET_PIN1_Msk   (0x1UL << GPIO_DIRSET_PIN1_Pos)
 
#define GPIO_DIRSET_PIN1_Input   (0UL)
 
#define GPIO_DIRSET_PIN1_Output   (1UL)
 
#define GPIO_DIRSET_PIN1_Set   (1UL)
 
#define GPIO_DIRSET_PIN0_Pos   (0UL)
 
#define GPIO_DIRSET_PIN0_Msk   (0x1UL << GPIO_DIRSET_PIN0_Pos)
 
#define GPIO_DIRSET_PIN0_Input   (0UL)
 
#define GPIO_DIRSET_PIN0_Output   (1UL)
 
#define GPIO_DIRSET_PIN0_Set   (1UL)
 
#define GPIO_DIRCLR_PIN31_Pos   (31UL)
 
#define GPIO_DIRCLR_PIN31_Msk   (0x1UL << GPIO_DIRCLR_PIN31_Pos)
 
#define GPIO_DIRCLR_PIN31_Input   (0UL)
 
#define GPIO_DIRCLR_PIN31_Output   (1UL)
 
#define GPIO_DIRCLR_PIN31_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN30_Pos   (30UL)
 
#define GPIO_DIRCLR_PIN30_Msk   (0x1UL << GPIO_DIRCLR_PIN30_Pos)
 
#define GPIO_DIRCLR_PIN30_Input   (0UL)
 
#define GPIO_DIRCLR_PIN30_Output   (1UL)
 
#define GPIO_DIRCLR_PIN30_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN29_Pos   (29UL)
 
#define GPIO_DIRCLR_PIN29_Msk   (0x1UL << GPIO_DIRCLR_PIN29_Pos)
 
#define GPIO_DIRCLR_PIN29_Input   (0UL)
 
#define GPIO_DIRCLR_PIN29_Output   (1UL)
 
#define GPIO_DIRCLR_PIN29_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN28_Pos   (28UL)
 
#define GPIO_DIRCLR_PIN28_Msk   (0x1UL << GPIO_DIRCLR_PIN28_Pos)
 
#define GPIO_DIRCLR_PIN28_Input   (0UL)
 
#define GPIO_DIRCLR_PIN28_Output   (1UL)
 
#define GPIO_DIRCLR_PIN28_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN27_Pos   (27UL)
 
#define GPIO_DIRCLR_PIN27_Msk   (0x1UL << GPIO_DIRCLR_PIN27_Pos)
 
#define GPIO_DIRCLR_PIN27_Input   (0UL)
 
#define GPIO_DIRCLR_PIN27_Output   (1UL)
 
#define GPIO_DIRCLR_PIN27_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN26_Pos   (26UL)
 
#define GPIO_DIRCLR_PIN26_Msk   (0x1UL << GPIO_DIRCLR_PIN26_Pos)
 
#define GPIO_DIRCLR_PIN26_Input   (0UL)
 
#define GPIO_DIRCLR_PIN26_Output   (1UL)
 
#define GPIO_DIRCLR_PIN26_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN25_Pos   (25UL)
 
#define GPIO_DIRCLR_PIN25_Msk   (0x1UL << GPIO_DIRCLR_PIN25_Pos)
 
#define GPIO_DIRCLR_PIN25_Input   (0UL)
 
#define GPIO_DIRCLR_PIN25_Output   (1UL)
 
#define GPIO_DIRCLR_PIN25_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN24_Pos   (24UL)
 
#define GPIO_DIRCLR_PIN24_Msk   (0x1UL << GPIO_DIRCLR_PIN24_Pos)
 
#define GPIO_DIRCLR_PIN24_Input   (0UL)
 
#define GPIO_DIRCLR_PIN24_Output   (1UL)
 
#define GPIO_DIRCLR_PIN24_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN23_Pos   (23UL)
 
#define GPIO_DIRCLR_PIN23_Msk   (0x1UL << GPIO_DIRCLR_PIN23_Pos)
 
#define GPIO_DIRCLR_PIN23_Input   (0UL)
 
#define GPIO_DIRCLR_PIN23_Output   (1UL)
 
#define GPIO_DIRCLR_PIN23_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN22_Pos   (22UL)
 
#define GPIO_DIRCLR_PIN22_Msk   (0x1UL << GPIO_DIRCLR_PIN22_Pos)
 
#define GPIO_DIRCLR_PIN22_Input   (0UL)
 
#define GPIO_DIRCLR_PIN22_Output   (1UL)
 
#define GPIO_DIRCLR_PIN22_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN21_Pos   (21UL)
 
#define GPIO_DIRCLR_PIN21_Msk   (0x1UL << GPIO_DIRCLR_PIN21_Pos)
 
#define GPIO_DIRCLR_PIN21_Input   (0UL)
 
#define GPIO_DIRCLR_PIN21_Output   (1UL)
 
#define GPIO_DIRCLR_PIN21_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN20_Pos   (20UL)
 
#define GPIO_DIRCLR_PIN20_Msk   (0x1UL << GPIO_DIRCLR_PIN20_Pos)
 
#define GPIO_DIRCLR_PIN20_Input   (0UL)
 
#define GPIO_DIRCLR_PIN20_Output   (1UL)
 
#define GPIO_DIRCLR_PIN20_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN19_Pos   (19UL)
 
#define GPIO_DIRCLR_PIN19_Msk   (0x1UL << GPIO_DIRCLR_PIN19_Pos)
 
#define GPIO_DIRCLR_PIN19_Input   (0UL)
 
#define GPIO_DIRCLR_PIN19_Output   (1UL)
 
#define GPIO_DIRCLR_PIN19_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN18_Pos   (18UL)
 
#define GPIO_DIRCLR_PIN18_Msk   (0x1UL << GPIO_DIRCLR_PIN18_Pos)
 
#define GPIO_DIRCLR_PIN18_Input   (0UL)
 
#define GPIO_DIRCLR_PIN18_Output   (1UL)
 
#define GPIO_DIRCLR_PIN18_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN17_Pos   (17UL)
 
#define GPIO_DIRCLR_PIN17_Msk   (0x1UL << GPIO_DIRCLR_PIN17_Pos)
 
#define GPIO_DIRCLR_PIN17_Input   (0UL)
 
#define GPIO_DIRCLR_PIN17_Output   (1UL)
 
#define GPIO_DIRCLR_PIN17_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN16_Pos   (16UL)
 
#define GPIO_DIRCLR_PIN16_Msk   (0x1UL << GPIO_DIRCLR_PIN16_Pos)
 
#define GPIO_DIRCLR_PIN16_Input   (0UL)
 
#define GPIO_DIRCLR_PIN16_Output   (1UL)
 
#define GPIO_DIRCLR_PIN16_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN15_Pos   (15UL)
 
#define GPIO_DIRCLR_PIN15_Msk   (0x1UL << GPIO_DIRCLR_PIN15_Pos)
 
#define GPIO_DIRCLR_PIN15_Input   (0UL)
 
#define GPIO_DIRCLR_PIN15_Output   (1UL)
 
#define GPIO_DIRCLR_PIN15_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN14_Pos   (14UL)
 
#define GPIO_DIRCLR_PIN14_Msk   (0x1UL << GPIO_DIRCLR_PIN14_Pos)
 
#define GPIO_DIRCLR_PIN14_Input   (0UL)
 
#define GPIO_DIRCLR_PIN14_Output   (1UL)
 
#define GPIO_DIRCLR_PIN14_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN13_Pos   (13UL)
 
#define GPIO_DIRCLR_PIN13_Msk   (0x1UL << GPIO_DIRCLR_PIN13_Pos)
 
#define GPIO_DIRCLR_PIN13_Input   (0UL)
 
#define GPIO_DIRCLR_PIN13_Output   (1UL)
 
#define GPIO_DIRCLR_PIN13_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN12_Pos   (12UL)
 
#define GPIO_DIRCLR_PIN12_Msk   (0x1UL << GPIO_DIRCLR_PIN12_Pos)
 
#define GPIO_DIRCLR_PIN12_Input   (0UL)
 
#define GPIO_DIRCLR_PIN12_Output   (1UL)
 
#define GPIO_DIRCLR_PIN12_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN11_Pos   (11UL)
 
#define GPIO_DIRCLR_PIN11_Msk   (0x1UL << GPIO_DIRCLR_PIN11_Pos)
 
#define GPIO_DIRCLR_PIN11_Input   (0UL)
 
#define GPIO_DIRCLR_PIN11_Output   (1UL)
 
#define GPIO_DIRCLR_PIN11_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN10_Pos   (10UL)
 
#define GPIO_DIRCLR_PIN10_Msk   (0x1UL << GPIO_DIRCLR_PIN10_Pos)
 
#define GPIO_DIRCLR_PIN10_Input   (0UL)
 
#define GPIO_DIRCLR_PIN10_Output   (1UL)
 
#define GPIO_DIRCLR_PIN10_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN9_Pos   (9UL)
 
#define GPIO_DIRCLR_PIN9_Msk   (0x1UL << GPIO_DIRCLR_PIN9_Pos)
 
#define GPIO_DIRCLR_PIN9_Input   (0UL)
 
#define GPIO_DIRCLR_PIN9_Output   (1UL)
 
#define GPIO_DIRCLR_PIN9_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN8_Pos   (8UL)
 
#define GPIO_DIRCLR_PIN8_Msk   (0x1UL << GPIO_DIRCLR_PIN8_Pos)
 
#define GPIO_DIRCLR_PIN8_Input   (0UL)
 
#define GPIO_DIRCLR_PIN8_Output   (1UL)
 
#define GPIO_DIRCLR_PIN8_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN7_Pos   (7UL)
 
#define GPIO_DIRCLR_PIN7_Msk   (0x1UL << GPIO_DIRCLR_PIN7_Pos)
 
#define GPIO_DIRCLR_PIN7_Input   (0UL)
 
#define GPIO_DIRCLR_PIN7_Output   (1UL)
 
#define GPIO_DIRCLR_PIN7_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN6_Pos   (6UL)
 
#define GPIO_DIRCLR_PIN6_Msk   (0x1UL << GPIO_DIRCLR_PIN6_Pos)
 
#define GPIO_DIRCLR_PIN6_Input   (0UL)
 
#define GPIO_DIRCLR_PIN6_Output   (1UL)
 
#define GPIO_DIRCLR_PIN6_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN5_Pos   (5UL)
 
#define GPIO_DIRCLR_PIN5_Msk   (0x1UL << GPIO_DIRCLR_PIN5_Pos)
 
#define GPIO_DIRCLR_PIN5_Input   (0UL)
 
#define GPIO_DIRCLR_PIN5_Output   (1UL)
 
#define GPIO_DIRCLR_PIN5_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN4_Pos   (4UL)
 
#define GPIO_DIRCLR_PIN4_Msk   (0x1UL << GPIO_DIRCLR_PIN4_Pos)
 
#define GPIO_DIRCLR_PIN4_Input   (0UL)
 
#define GPIO_DIRCLR_PIN4_Output   (1UL)
 
#define GPIO_DIRCLR_PIN4_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN3_Pos   (3UL)
 
#define GPIO_DIRCLR_PIN3_Msk   (0x1UL << GPIO_DIRCLR_PIN3_Pos)
 
#define GPIO_DIRCLR_PIN3_Input   (0UL)
 
#define GPIO_DIRCLR_PIN3_Output   (1UL)
 
#define GPIO_DIRCLR_PIN3_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN2_Pos   (2UL)
 
#define GPIO_DIRCLR_PIN2_Msk   (0x1UL << GPIO_DIRCLR_PIN2_Pos)
 
#define GPIO_DIRCLR_PIN2_Input   (0UL)
 
#define GPIO_DIRCLR_PIN2_Output   (1UL)
 
#define GPIO_DIRCLR_PIN2_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN1_Pos   (1UL)
 
#define GPIO_DIRCLR_PIN1_Msk   (0x1UL << GPIO_DIRCLR_PIN1_Pos)
 
#define GPIO_DIRCLR_PIN1_Input   (0UL)
 
#define GPIO_DIRCLR_PIN1_Output   (1UL)
 
#define GPIO_DIRCLR_PIN1_Clear   (1UL)
 
#define GPIO_DIRCLR_PIN0_Pos   (0UL)
 
#define GPIO_DIRCLR_PIN0_Msk   (0x1UL << GPIO_DIRCLR_PIN0_Pos)
 
#define GPIO_DIRCLR_PIN0_Input   (0UL)
 
#define GPIO_DIRCLR_PIN0_Output   (1UL)
 
#define GPIO_DIRCLR_PIN0_Clear   (1UL)
 
#define GPIO_LATCH_PIN31_Pos   (31UL)
 
#define GPIO_LATCH_PIN31_Msk   (0x1UL << GPIO_LATCH_PIN31_Pos)
 
#define GPIO_LATCH_PIN31_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN31_Latched   (1UL)
 
#define GPIO_LATCH_PIN30_Pos   (30UL)
 
#define GPIO_LATCH_PIN30_Msk   (0x1UL << GPIO_LATCH_PIN30_Pos)
 
#define GPIO_LATCH_PIN30_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN30_Latched   (1UL)
 
#define GPIO_LATCH_PIN29_Pos   (29UL)
 
#define GPIO_LATCH_PIN29_Msk   (0x1UL << GPIO_LATCH_PIN29_Pos)
 
#define GPIO_LATCH_PIN29_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN29_Latched   (1UL)
 
#define GPIO_LATCH_PIN28_Pos   (28UL)
 
#define GPIO_LATCH_PIN28_Msk   (0x1UL << GPIO_LATCH_PIN28_Pos)
 
#define GPIO_LATCH_PIN28_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN28_Latched   (1UL)
 
#define GPIO_LATCH_PIN27_Pos   (27UL)
 
#define GPIO_LATCH_PIN27_Msk   (0x1UL << GPIO_LATCH_PIN27_Pos)
 
#define GPIO_LATCH_PIN27_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN27_Latched   (1UL)
 
#define GPIO_LATCH_PIN26_Pos   (26UL)
 
#define GPIO_LATCH_PIN26_Msk   (0x1UL << GPIO_LATCH_PIN26_Pos)
 
#define GPIO_LATCH_PIN26_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN26_Latched   (1UL)
 
#define GPIO_LATCH_PIN25_Pos   (25UL)
 
#define GPIO_LATCH_PIN25_Msk   (0x1UL << GPIO_LATCH_PIN25_Pos)
 
#define GPIO_LATCH_PIN25_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN25_Latched   (1UL)
 
#define GPIO_LATCH_PIN24_Pos   (24UL)
 
#define GPIO_LATCH_PIN24_Msk   (0x1UL << GPIO_LATCH_PIN24_Pos)
 
#define GPIO_LATCH_PIN24_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN24_Latched   (1UL)
 
#define GPIO_LATCH_PIN23_Pos   (23UL)
 
#define GPIO_LATCH_PIN23_Msk   (0x1UL << GPIO_LATCH_PIN23_Pos)
 
#define GPIO_LATCH_PIN23_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN23_Latched   (1UL)
 
#define GPIO_LATCH_PIN22_Pos   (22UL)
 
#define GPIO_LATCH_PIN22_Msk   (0x1UL << GPIO_LATCH_PIN22_Pos)
 
#define GPIO_LATCH_PIN22_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN22_Latched   (1UL)
 
#define GPIO_LATCH_PIN21_Pos   (21UL)
 
#define GPIO_LATCH_PIN21_Msk   (0x1UL << GPIO_LATCH_PIN21_Pos)
 
#define GPIO_LATCH_PIN21_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN21_Latched   (1UL)
 
#define GPIO_LATCH_PIN20_Pos   (20UL)
 
#define GPIO_LATCH_PIN20_Msk   (0x1UL << GPIO_LATCH_PIN20_Pos)
 
#define GPIO_LATCH_PIN20_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN20_Latched   (1UL)
 
#define GPIO_LATCH_PIN19_Pos   (19UL)
 
#define GPIO_LATCH_PIN19_Msk   (0x1UL << GPIO_LATCH_PIN19_Pos)
 
#define GPIO_LATCH_PIN19_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN19_Latched   (1UL)
 
#define GPIO_LATCH_PIN18_Pos   (18UL)
 
#define GPIO_LATCH_PIN18_Msk   (0x1UL << GPIO_LATCH_PIN18_Pos)
 
#define GPIO_LATCH_PIN18_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN18_Latched   (1UL)
 
#define GPIO_LATCH_PIN17_Pos   (17UL)
 
#define GPIO_LATCH_PIN17_Msk   (0x1UL << GPIO_LATCH_PIN17_Pos)
 
#define GPIO_LATCH_PIN17_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN17_Latched   (1UL)
 
#define GPIO_LATCH_PIN16_Pos   (16UL)
 
#define GPIO_LATCH_PIN16_Msk   (0x1UL << GPIO_LATCH_PIN16_Pos)
 
#define GPIO_LATCH_PIN16_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN16_Latched   (1UL)
 
#define GPIO_LATCH_PIN15_Pos   (15UL)
 
#define GPIO_LATCH_PIN15_Msk   (0x1UL << GPIO_LATCH_PIN15_Pos)
 
#define GPIO_LATCH_PIN15_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN15_Latched   (1UL)
 
#define GPIO_LATCH_PIN14_Pos   (14UL)
 
#define GPIO_LATCH_PIN14_Msk   (0x1UL << GPIO_LATCH_PIN14_Pos)
 
#define GPIO_LATCH_PIN14_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN14_Latched   (1UL)
 
#define GPIO_LATCH_PIN13_Pos   (13UL)
 
#define GPIO_LATCH_PIN13_Msk   (0x1UL << GPIO_LATCH_PIN13_Pos)
 
#define GPIO_LATCH_PIN13_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN13_Latched   (1UL)
 
#define GPIO_LATCH_PIN12_Pos   (12UL)
 
#define GPIO_LATCH_PIN12_Msk   (0x1UL << GPIO_LATCH_PIN12_Pos)
 
#define GPIO_LATCH_PIN12_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN12_Latched   (1UL)
 
#define GPIO_LATCH_PIN11_Pos   (11UL)
 
#define GPIO_LATCH_PIN11_Msk   (0x1UL << GPIO_LATCH_PIN11_Pos)
 
#define GPIO_LATCH_PIN11_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN11_Latched   (1UL)
 
#define GPIO_LATCH_PIN10_Pos   (10UL)
 
#define GPIO_LATCH_PIN10_Msk   (0x1UL << GPIO_LATCH_PIN10_Pos)
 
#define GPIO_LATCH_PIN10_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN10_Latched   (1UL)
 
#define GPIO_LATCH_PIN9_Pos   (9UL)
 
#define GPIO_LATCH_PIN9_Msk   (0x1UL << GPIO_LATCH_PIN9_Pos)
 
#define GPIO_LATCH_PIN9_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN9_Latched   (1UL)
 
#define GPIO_LATCH_PIN8_Pos   (8UL)
 
#define GPIO_LATCH_PIN8_Msk   (0x1UL << GPIO_LATCH_PIN8_Pos)
 
#define GPIO_LATCH_PIN8_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN8_Latched   (1UL)
 
#define GPIO_LATCH_PIN7_Pos   (7UL)
 
#define GPIO_LATCH_PIN7_Msk   (0x1UL << GPIO_LATCH_PIN7_Pos)
 
#define GPIO_LATCH_PIN7_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN7_Latched   (1UL)
 
#define GPIO_LATCH_PIN6_Pos   (6UL)
 
#define GPIO_LATCH_PIN6_Msk   (0x1UL << GPIO_LATCH_PIN6_Pos)
 
#define GPIO_LATCH_PIN6_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN6_Latched   (1UL)
 
#define GPIO_LATCH_PIN5_Pos   (5UL)
 
#define GPIO_LATCH_PIN5_Msk   (0x1UL << GPIO_LATCH_PIN5_Pos)
 
#define GPIO_LATCH_PIN5_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN5_Latched   (1UL)
 
#define GPIO_LATCH_PIN4_Pos   (4UL)
 
#define GPIO_LATCH_PIN4_Msk   (0x1UL << GPIO_LATCH_PIN4_Pos)
 
#define GPIO_LATCH_PIN4_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN4_Latched   (1UL)
 
#define GPIO_LATCH_PIN3_Pos   (3UL)
 
#define GPIO_LATCH_PIN3_Msk   (0x1UL << GPIO_LATCH_PIN3_Pos)
 
#define GPIO_LATCH_PIN3_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN3_Latched   (1UL)
 
#define GPIO_LATCH_PIN2_Pos   (2UL)
 
#define GPIO_LATCH_PIN2_Msk   (0x1UL << GPIO_LATCH_PIN2_Pos)
 
#define GPIO_LATCH_PIN2_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN2_Latched   (1UL)
 
#define GPIO_LATCH_PIN1_Pos   (1UL)
 
#define GPIO_LATCH_PIN1_Msk   (0x1UL << GPIO_LATCH_PIN1_Pos)
 
#define GPIO_LATCH_PIN1_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN1_Latched   (1UL)
 
#define GPIO_LATCH_PIN0_Pos   (0UL)
 
#define GPIO_LATCH_PIN0_Msk   (0x1UL << GPIO_LATCH_PIN0_Pos)
 
#define GPIO_LATCH_PIN0_NotLatched   (0UL)
 
#define GPIO_LATCH_PIN0_Latched   (1UL)
 
#define GPIO_DETECTMODE_DETECTMODE_Pos   (0UL)
 
#define GPIO_DETECTMODE_DETECTMODE_Msk   (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos)
 
#define GPIO_DETECTMODE_DETECTMODE_Default   (0UL)
 
#define GPIO_DETECTMODE_DETECTMODE_LDETECT   (1UL)
 
#define GPIO_PIN_CNF_SENSE_Pos   (16UL)
 
#define GPIO_PIN_CNF_SENSE_Msk   (0x3UL << GPIO_PIN_CNF_SENSE_Pos)
 
#define GPIO_PIN_CNF_SENSE_Disabled   (0UL)
 
#define GPIO_PIN_CNF_SENSE_High   (2UL)
 
#define GPIO_PIN_CNF_SENSE_Low   (3UL)
 
#define GPIO_PIN_CNF_DRIVE_Pos   (8UL)
 
#define GPIO_PIN_CNF_DRIVE_Msk   (0x7UL << GPIO_PIN_CNF_DRIVE_Pos)
 
#define GPIO_PIN_CNF_DRIVE_S0S1   (0UL)
 
#define GPIO_PIN_CNF_DRIVE_H0S1   (1UL)
 
#define GPIO_PIN_CNF_DRIVE_S0H1   (2UL)
 
#define GPIO_PIN_CNF_DRIVE_H0H1   (3UL)
 
#define GPIO_PIN_CNF_DRIVE_D0S1   (4UL)
 
#define GPIO_PIN_CNF_DRIVE_D0H1   (5UL)
 
#define GPIO_PIN_CNF_DRIVE_S0D1   (6UL)
 
#define GPIO_PIN_CNF_DRIVE_H0D1   (7UL)
 
#define GPIO_PIN_CNF_PULL_Pos   (2UL)
 
#define GPIO_PIN_CNF_PULL_Msk   (0x3UL << GPIO_PIN_CNF_PULL_Pos)
 
#define GPIO_PIN_CNF_PULL_Disabled   (0UL)
 
#define GPIO_PIN_CNF_PULL_Pulldown   (1UL)
 
#define GPIO_PIN_CNF_PULL_Pullup   (3UL)
 
#define GPIO_PIN_CNF_INPUT_Pos   (1UL)
 
#define GPIO_PIN_CNF_INPUT_Msk   (0x1UL << GPIO_PIN_CNF_INPUT_Pos)
 
#define GPIO_PIN_CNF_INPUT_Connect   (0UL)
 
#define GPIO_PIN_CNF_INPUT_Disconnect   (1UL)
 
#define GPIO_PIN_CNF_DIR_Pos   (0UL)
 
#define GPIO_PIN_CNF_DIR_Msk   (0x1UL << GPIO_PIN_CNF_DIR_Pos)
 
#define GPIO_PIN_CNF_DIR_Input   (0UL)
 
#define GPIO_PIN_CNF_DIR_Output   (1UL)
 
#define PDM_INTEN_END_Pos   (2UL)
 
#define PDM_INTEN_END_Msk   (0x1UL << PDM_INTEN_END_Pos)
 
#define PDM_INTEN_END_Disabled   (0UL)
 
#define PDM_INTEN_END_Enabled   (1UL)
 
#define PDM_INTEN_STOPPED_Pos   (1UL)
 
#define PDM_INTEN_STOPPED_Msk   (0x1UL << PDM_INTEN_STOPPED_Pos)
 
#define PDM_INTEN_STOPPED_Disabled   (0UL)
 
#define PDM_INTEN_STOPPED_Enabled   (1UL)
 
#define PDM_INTEN_STARTED_Pos   (0UL)
 
#define PDM_INTEN_STARTED_Msk   (0x1UL << PDM_INTEN_STARTED_Pos)
 
#define PDM_INTEN_STARTED_Disabled   (0UL)
 
#define PDM_INTEN_STARTED_Enabled   (1UL)
 
#define PDM_INTENSET_END_Pos   (2UL)
 
#define PDM_INTENSET_END_Msk   (0x1UL << PDM_INTENSET_END_Pos)
 
#define PDM_INTENSET_END_Disabled   (0UL)
 
#define PDM_INTENSET_END_Enabled   (1UL)
 
#define PDM_INTENSET_END_Set   (1UL)
 
#define PDM_INTENSET_STOPPED_Pos   (1UL)
 
#define PDM_INTENSET_STOPPED_Msk   (0x1UL << PDM_INTENSET_STOPPED_Pos)
 
#define PDM_INTENSET_STOPPED_Disabled   (0UL)
 
#define PDM_INTENSET_STOPPED_Enabled   (1UL)
 
#define PDM_INTENSET_STOPPED_Set   (1UL)
 
#define PDM_INTENSET_STARTED_Pos   (0UL)
 
#define PDM_INTENSET_STARTED_Msk   (0x1UL << PDM_INTENSET_STARTED_Pos)
 
#define PDM_INTENSET_STARTED_Disabled   (0UL)
 
#define PDM_INTENSET_STARTED_Enabled   (1UL)
 
#define PDM_INTENSET_STARTED_Set   (1UL)
 
#define PDM_INTENCLR_END_Pos   (2UL)
 
#define PDM_INTENCLR_END_Msk   (0x1UL << PDM_INTENCLR_END_Pos)
 
#define PDM_INTENCLR_END_Disabled   (0UL)
 
#define PDM_INTENCLR_END_Enabled   (1UL)
 
#define PDM_INTENCLR_END_Clear   (1UL)
 
#define PDM_INTENCLR_STOPPED_Pos   (1UL)
 
#define PDM_INTENCLR_STOPPED_Msk   (0x1UL << PDM_INTENCLR_STOPPED_Pos)
 
#define PDM_INTENCLR_STOPPED_Disabled   (0UL)
 
#define PDM_INTENCLR_STOPPED_Enabled   (1UL)
 
#define PDM_INTENCLR_STOPPED_Clear   (1UL)
 
#define PDM_INTENCLR_STARTED_Pos   (0UL)
 
#define PDM_INTENCLR_STARTED_Msk   (0x1UL << PDM_INTENCLR_STARTED_Pos)
 
#define PDM_INTENCLR_STARTED_Disabled   (0UL)
 
#define PDM_INTENCLR_STARTED_Enabled   (1UL)
 
#define PDM_INTENCLR_STARTED_Clear   (1UL)
 
#define PDM_ENABLE_ENABLE_Pos   (0UL)
 
#define PDM_ENABLE_ENABLE_Msk   (0x1UL << PDM_ENABLE_ENABLE_Pos)
 
#define PDM_ENABLE_ENABLE_Disabled   (0UL)
 
#define PDM_ENABLE_ENABLE_Enabled   (1UL)
 
#define PDM_PDMCLKCTRL_FREQ_Pos   (0UL)
 
#define PDM_PDMCLKCTRL_FREQ_Msk   (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos)
 
#define PDM_PDMCLKCTRL_FREQ_1000K   (0x08000000UL)
 
#define PDM_PDMCLKCTRL_FREQ_Default   (0x08400000UL)
 
#define PDM_PDMCLKCTRL_FREQ_1067K   (0x08800000UL)
 
#define PDM_MODE_EDGE_Pos   (1UL)
 
#define PDM_MODE_EDGE_Msk   (0x1UL << PDM_MODE_EDGE_Pos)
 
#define PDM_MODE_EDGE_LeftFalling   (0UL)
 
#define PDM_MODE_EDGE_LeftRising   (1UL)
 
#define PDM_MODE_OPERATION_Pos   (0UL)
 
#define PDM_MODE_OPERATION_Msk   (0x1UL << PDM_MODE_OPERATION_Pos)
 
#define PDM_MODE_OPERATION_Stereo   (0UL)
 
#define PDM_MODE_OPERATION_Mono   (1UL)
 
#define PDM_GAINL_GAINL_Pos   (0UL)
 
#define PDM_GAINL_GAINL_Msk   (0x7FUL << PDM_GAINL_GAINL_Pos)
 
#define PDM_GAINL_GAINL_MinGain   (0x00UL)
 
#define PDM_GAINL_GAINL_DefaultGain   (0x28UL)
 
#define PDM_GAINL_GAINL_MaxGain   (0x50UL)
 
#define PDM_GAINR_GAINR_Pos   (0UL)
 
#define PDM_GAINR_GAINR_Msk   (0xFFUL << PDM_GAINR_GAINR_Pos)
 
#define PDM_GAINR_GAINR_MinGain   (0x00UL)
 
#define PDM_GAINR_GAINR_DefaultGain   (0x28UL)
 
#define PDM_GAINR_GAINR_MaxGain   (0x50UL)
 
#define PDM_PSEL_CLK_CONNECT_Pos   (31UL)
 
#define PDM_PSEL_CLK_CONNECT_Msk   (0x1UL << PDM_PSEL_CLK_CONNECT_Pos)
 
#define PDM_PSEL_CLK_CONNECT_Connected   (0UL)
 
#define PDM_PSEL_CLK_CONNECT_Disconnected   (1UL)
 
#define PDM_PSEL_CLK_PIN_Pos   (0UL)
 
#define PDM_PSEL_CLK_PIN_Msk   (0x1FUL << PDM_PSEL_CLK_PIN_Pos)
 
#define PDM_PSEL_DIN_CONNECT_Pos   (31UL)
 
#define PDM_PSEL_DIN_CONNECT_Msk   (0x1UL << PDM_PSEL_DIN_CONNECT_Pos)
 
#define PDM_PSEL_DIN_CONNECT_Connected   (0UL)
 
#define PDM_PSEL_DIN_CONNECT_Disconnected   (1UL)
 
#define PDM_PSEL_DIN_PIN_Pos   (0UL)
 
#define PDM_PSEL_DIN_PIN_Msk   (0x1FUL << PDM_PSEL_DIN_PIN_Pos)
 
#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos   (0UL)
 
#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk   (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos)
 
#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos   (0UL)
 
#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk   (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos)
 
#define POWER_INTENSET_SLEEPEXIT_Pos   (6UL)
 
#define POWER_INTENSET_SLEEPEXIT_Msk   (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos)
 
#define POWER_INTENSET_SLEEPEXIT_Disabled   (0UL)
 
#define POWER_INTENSET_SLEEPEXIT_Enabled   (1UL)
 
#define POWER_INTENSET_SLEEPEXIT_Set   (1UL)
 
#define POWER_INTENSET_SLEEPENTER_Pos   (5UL)
 
#define POWER_INTENSET_SLEEPENTER_Msk   (0x1UL << POWER_INTENSET_SLEEPENTER_Pos)
 
#define POWER_INTENSET_SLEEPENTER_Disabled   (0UL)
 
#define POWER_INTENSET_SLEEPENTER_Enabled   (1UL)
 
#define POWER_INTENSET_SLEEPENTER_Set   (1UL)
 
#define POWER_INTENSET_POFWARN_Pos   (2UL)
 
#define POWER_INTENSET_POFWARN_Msk   (0x1UL << POWER_INTENSET_POFWARN_Pos)
 
#define POWER_INTENSET_POFWARN_Disabled   (0UL)
 
#define POWER_INTENSET_POFWARN_Enabled   (1UL)
 
#define POWER_INTENSET_POFWARN_Set   (1UL)
 
#define POWER_INTENCLR_SLEEPEXIT_Pos   (6UL)
 
#define POWER_INTENCLR_SLEEPEXIT_Msk   (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos)
 
#define POWER_INTENCLR_SLEEPEXIT_Disabled   (0UL)
 
#define POWER_INTENCLR_SLEEPEXIT_Enabled   (1UL)
 
#define POWER_INTENCLR_SLEEPEXIT_Clear   (1UL)
 
#define POWER_INTENCLR_SLEEPENTER_Pos   (5UL)
 
#define POWER_INTENCLR_SLEEPENTER_Msk   (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos)
 
#define POWER_INTENCLR_SLEEPENTER_Disabled   (0UL)
 
#define POWER_INTENCLR_SLEEPENTER_Enabled   (1UL)
 
#define POWER_INTENCLR_SLEEPENTER_Clear   (1UL)
 
#define POWER_INTENCLR_POFWARN_Pos   (2UL)
 
#define POWER_INTENCLR_POFWARN_Msk   (0x1UL << POWER_INTENCLR_POFWARN_Pos)
 
#define POWER_INTENCLR_POFWARN_Disabled   (0UL)
 
#define POWER_INTENCLR_POFWARN_Enabled   (1UL)
 
#define POWER_INTENCLR_POFWARN_Clear   (1UL)
 
#define POWER_RESETREAS_NFC_Pos   (19UL)
 
#define POWER_RESETREAS_NFC_Msk   (0x1UL << POWER_RESETREAS_NFC_Pos)
 
#define POWER_RESETREAS_NFC_NotDetected   (0UL)
 
#define POWER_RESETREAS_NFC_Detected   (1UL)
 
#define POWER_RESETREAS_DIF_Pos   (18UL)
 
#define POWER_RESETREAS_DIF_Msk   (0x1UL << POWER_RESETREAS_DIF_Pos)
 
#define POWER_RESETREAS_DIF_NotDetected   (0UL)
 
#define POWER_RESETREAS_DIF_Detected   (1UL)
 
#define POWER_RESETREAS_LPCOMP_Pos   (17UL)
 
#define POWER_RESETREAS_LPCOMP_Msk   (0x1UL << POWER_RESETREAS_LPCOMP_Pos)
 
#define POWER_RESETREAS_LPCOMP_NotDetected   (0UL)
 
#define POWER_RESETREAS_LPCOMP_Detected   (1UL)
 
#define POWER_RESETREAS_OFF_Pos   (16UL)
 
#define POWER_RESETREAS_OFF_Msk   (0x1UL << POWER_RESETREAS_OFF_Pos)
 
#define POWER_RESETREAS_OFF_NotDetected   (0UL)
 
#define POWER_RESETREAS_OFF_Detected   (1UL)
 
#define POWER_RESETREAS_LOCKUP_Pos   (3UL)
 
#define POWER_RESETREAS_LOCKUP_Msk   (0x1UL << POWER_RESETREAS_LOCKUP_Pos)
 
#define POWER_RESETREAS_LOCKUP_NotDetected   (0UL)
 
#define POWER_RESETREAS_LOCKUP_Detected   (1UL)
 
#define POWER_RESETREAS_SREQ_Pos   (2UL)
 
#define POWER_RESETREAS_SREQ_Msk   (0x1UL << POWER_RESETREAS_SREQ_Pos)
 
#define POWER_RESETREAS_SREQ_NotDetected   (0UL)
 
#define POWER_RESETREAS_SREQ_Detected   (1UL)
 
#define POWER_RESETREAS_DOG_Pos   (1UL)
 
#define POWER_RESETREAS_DOG_Msk   (0x1UL << POWER_RESETREAS_DOG_Pos)
 
#define POWER_RESETREAS_DOG_NotDetected   (0UL)
 
#define POWER_RESETREAS_DOG_Detected   (1UL)
 
#define POWER_RESETREAS_RESETPIN_Pos   (0UL)
 
#define POWER_RESETREAS_RESETPIN_Msk   (0x1UL << POWER_RESETREAS_RESETPIN_Pos)
 
#define POWER_RESETREAS_RESETPIN_NotDetected   (0UL)
 
#define POWER_RESETREAS_RESETPIN_Detected   (1UL)
 
#define POWER_RAMSTATUS_RAMBLOCK3_Pos   (3UL)
 
#define POWER_RAMSTATUS_RAMBLOCK3_Msk   (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos)
 
#define POWER_RAMSTATUS_RAMBLOCK3_Off   (0UL)
 
#define POWER_RAMSTATUS_RAMBLOCK3_On   (1UL)
 
#define POWER_RAMSTATUS_RAMBLOCK2_Pos   (2UL)
 
#define POWER_RAMSTATUS_RAMBLOCK2_Msk   (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos)
 
#define POWER_RAMSTATUS_RAMBLOCK2_Off   (0UL)
 
#define POWER_RAMSTATUS_RAMBLOCK2_On   (1UL)
 
#define POWER_RAMSTATUS_RAMBLOCK1_Pos   (1UL)
 
#define POWER_RAMSTATUS_RAMBLOCK1_Msk   (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos)
 
#define POWER_RAMSTATUS_RAMBLOCK1_Off   (0UL)
 
#define POWER_RAMSTATUS_RAMBLOCK1_On   (1UL)
 
#define POWER_RAMSTATUS_RAMBLOCK0_Pos   (0UL)
 
#define POWER_RAMSTATUS_RAMBLOCK0_Msk   (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos)
 
#define POWER_RAMSTATUS_RAMBLOCK0_Off   (0UL)
 
#define POWER_RAMSTATUS_RAMBLOCK0_On   (1UL)
 
#define POWER_SYSTEMOFF_SYSTEMOFF_Pos   (0UL)
 
#define POWER_SYSTEMOFF_SYSTEMOFF_Msk   (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos)
 
#define POWER_SYSTEMOFF_SYSTEMOFF_Enter   (1UL)
 
#define POWER_POFCON_THRESHOLD_Pos   (1UL)
 
#define POWER_POFCON_THRESHOLD_Msk   (0xFUL << POWER_POFCON_THRESHOLD_Pos)
 
#define POWER_POFCON_THRESHOLD_V17   (4UL)
 
#define POWER_POFCON_THRESHOLD_V18   (5UL)
 
#define POWER_POFCON_THRESHOLD_V19   (6UL)
 
#define POWER_POFCON_THRESHOLD_V20   (7UL)
 
#define POWER_POFCON_THRESHOLD_V21   (8UL)
 
#define POWER_POFCON_THRESHOLD_V22   (9UL)
 
#define POWER_POFCON_THRESHOLD_V23   (10UL)
 
#define POWER_POFCON_THRESHOLD_V24   (11UL)
 
#define POWER_POFCON_THRESHOLD_V25   (12UL)
 
#define POWER_POFCON_THRESHOLD_V26   (13UL)
 
#define POWER_POFCON_THRESHOLD_V27   (14UL)
 
#define POWER_POFCON_THRESHOLD_V28   (15UL)
 
#define POWER_POFCON_POF_Pos   (0UL)
 
#define POWER_POFCON_POF_Msk   (0x1UL << POWER_POFCON_POF_Pos)
 
#define POWER_POFCON_POF_Disabled   (0UL)
 
#define POWER_POFCON_POF_Enabled   (1UL)
 
#define POWER_GPREGRET_GPREGRET_Pos   (0UL)
 
#define POWER_GPREGRET_GPREGRET_Msk   (0xFFUL << POWER_GPREGRET_GPREGRET_Pos)
 
#define POWER_GPREGRET2_GPREGRET_Pos   (0UL)
 
#define POWER_GPREGRET2_GPREGRET_Msk   (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos)
 
#define POWER_RAMON_OFFRAM1_Pos   (17UL)
 
#define POWER_RAMON_OFFRAM1_Msk   (0x1UL << POWER_RAMON_OFFRAM1_Pos)
 
#define POWER_RAMON_OFFRAM1_RAM1Off   (0UL)
 
#define POWER_RAMON_OFFRAM1_RAM1On   (1UL)
 
#define POWER_RAMON_OFFRAM0_Pos   (16UL)
 
#define POWER_RAMON_OFFRAM0_Msk   (0x1UL << POWER_RAMON_OFFRAM0_Pos)
 
#define POWER_RAMON_OFFRAM0_RAM0Off   (0UL)
 
#define POWER_RAMON_OFFRAM0_RAM0On   (1UL)
 
#define POWER_RAMON_ONRAM1_Pos   (1UL)
 
#define POWER_RAMON_ONRAM1_Msk   (0x1UL << POWER_RAMON_ONRAM1_Pos)
 
#define POWER_RAMON_ONRAM1_RAM1Off   (0UL)
 
#define POWER_RAMON_ONRAM1_RAM1On   (1UL)
 
#define POWER_RAMON_ONRAM0_Pos   (0UL)
 
#define POWER_RAMON_ONRAM0_Msk   (0x1UL << POWER_RAMON_ONRAM0_Pos)
 
#define POWER_RAMON_ONRAM0_RAM0Off   (0UL)
 
#define POWER_RAMON_ONRAM0_RAM0On   (1UL)
 
#define POWER_RAMONB_OFFRAM3_Pos   (17UL)
 
#define POWER_RAMONB_OFFRAM3_Msk   (0x1UL << POWER_RAMONB_OFFRAM3_Pos)
 
#define POWER_RAMONB_OFFRAM3_RAM3Off   (0UL)
 
#define POWER_RAMONB_OFFRAM3_RAM3On   (1UL)
 
#define POWER_RAMONB_OFFRAM2_Pos   (16UL)
 
#define POWER_RAMONB_OFFRAM2_Msk   (0x1UL << POWER_RAMONB_OFFRAM2_Pos)
 
#define POWER_RAMONB_OFFRAM2_RAM2Off   (0UL)
 
#define POWER_RAMONB_OFFRAM2_RAM2On   (1UL)
 
#define POWER_RAMONB_ONRAM3_Pos   (1UL)
 
#define POWER_RAMONB_ONRAM3_Msk   (0x1UL << POWER_RAMONB_ONRAM3_Pos)
 
#define POWER_RAMONB_ONRAM3_RAM3Off   (0UL)
 
#define POWER_RAMONB_ONRAM3_RAM3On   (1UL)
 
#define POWER_RAMONB_ONRAM2_Pos   (0UL)
 
#define POWER_RAMONB_ONRAM2_Msk   (0x1UL << POWER_RAMONB_ONRAM2_Pos)
 
#define POWER_RAMONB_ONRAM2_RAM2Off   (0UL)
 
#define POWER_RAMONB_ONRAM2_RAM2On   (1UL)
 
#define POWER_DCDCEN_DCDCEN_Pos   (0UL)
 
#define POWER_DCDCEN_DCDCEN_Msk   (0x1UL << POWER_DCDCEN_DCDCEN_Pos)
 
#define POWER_DCDCEN_DCDCEN_Disabled   (0UL)
 
#define POWER_DCDCEN_DCDCEN_Enabled   (1UL)
 
#define POWER_RAM_POWER_S1RETENTION_Pos   (17UL)
 
#define POWER_RAM_POWER_S1RETENTION_Msk   (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos)
 
#define POWER_RAM_POWER_S1RETENTION_Off   (0UL)
 
#define POWER_RAM_POWER_S1RETENTION_On   (1UL)
 
#define POWER_RAM_POWER_S0RETENTION_Pos   (16UL)
 
#define POWER_RAM_POWER_S0RETENTION_Msk   (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos)
 
#define POWER_RAM_POWER_S0RETENTION_Off   (0UL)
 
#define POWER_RAM_POWER_S0RETENTION_On   (1UL)
 
#define POWER_RAM_POWER_S1POWER_Pos   (1UL)
 
#define POWER_RAM_POWER_S1POWER_Msk   (0x1UL << POWER_RAM_POWER_S1POWER_Pos)
 
#define POWER_RAM_POWER_S1POWER_Off   (0UL)
 
#define POWER_RAM_POWER_S1POWER_On   (1UL)
 
#define POWER_RAM_POWER_S0POWER_Pos   (0UL)
 
#define POWER_RAM_POWER_S0POWER_Msk   (0x1UL << POWER_RAM_POWER_S0POWER_Pos)
 
#define POWER_RAM_POWER_S0POWER_Off   (0UL)
 
#define POWER_RAM_POWER_S0POWER_On   (1UL)
 
#define POWER_RAM_POWERSET_S1RETENTION_Pos   (17UL)
 
#define POWER_RAM_POWERSET_S1RETENTION_Msk   (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos)
 
#define POWER_RAM_POWERSET_S1RETENTION_On   (1UL)
 
#define POWER_RAM_POWERSET_S0RETENTION_Pos   (16UL)
 
#define POWER_RAM_POWERSET_S0RETENTION_Msk   (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos)
 
#define POWER_RAM_POWERSET_S0RETENTION_On   (1UL)
 
#define POWER_RAM_POWERSET_S1POWER_Pos   (1UL)
 
#define POWER_RAM_POWERSET_S1POWER_Msk   (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos)
 
#define POWER_RAM_POWERSET_S1POWER_On   (1UL)
 
#define POWER_RAM_POWERSET_S0POWER_Pos   (0UL)
 
#define POWER_RAM_POWERSET_S0POWER_Msk   (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos)
 
#define POWER_RAM_POWERSET_S0POWER_On   (1UL)
 
#define POWER_RAM_POWERCLR_S1RETENTION_Pos   (17UL)
 
#define POWER_RAM_POWERCLR_S1RETENTION_Msk   (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos)
 
#define POWER_RAM_POWERCLR_S1RETENTION_Off   (1UL)
 
#define POWER_RAM_POWERCLR_S0RETENTION_Pos   (16UL)
 
#define POWER_RAM_POWERCLR_S0RETENTION_Msk   (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos)
 
#define POWER_RAM_POWERCLR_S0RETENTION_Off   (1UL)
 
#define POWER_RAM_POWERCLR_S1POWER_Pos   (1UL)
 
#define POWER_RAM_POWERCLR_S1POWER_Msk   (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos)
 
#define POWER_RAM_POWERCLR_S1POWER_Off   (1UL)
 
#define POWER_RAM_POWERCLR_S0POWER_Pos   (0UL)
 
#define POWER_RAM_POWERCLR_S0POWER_Msk   (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos)
 
#define POWER_RAM_POWERCLR_S0POWER_Off   (1UL)
 
#define PPI_CHEN_CH31_Pos   (31UL)
 
#define PPI_CHEN_CH31_Msk   (0x1UL << PPI_CHEN_CH31_Pos)
 
#define PPI_CHEN_CH31_Disabled   (0UL)
 
#define PPI_CHEN_CH31_Enabled   (1UL)
 
#define PPI_CHEN_CH30_Pos   (30UL)
 
#define PPI_CHEN_CH30_Msk   (0x1UL << PPI_CHEN_CH30_Pos)
 
#define PPI_CHEN_CH30_Disabled   (0UL)
 
#define PPI_CHEN_CH30_Enabled   (1UL)
 
#define PPI_CHEN_CH29_Pos   (29UL)
 
#define PPI_CHEN_CH29_Msk   (0x1UL << PPI_CHEN_CH29_Pos)
 
#define PPI_CHEN_CH29_Disabled   (0UL)
 
#define PPI_CHEN_CH29_Enabled   (1UL)
 
#define PPI_CHEN_CH28_Pos   (28UL)
 
#define PPI_CHEN_CH28_Msk   (0x1UL << PPI_CHEN_CH28_Pos)
 
#define PPI_CHEN_CH28_Disabled   (0UL)
 
#define PPI_CHEN_CH28_Enabled   (1UL)
 
#define PPI_CHEN_CH27_Pos   (27UL)
 
#define PPI_CHEN_CH27_Msk   (0x1UL << PPI_CHEN_CH27_Pos)
 
#define PPI_CHEN_CH27_Disabled   (0UL)
 
#define PPI_CHEN_CH27_Enabled   (1UL)
 
#define PPI_CHEN_CH26_Pos   (26UL)
 
#define PPI_CHEN_CH26_Msk   (0x1UL << PPI_CHEN_CH26_Pos)
 
#define PPI_CHEN_CH26_Disabled   (0UL)
 
#define PPI_CHEN_CH26_Enabled   (1UL)
 
#define PPI_CHEN_CH25_Pos   (25UL)
 
#define PPI_CHEN_CH25_Msk   (0x1UL << PPI_CHEN_CH25_Pos)
 
#define PPI_CHEN_CH25_Disabled   (0UL)
 
#define PPI_CHEN_CH25_Enabled   (1UL)
 
#define PPI_CHEN_CH24_Pos   (24UL)
 
#define PPI_CHEN_CH24_Msk   (0x1UL << PPI_CHEN_CH24_Pos)
 
#define PPI_CHEN_CH24_Disabled   (0UL)
 
#define PPI_CHEN_CH24_Enabled   (1UL)
 
#define PPI_CHEN_CH23_Pos   (23UL)
 
#define PPI_CHEN_CH23_Msk   (0x1UL << PPI_CHEN_CH23_Pos)
 
#define PPI_CHEN_CH23_Disabled   (0UL)
 
#define PPI_CHEN_CH23_Enabled   (1UL)
 
#define PPI_CHEN_CH22_Pos   (22UL)
 
#define PPI_CHEN_CH22_Msk   (0x1UL << PPI_CHEN_CH22_Pos)
 
#define PPI_CHEN_CH22_Disabled   (0UL)
 
#define PPI_CHEN_CH22_Enabled   (1UL)
 
#define PPI_CHEN_CH21_Pos   (21UL)
 
#define PPI_CHEN_CH21_Msk   (0x1UL << PPI_CHEN_CH21_Pos)
 
#define PPI_CHEN_CH21_Disabled   (0UL)
 
#define PPI_CHEN_CH21_Enabled   (1UL)
 
#define PPI_CHEN_CH20_Pos   (20UL)
 
#define PPI_CHEN_CH20_Msk   (0x1UL << PPI_CHEN_CH20_Pos)
 
#define PPI_CHEN_CH20_Disabled   (0UL)
 
#define PPI_CHEN_CH20_Enabled   (1UL)
 
#define PPI_CHEN_CH19_Pos   (19UL)
 
#define PPI_CHEN_CH19_Msk   (0x1UL << PPI_CHEN_CH19_Pos)
 
#define PPI_CHEN_CH19_Disabled   (0UL)
 
#define PPI_CHEN_CH19_Enabled   (1UL)
 
#define PPI_CHEN_CH18_Pos   (18UL)
 
#define PPI_CHEN_CH18_Msk   (0x1UL << PPI_CHEN_CH18_Pos)
 
#define PPI_CHEN_CH18_Disabled   (0UL)
 
#define PPI_CHEN_CH18_Enabled   (1UL)
 
#define PPI_CHEN_CH17_Pos   (17UL)
 
#define PPI_CHEN_CH17_Msk   (0x1UL << PPI_CHEN_CH17_Pos)
 
#define PPI_CHEN_CH17_Disabled   (0UL)
 
#define PPI_CHEN_CH17_Enabled   (1UL)
 
#define PPI_CHEN_CH16_Pos   (16UL)
 
#define PPI_CHEN_CH16_Msk   (0x1UL << PPI_CHEN_CH16_Pos)
 
#define PPI_CHEN_CH16_Disabled   (0UL)
 
#define PPI_CHEN_CH16_Enabled   (1UL)
 
#define PPI_CHEN_CH15_Pos   (15UL)
 
#define PPI_CHEN_CH15_Msk   (0x1UL << PPI_CHEN_CH15_Pos)
 
#define PPI_CHEN_CH15_Disabled   (0UL)
 
#define PPI_CHEN_CH15_Enabled   (1UL)
 
#define PPI_CHEN_CH14_Pos   (14UL)
 
#define PPI_CHEN_CH14_Msk   (0x1UL << PPI_CHEN_CH14_Pos)
 
#define PPI_CHEN_CH14_Disabled   (0UL)
 
#define PPI_CHEN_CH14_Enabled   (1UL)
 
#define PPI_CHEN_CH13_Pos   (13UL)
 
#define PPI_CHEN_CH13_Msk   (0x1UL << PPI_CHEN_CH13_Pos)
 
#define PPI_CHEN_CH13_Disabled   (0UL)
 
#define PPI_CHEN_CH13_Enabled   (1UL)
 
#define PPI_CHEN_CH12_Pos   (12UL)
 
#define PPI_CHEN_CH12_Msk   (0x1UL << PPI_CHEN_CH12_Pos)
 
#define PPI_CHEN_CH12_Disabled   (0UL)
 
#define PPI_CHEN_CH12_Enabled   (1UL)
 
#define PPI_CHEN_CH11_Pos   (11UL)
 
#define PPI_CHEN_CH11_Msk   (0x1UL << PPI_CHEN_CH11_Pos)
 
#define PPI_CHEN_CH11_Disabled   (0UL)
 
#define PPI_CHEN_CH11_Enabled   (1UL)
 
#define PPI_CHEN_CH10_Pos   (10UL)
 
#define PPI_CHEN_CH10_Msk   (0x1UL << PPI_CHEN_CH10_Pos)
 
#define PPI_CHEN_CH10_Disabled   (0UL)
 
#define PPI_CHEN_CH10_Enabled   (1UL)
 
#define PPI_CHEN_CH9_Pos   (9UL)
 
#define PPI_CHEN_CH9_Msk   (0x1UL << PPI_CHEN_CH9_Pos)
 
#define PPI_CHEN_CH9_Disabled   (0UL)
 
#define PPI_CHEN_CH9_Enabled   (1UL)
 
#define PPI_CHEN_CH8_Pos   (8UL)
 
#define PPI_CHEN_CH8_Msk   (0x1UL << PPI_CHEN_CH8_Pos)
 
#define PPI_CHEN_CH8_Disabled   (0UL)
 
#define PPI_CHEN_CH8_Enabled   (1UL)
 
#define PPI_CHEN_CH7_Pos   (7UL)
 
#define PPI_CHEN_CH7_Msk   (0x1UL << PPI_CHEN_CH7_Pos)
 
#define PPI_CHEN_CH7_Disabled   (0UL)
 
#define PPI_CHEN_CH7_Enabled   (1UL)
 
#define PPI_CHEN_CH6_Pos   (6UL)
 
#define PPI_CHEN_CH6_Msk   (0x1UL << PPI_CHEN_CH6_Pos)
 
#define PPI_CHEN_CH6_Disabled   (0UL)
 
#define PPI_CHEN_CH6_Enabled   (1UL)
 
#define PPI_CHEN_CH5_Pos   (5UL)
 
#define PPI_CHEN_CH5_Msk   (0x1UL << PPI_CHEN_CH5_Pos)
 
#define PPI_CHEN_CH5_Disabled   (0UL)
 
#define PPI_CHEN_CH5_Enabled   (1UL)
 
#define PPI_CHEN_CH4_Pos   (4UL)
 
#define PPI_CHEN_CH4_Msk   (0x1UL << PPI_CHEN_CH4_Pos)
 
#define PPI_CHEN_CH4_Disabled   (0UL)
 
#define PPI_CHEN_CH4_Enabled   (1UL)
 
#define PPI_CHEN_CH3_Pos   (3UL)
 
#define PPI_CHEN_CH3_Msk   (0x1UL << PPI_CHEN_CH3_Pos)
 
#define PPI_CHEN_CH3_Disabled   (0UL)
 
#define PPI_CHEN_CH3_Enabled   (1UL)
 
#define PPI_CHEN_CH2_Pos   (2UL)
 
#define PPI_CHEN_CH2_Msk   (0x1UL << PPI_CHEN_CH2_Pos)
 
#define PPI_CHEN_CH2_Disabled   (0UL)
 
#define PPI_CHEN_CH2_Enabled   (1UL)
 
#define PPI_CHEN_CH1_Pos   (1UL)
 
#define PPI_CHEN_CH1_Msk   (0x1UL << PPI_CHEN_CH1_Pos)
 
#define PPI_CHEN_CH1_Disabled   (0UL)
 
#define PPI_CHEN_CH1_Enabled   (1UL)
 
#define PPI_CHEN_CH0_Pos   (0UL)
 
#define PPI_CHEN_CH0_Msk   (0x1UL << PPI_CHEN_CH0_Pos)
 
#define PPI_CHEN_CH0_Disabled   (0UL)
 
#define PPI_CHEN_CH0_Enabled   (1UL)
 
#define PPI_CHENSET_CH31_Pos   (31UL)
 
#define PPI_CHENSET_CH31_Msk   (0x1UL << PPI_CHENSET_CH31_Pos)
 
#define PPI_CHENSET_CH31_Disabled   (0UL)
 
#define PPI_CHENSET_CH31_Enabled   (1UL)
 
#define PPI_CHENSET_CH31_Set   (1UL)
 
#define PPI_CHENSET_CH30_Pos   (30UL)
 
#define PPI_CHENSET_CH30_Msk   (0x1UL << PPI_CHENSET_CH30_Pos)
 
#define PPI_CHENSET_CH30_Disabled   (0UL)
 
#define PPI_CHENSET_CH30_Enabled   (1UL)
 
#define PPI_CHENSET_CH30_Set   (1UL)
 
#define PPI_CHENSET_CH29_Pos   (29UL)
 
#define PPI_CHENSET_CH29_Msk   (0x1UL << PPI_CHENSET_CH29_Pos)
 
#define PPI_CHENSET_CH29_Disabled   (0UL)
 
#define PPI_CHENSET_CH29_Enabled   (1UL)
 
#define PPI_CHENSET_CH29_Set   (1UL)
 
#define PPI_CHENSET_CH28_Pos   (28UL)
 
#define PPI_CHENSET_CH28_Msk   (0x1UL << PPI_CHENSET_CH28_Pos)
 
#define PPI_CHENSET_CH28_Disabled   (0UL)
 
#define PPI_CHENSET_CH28_Enabled   (1UL)
 
#define PPI_CHENSET_CH28_Set   (1UL)
 
#define PPI_CHENSET_CH27_Pos   (27UL)
 
#define PPI_CHENSET_CH27_Msk   (0x1UL << PPI_CHENSET_CH27_Pos)
 
#define PPI_CHENSET_CH27_Disabled   (0UL)
 
#define PPI_CHENSET_CH27_Enabled   (1UL)
 
#define PPI_CHENSET_CH27_Set   (1UL)
 
#define PPI_CHENSET_CH26_Pos   (26UL)
 
#define PPI_CHENSET_CH26_Msk   (0x1UL << PPI_CHENSET_CH26_Pos)
 
#define PPI_CHENSET_CH26_Disabled   (0UL)
 
#define PPI_CHENSET_CH26_Enabled   (1UL)
 
#define PPI_CHENSET_CH26_Set   (1UL)
 
#define PPI_CHENSET_CH25_Pos   (25UL)
 
#define PPI_CHENSET_CH25_Msk   (0x1UL << PPI_CHENSET_CH25_Pos)
 
#define PPI_CHENSET_CH25_Disabled   (0UL)
 
#define PPI_CHENSET_CH25_Enabled   (1UL)
 
#define PPI_CHENSET_CH25_Set   (1UL)
 
#define PPI_CHENSET_CH24_Pos   (24UL)
 
#define PPI_CHENSET_CH24_Msk   (0x1UL << PPI_CHENSET_CH24_Pos)
 
#define PPI_CHENSET_CH24_Disabled   (0UL)
 
#define PPI_CHENSET_CH24_Enabled   (1UL)
 
#define PPI_CHENSET_CH24_Set   (1UL)
 
#define PPI_CHENSET_CH23_Pos   (23UL)
 
#define PPI_CHENSET_CH23_Msk   (0x1UL << PPI_CHENSET_CH23_Pos)
 
#define PPI_CHENSET_CH23_Disabled   (0UL)
 
#define PPI_CHENSET_CH23_Enabled   (1UL)
 
#define PPI_CHENSET_CH23_Set   (1UL)
 
#define PPI_CHENSET_CH22_Pos   (22UL)
 
#define PPI_CHENSET_CH22_Msk   (0x1UL << PPI_CHENSET_CH22_Pos)
 
#define PPI_CHENSET_CH22_Disabled   (0UL)
 
#define PPI_CHENSET_CH22_Enabled   (1UL)
 
#define PPI_CHENSET_CH22_Set   (1UL)
 
#define PPI_CHENSET_CH21_Pos   (21UL)
 
#define PPI_CHENSET_CH21_Msk   (0x1UL << PPI_CHENSET_CH21_Pos)
 
#define PPI_CHENSET_CH21_Disabled   (0UL)
 
#define PPI_CHENSET_CH21_Enabled   (1UL)
 
#define PPI_CHENSET_CH21_Set   (1UL)
 
#define PPI_CHENSET_CH20_Pos   (20UL)
 
#define PPI_CHENSET_CH20_Msk   (0x1UL << PPI_CHENSET_CH20_Pos)
 
#define PPI_CHENSET_CH20_Disabled   (0UL)
 
#define PPI_CHENSET_CH20_Enabled   (1UL)
 
#define PPI_CHENSET_CH20_Set   (1UL)
 
#define PPI_CHENSET_CH19_Pos   (19UL)
 
#define PPI_CHENSET_CH19_Msk   (0x1UL << PPI_CHENSET_CH19_Pos)
 
#define PPI_CHENSET_CH19_Disabled   (0UL)
 
#define PPI_CHENSET_CH19_Enabled   (1UL)
 
#define PPI_CHENSET_CH19_Set   (1UL)
 
#define PPI_CHENSET_CH18_Pos   (18UL)
 
#define PPI_CHENSET_CH18_Msk   (0x1UL << PPI_CHENSET_CH18_Pos)
 
#define PPI_CHENSET_CH18_Disabled   (0UL)
 
#define PPI_CHENSET_CH18_Enabled   (1UL)
 
#define PPI_CHENSET_CH18_Set   (1UL)
 
#define PPI_CHENSET_CH17_Pos   (17UL)
 
#define PPI_CHENSET_CH17_Msk   (0x1UL << PPI_CHENSET_CH17_Pos)
 
#define PPI_CHENSET_CH17_Disabled   (0UL)
 
#define PPI_CHENSET_CH17_Enabled   (1UL)
 
#define PPI_CHENSET_CH17_Set   (1UL)
 
#define PPI_CHENSET_CH16_Pos   (16UL)
 
#define PPI_CHENSET_CH16_Msk   (0x1UL << PPI_CHENSET_CH16_Pos)
 
#define PPI_CHENSET_CH16_Disabled   (0UL)
 
#define PPI_CHENSET_CH16_Enabled   (1UL)
 
#define PPI_CHENSET_CH16_Set   (1UL)
 
#define PPI_CHENSET_CH15_Pos   (15UL)
 
#define PPI_CHENSET_CH15_Msk   (0x1UL << PPI_CHENSET_CH15_Pos)
 
#define PPI_CHENSET_CH15_Disabled   (0UL)
 
#define PPI_CHENSET_CH15_Enabled   (1UL)
 
#define PPI_CHENSET_CH15_Set   (1UL)
 
#define PPI_CHENSET_CH14_Pos   (14UL)
 
#define PPI_CHENSET_CH14_Msk   (0x1UL << PPI_CHENSET_CH14_Pos)
 
#define PPI_CHENSET_CH14_Disabled   (0UL)
 
#define PPI_CHENSET_CH14_Enabled   (1UL)
 
#define PPI_CHENSET_CH14_Set   (1UL)
 
#define PPI_CHENSET_CH13_Pos   (13UL)
 
#define PPI_CHENSET_CH13_Msk   (0x1UL << PPI_CHENSET_CH13_Pos)
 
#define PPI_CHENSET_CH13_Disabled   (0UL)
 
#define PPI_CHENSET_CH13_Enabled   (1UL)
 
#define PPI_CHENSET_CH13_Set   (1UL)
 
#define PPI_CHENSET_CH12_Pos   (12UL)
 
#define PPI_CHENSET_CH12_Msk   (0x1UL << PPI_CHENSET_CH12_Pos)
 
#define PPI_CHENSET_CH12_Disabled   (0UL)
 
#define PPI_CHENSET_CH12_Enabled   (1UL)
 
#define PPI_CHENSET_CH12_Set   (1UL)
 
#define PPI_CHENSET_CH11_Pos   (11UL)
 
#define PPI_CHENSET_CH11_Msk   (0x1UL << PPI_CHENSET_CH11_Pos)
 
#define PPI_CHENSET_CH11_Disabled   (0UL)
 
#define PPI_CHENSET_CH11_Enabled   (1UL)
 
#define PPI_CHENSET_CH11_Set   (1UL)
 
#define PPI_CHENSET_CH10_Pos   (10UL)
 
#define PPI_CHENSET_CH10_Msk   (0x1UL << PPI_CHENSET_CH10_Pos)
 
#define PPI_CHENSET_CH10_Disabled   (0UL)
 
#define PPI_CHENSET_CH10_Enabled   (1UL)
 
#define PPI_CHENSET_CH10_Set   (1UL)
 
#define PPI_CHENSET_CH9_Pos   (9UL)
 
#define PPI_CHENSET_CH9_Msk   (0x1UL << PPI_CHENSET_CH9_Pos)
 
#define PPI_CHENSET_CH9_Disabled   (0UL)
 
#define PPI_CHENSET_CH9_Enabled   (1UL)
 
#define PPI_CHENSET_CH9_Set   (1UL)
 
#define PPI_CHENSET_CH8_Pos   (8UL)
 
#define PPI_CHENSET_CH8_Msk   (0x1UL << PPI_CHENSET_CH8_Pos)
 
#define PPI_CHENSET_CH8_Disabled   (0UL)
 
#define PPI_CHENSET_CH8_Enabled   (1UL)
 
#define PPI_CHENSET_CH8_Set   (1UL)
 
#define PPI_CHENSET_CH7_Pos   (7UL)
 
#define PPI_CHENSET_CH7_Msk   (0x1UL << PPI_CHENSET_CH7_Pos)
 
#define PPI_CHENSET_CH7_Disabled   (0UL)
 
#define PPI_CHENSET_CH7_Enabled   (1UL)
 
#define PPI_CHENSET_CH7_Set   (1UL)
 
#define PPI_CHENSET_CH6_Pos   (6UL)
 
#define PPI_CHENSET_CH6_Msk   (0x1UL << PPI_CHENSET_CH6_Pos)
 
#define PPI_CHENSET_CH6_Disabled   (0UL)
 
#define PPI_CHENSET_CH6_Enabled   (1UL)
 
#define PPI_CHENSET_CH6_Set   (1UL)
 
#define PPI_CHENSET_CH5_Pos   (5UL)
 
#define PPI_CHENSET_CH5_Msk   (0x1UL << PPI_CHENSET_CH5_Pos)
 
#define PPI_CHENSET_CH5_Disabled   (0UL)
 
#define PPI_CHENSET_CH5_Enabled   (1UL)
 
#define PPI_CHENSET_CH5_Set   (1UL)
 
#define PPI_CHENSET_CH4_Pos   (4UL)
 
#define PPI_CHENSET_CH4_Msk   (0x1UL << PPI_CHENSET_CH4_Pos)
 
#define PPI_CHENSET_CH4_Disabled   (0UL)
 
#define PPI_CHENSET_CH4_Enabled   (1UL)
 
#define PPI_CHENSET_CH4_Set   (1UL)
 
#define PPI_CHENSET_CH3_Pos   (3UL)
 
#define PPI_CHENSET_CH3_Msk   (0x1UL << PPI_CHENSET_CH3_Pos)
 
#define PPI_CHENSET_CH3_Disabled   (0UL)
 
#define PPI_CHENSET_CH3_Enabled   (1UL)
 
#define PPI_CHENSET_CH3_Set   (1UL)
 
#define PPI_CHENSET_CH2_Pos   (2UL)
 
#define PPI_CHENSET_CH2_Msk   (0x1UL << PPI_CHENSET_CH2_Pos)
 
#define PPI_CHENSET_CH2_Disabled   (0UL)
 
#define PPI_CHENSET_CH2_Enabled   (1UL)
 
#define PPI_CHENSET_CH2_Set   (1UL)
 
#define PPI_CHENSET_CH1_Pos   (1UL)
 
#define PPI_CHENSET_CH1_Msk   (0x1UL << PPI_CHENSET_CH1_Pos)
 
#define PPI_CHENSET_CH1_Disabled   (0UL)
 
#define PPI_CHENSET_CH1_Enabled   (1UL)
 
#define PPI_CHENSET_CH1_Set   (1UL)
 
#define PPI_CHENSET_CH0_Pos   (0UL)
 
#define PPI_CHENSET_CH0_Msk   (0x1UL << PPI_CHENSET_CH0_Pos)
 
#define PPI_CHENSET_CH0_Disabled   (0UL)
 
#define PPI_CHENSET_CH0_Enabled   (1UL)
 
#define PPI_CHENSET_CH0_Set   (1UL)
 
#define PPI_CHENCLR_CH31_Pos   (31UL)
 
#define PPI_CHENCLR_CH31_Msk   (0x1UL << PPI_CHENCLR_CH31_Pos)
 
#define PPI_CHENCLR_CH31_Disabled   (0UL)
 
#define PPI_CHENCLR_CH31_Enabled   (1UL)
 
#define PPI_CHENCLR_CH31_Clear   (1UL)
 
#define PPI_CHENCLR_CH30_Pos   (30UL)
 
#define PPI_CHENCLR_CH30_Msk   (0x1UL << PPI_CHENCLR_CH30_Pos)
 
#define PPI_CHENCLR_CH30_Disabled   (0UL)
 
#define PPI_CHENCLR_CH30_Enabled   (1UL)
 
#define PPI_CHENCLR_CH30_Clear   (1UL)
 
#define PPI_CHENCLR_CH29_Pos   (29UL)
 
#define PPI_CHENCLR_CH29_Msk   (0x1UL << PPI_CHENCLR_CH29_Pos)
 
#define PPI_CHENCLR_CH29_Disabled   (0UL)
 
#define PPI_CHENCLR_CH29_Enabled   (1UL)
 
#define PPI_CHENCLR_CH29_Clear   (1UL)
 
#define PPI_CHENCLR_CH28_Pos   (28UL)
 
#define PPI_CHENCLR_CH28_Msk   (0x1UL << PPI_CHENCLR_CH28_Pos)
 
#define PPI_CHENCLR_CH28_Disabled   (0UL)
 
#define PPI_CHENCLR_CH28_Enabled   (1UL)
 
#define PPI_CHENCLR_CH28_Clear   (1UL)
 
#define PPI_CHENCLR_CH27_Pos   (27UL)
 
#define PPI_CHENCLR_CH27_Msk   (0x1UL << PPI_CHENCLR_CH27_Pos)
 
#define PPI_CHENCLR_CH27_Disabled   (0UL)
 
#define PPI_CHENCLR_CH27_Enabled   (1UL)
 
#define PPI_CHENCLR_CH27_Clear   (1UL)
 
#define PPI_CHENCLR_CH26_Pos   (26UL)
 
#define PPI_CHENCLR_CH26_Msk   (0x1UL << PPI_CHENCLR_CH26_Pos)
 
#define PPI_CHENCLR_CH26_Disabled   (0UL)
 
#define PPI_CHENCLR_CH26_Enabled   (1UL)
 
#define PPI_CHENCLR_CH26_Clear   (1UL)
 
#define PPI_CHENCLR_CH25_Pos   (25UL)
 
#define PPI_CHENCLR_CH25_Msk   (0x1UL << PPI_CHENCLR_CH25_Pos)
 
#define PPI_CHENCLR_CH25_Disabled   (0UL)
 
#define PPI_CHENCLR_CH25_Enabled   (1UL)
 
#define PPI_CHENCLR_CH25_Clear   (1UL)
 
#define PPI_CHENCLR_CH24_Pos   (24UL)
 
#define PPI_CHENCLR_CH24_Msk   (0x1UL << PPI_CHENCLR_CH24_Pos)
 
#define PPI_CHENCLR_CH24_Disabled   (0UL)
 
#define PPI_CHENCLR_CH24_Enabled   (1UL)
 
#define PPI_CHENCLR_CH24_Clear   (1UL)
 
#define PPI_CHENCLR_CH23_Pos   (23UL)
 
#define PPI_CHENCLR_CH23_Msk   (0x1UL << PPI_CHENCLR_CH23_Pos)
 
#define PPI_CHENCLR_CH23_Disabled   (0UL)
 
#define PPI_CHENCLR_CH23_Enabled   (1UL)
 
#define PPI_CHENCLR_CH23_Clear   (1UL)
 
#define PPI_CHENCLR_CH22_Pos   (22UL)
 
#define PPI_CHENCLR_CH22_Msk   (0x1UL << PPI_CHENCLR_CH22_Pos)
 
#define PPI_CHENCLR_CH22_Disabled   (0UL)
 
#define PPI_CHENCLR_CH22_Enabled   (1UL)
 
#define PPI_CHENCLR_CH22_Clear   (1UL)
 
#define PPI_CHENCLR_CH21_Pos   (21UL)
 
#define PPI_CHENCLR_CH21_Msk   (0x1UL << PPI_CHENCLR_CH21_Pos)
 
#define PPI_CHENCLR_CH21_Disabled   (0UL)
 
#define PPI_CHENCLR_CH21_Enabled   (1UL)
 
#define PPI_CHENCLR_CH21_Clear   (1UL)
 
#define PPI_CHENCLR_CH20_Pos   (20UL)
 
#define PPI_CHENCLR_CH20_Msk   (0x1UL << PPI_CHENCLR_CH20_Pos)
 
#define PPI_CHENCLR_CH20_Disabled   (0UL)
 
#define PPI_CHENCLR_CH20_Enabled   (1UL)
 
#define PPI_CHENCLR_CH20_Clear   (1UL)
 
#define PPI_CHENCLR_CH19_Pos   (19UL)
 
#define PPI_CHENCLR_CH19_Msk   (0x1UL << PPI_CHENCLR_CH19_Pos)
 
#define PPI_CHENCLR_CH19_Disabled   (0UL)
 
#define PPI_CHENCLR_CH19_Enabled   (1UL)
 
#define PPI_CHENCLR_CH19_Clear   (1UL)
 
#define PPI_CHENCLR_CH18_Pos   (18UL)
 
#define PPI_CHENCLR_CH18_Msk   (0x1UL << PPI_CHENCLR_CH18_Pos)
 
#define PPI_CHENCLR_CH18_Disabled   (0UL)
 
#define PPI_CHENCLR_CH18_Enabled   (1UL)
 
#define PPI_CHENCLR_CH18_Clear   (1UL)
 
#define PPI_CHENCLR_CH17_Pos   (17UL)
 
#define PPI_CHENCLR_CH17_Msk   (0x1UL << PPI_CHENCLR_CH17_Pos)
 
#define PPI_CHENCLR_CH17_Disabled   (0UL)
 
#define PPI_CHENCLR_CH17_Enabled   (1UL)
 
#define PPI_CHENCLR_CH17_Clear   (1UL)
 
#define PPI_CHENCLR_CH16_Pos   (16UL)
 
#define PPI_CHENCLR_CH16_Msk   (0x1UL << PPI_CHENCLR_CH16_Pos)
 
#define PPI_CHENCLR_CH16_Disabled   (0UL)
 
#define PPI_CHENCLR_CH16_Enabled   (1UL)
 
#define PPI_CHENCLR_CH16_Clear   (1UL)
 
#define PPI_CHENCLR_CH15_Pos   (15UL)
 
#define PPI_CHENCLR_CH15_Msk   (0x1UL << PPI_CHENCLR_CH15_Pos)
 
#define PPI_CHENCLR_CH15_Disabled   (0UL)
 
#define PPI_CHENCLR_CH15_Enabled   (1UL)
 
#define PPI_CHENCLR_CH15_Clear   (1UL)
 
#define PPI_CHENCLR_CH14_Pos   (14UL)
 
#define PPI_CHENCLR_CH14_Msk   (0x1UL << PPI_CHENCLR_CH14_Pos)
 
#define PPI_CHENCLR_CH14_Disabled   (0UL)
 
#define PPI_CHENCLR_CH14_Enabled   (1UL)
 
#define PPI_CHENCLR_CH14_Clear   (1UL)
 
#define PPI_CHENCLR_CH13_Pos   (13UL)
 
#define PPI_CHENCLR_CH13_Msk   (0x1UL << PPI_CHENCLR_CH13_Pos)
 
#define PPI_CHENCLR_CH13_Disabled   (0UL)
 
#define PPI_CHENCLR_CH13_Enabled   (1UL)
 
#define PPI_CHENCLR_CH13_Clear   (1UL)
 
#define PPI_CHENCLR_CH12_Pos   (12UL)
 
#define PPI_CHENCLR_CH12_Msk   (0x1UL << PPI_CHENCLR_CH12_Pos)
 
#define PPI_CHENCLR_CH12_Disabled   (0UL)
 
#define PPI_CHENCLR_CH12_Enabled   (1UL)
 
#define PPI_CHENCLR_CH12_Clear   (1UL)
 
#define PPI_CHENCLR_CH11_Pos   (11UL)
 
#define PPI_CHENCLR_CH11_Msk   (0x1UL << PPI_CHENCLR_CH11_Pos)
 
#define PPI_CHENCLR_CH11_Disabled   (0UL)
 
#define PPI_CHENCLR_CH11_Enabled   (1UL)
 
#define PPI_CHENCLR_CH11_Clear   (1UL)
 
#define PPI_CHENCLR_CH10_Pos   (10UL)
 
#define PPI_CHENCLR_CH10_Msk   (0x1UL << PPI_CHENCLR_CH10_Pos)
 
#define PPI_CHENCLR_CH10_Disabled   (0UL)
 
#define PPI_CHENCLR_CH10_Enabled   (1UL)
 
#define PPI_CHENCLR_CH10_Clear   (1UL)
 
#define PPI_CHENCLR_CH9_Pos   (9UL)
 
#define PPI_CHENCLR_CH9_Msk   (0x1UL << PPI_CHENCLR_CH9_Pos)
 
#define PPI_CHENCLR_CH9_Disabled   (0UL)
 
#define PPI_CHENCLR_CH9_Enabled   (1UL)
 
#define PPI_CHENCLR_CH9_Clear   (1UL)
 
#define PPI_CHENCLR_CH8_Pos   (8UL)
 
#define PPI_CHENCLR_CH8_Msk   (0x1UL << PPI_CHENCLR_CH8_Pos)
 
#define PPI_CHENCLR_CH8_Disabled   (0UL)
 
#define PPI_CHENCLR_CH8_Enabled   (1UL)
 
#define PPI_CHENCLR_CH8_Clear   (1UL)
 
#define PPI_CHENCLR_CH7_Pos   (7UL)
 
#define PPI_CHENCLR_CH7_Msk   (0x1UL << PPI_CHENCLR_CH7_Pos)
 
#define PPI_CHENCLR_CH7_Disabled   (0UL)
 
#define PPI_CHENCLR_CH7_Enabled   (1UL)
 
#define PPI_CHENCLR_CH7_Clear   (1UL)
 
#define PPI_CHENCLR_CH6_Pos   (6UL)
 
#define PPI_CHENCLR_CH6_Msk   (0x1UL << PPI_CHENCLR_CH6_Pos)
 
#define PPI_CHENCLR_CH6_Disabled   (0UL)
 
#define PPI_CHENCLR_CH6_Enabled   (1UL)
 
#define PPI_CHENCLR_CH6_Clear   (1UL)
 
#define PPI_CHENCLR_CH5_Pos   (5UL)
 
#define PPI_CHENCLR_CH5_Msk   (0x1UL << PPI_CHENCLR_CH5_Pos)
 
#define PPI_CHENCLR_CH5_Disabled   (0UL)
 
#define PPI_CHENCLR_CH5_Enabled   (1UL)
 
#define PPI_CHENCLR_CH5_Clear   (1UL)
 
#define PPI_CHENCLR_CH4_Pos   (4UL)
 
#define PPI_CHENCLR_CH4_Msk   (0x1UL << PPI_CHENCLR_CH4_Pos)
 
#define PPI_CHENCLR_CH4_Disabled   (0UL)
 
#define PPI_CHENCLR_CH4_Enabled   (1UL)
 
#define PPI_CHENCLR_CH4_Clear   (1UL)
 
#define PPI_CHENCLR_CH3_Pos   (3UL)
 
#define PPI_CHENCLR_CH3_Msk   (0x1UL << PPI_CHENCLR_CH3_Pos)
 
#define PPI_CHENCLR_CH3_Disabled   (0UL)
 
#define PPI_CHENCLR_CH3_Enabled   (1UL)
 
#define PPI_CHENCLR_CH3_Clear   (1UL)
 
#define PPI_CHENCLR_CH2_Pos   (2UL)
 
#define PPI_CHENCLR_CH2_Msk   (0x1UL << PPI_CHENCLR_CH2_Pos)
 
#define PPI_CHENCLR_CH2_Disabled   (0UL)
 
#define PPI_CHENCLR_CH2_Enabled   (1UL)
 
#define PPI_CHENCLR_CH2_Clear   (1UL)
 
#define PPI_CHENCLR_CH1_Pos   (1UL)
 
#define PPI_CHENCLR_CH1_Msk   (0x1UL << PPI_CHENCLR_CH1_Pos)
 
#define PPI_CHENCLR_CH1_Disabled   (0UL)
 
#define PPI_CHENCLR_CH1_Enabled   (1UL)
 
#define PPI_CHENCLR_CH1_Clear   (1UL)
 
#define PPI_CHENCLR_CH0_Pos   (0UL)
 
#define PPI_CHENCLR_CH0_Msk   (0x1UL << PPI_CHENCLR_CH0_Pos)
 
#define PPI_CHENCLR_CH0_Disabled   (0UL)
 
#define PPI_CHENCLR_CH0_Enabled   (1UL)
 
#define PPI_CHENCLR_CH0_Clear   (1UL)
 
#define PPI_CH_EEP_EEP_Pos   (0UL)
 
#define PPI_CH_EEP_EEP_Msk   (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos)
 
#define PPI_CH_TEP_TEP_Pos   (0UL)
 
#define PPI_CH_TEP_TEP_Msk   (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos)
 
#define PPI_CHG_CH31_Pos   (31UL)
 
#define PPI_CHG_CH31_Msk   (0x1UL << PPI_CHG_CH31_Pos)
 
#define PPI_CHG_CH31_Excluded   (0UL)
 
#define PPI_CHG_CH31_Included   (1UL)
 
#define PPI_CHG_CH30_Pos   (30UL)
 
#define PPI_CHG_CH30_Msk   (0x1UL << PPI_CHG_CH30_Pos)
 
#define PPI_CHG_CH30_Excluded   (0UL)
 
#define PPI_CHG_CH30_Included   (1UL)
 
#define PPI_CHG_CH29_Pos   (29UL)
 
#define PPI_CHG_CH29_Msk   (0x1UL << PPI_CHG_CH29_Pos)
 
#define PPI_CHG_CH29_Excluded   (0UL)
 
#define PPI_CHG_CH29_Included   (1UL)
 
#define PPI_CHG_CH28_Pos   (28UL)
 
#define PPI_CHG_CH28_Msk   (0x1UL << PPI_CHG_CH28_Pos)
 
#define PPI_CHG_CH28_Excluded   (0UL)
 
#define PPI_CHG_CH28_Included   (1UL)
 
#define PPI_CHG_CH27_Pos   (27UL)
 
#define PPI_CHG_CH27_Msk   (0x1UL << PPI_CHG_CH27_Pos)
 
#define PPI_CHG_CH27_Excluded   (0UL)
 
#define PPI_CHG_CH27_Included   (1UL)
 
#define PPI_CHG_CH26_Pos   (26UL)
 
#define PPI_CHG_CH26_Msk   (0x1UL << PPI_CHG_CH26_Pos)
 
#define PPI_CHG_CH26_Excluded   (0UL)
 
#define PPI_CHG_CH26_Included   (1UL)
 
#define PPI_CHG_CH25_Pos   (25UL)
 
#define PPI_CHG_CH25_Msk   (0x1UL << PPI_CHG_CH25_Pos)
 
#define PPI_CHG_CH25_Excluded   (0UL)
 
#define PPI_CHG_CH25_Included   (1UL)
 
#define PPI_CHG_CH24_Pos   (24UL)
 
#define PPI_CHG_CH24_Msk   (0x1UL << PPI_CHG_CH24_Pos)
 
#define PPI_CHG_CH24_Excluded   (0UL)
 
#define PPI_CHG_CH24_Included   (1UL)
 
#define PPI_CHG_CH23_Pos   (23UL)
 
#define PPI_CHG_CH23_Msk   (0x1UL << PPI_CHG_CH23_Pos)
 
#define PPI_CHG_CH23_Excluded   (0UL)
 
#define PPI_CHG_CH23_Included   (1UL)
 
#define PPI_CHG_CH22_Pos   (22UL)
 
#define PPI_CHG_CH22_Msk   (0x1UL << PPI_CHG_CH22_Pos)
 
#define PPI_CHG_CH22_Excluded   (0UL)
 
#define PPI_CHG_CH22_Included   (1UL)
 
#define PPI_CHG_CH21_Pos   (21UL)
 
#define PPI_CHG_CH21_Msk   (0x1UL << PPI_CHG_CH21_Pos)
 
#define PPI_CHG_CH21_Excluded   (0UL)
 
#define PPI_CHG_CH21_Included   (1UL)
 
#define PPI_CHG_CH20_Pos   (20UL)
 
#define PPI_CHG_CH20_Msk   (0x1UL << PPI_CHG_CH20_Pos)
 
#define PPI_CHG_CH20_Excluded   (0UL)
 
#define PPI_CHG_CH20_Included   (1UL)
 
#define PPI_CHG_CH19_Pos   (19UL)
 
#define PPI_CHG_CH19_Msk   (0x1UL << PPI_CHG_CH19_Pos)
 
#define PPI_CHG_CH19_Excluded   (0UL)
 
#define PPI_CHG_CH19_Included   (1UL)
 
#define PPI_CHG_CH18_Pos   (18UL)
 
#define PPI_CHG_CH18_Msk   (0x1UL << PPI_CHG_CH18_Pos)
 
#define PPI_CHG_CH18_Excluded   (0UL)
 
#define PPI_CHG_CH18_Included   (1UL)
 
#define PPI_CHG_CH17_Pos   (17UL)
 
#define PPI_CHG_CH17_Msk   (0x1UL << PPI_CHG_CH17_Pos)
 
#define PPI_CHG_CH17_Excluded   (0UL)
 
#define PPI_CHG_CH17_Included   (1UL)
 
#define PPI_CHG_CH16_Pos   (16UL)
 
#define PPI_CHG_CH16_Msk   (0x1UL << PPI_CHG_CH16_Pos)
 
#define PPI_CHG_CH16_Excluded   (0UL)
 
#define PPI_CHG_CH16_Included   (1UL)
 
#define PPI_CHG_CH15_Pos   (15UL)
 
#define PPI_CHG_CH15_Msk   (0x1UL << PPI_CHG_CH15_Pos)
 
#define PPI_CHG_CH15_Excluded   (0UL)
 
#define PPI_CHG_CH15_Included   (1UL)
 
#define PPI_CHG_CH14_Pos   (14UL)
 
#define PPI_CHG_CH14_Msk   (0x1UL << PPI_CHG_CH14_Pos)
 
#define PPI_CHG_CH14_Excluded   (0UL)
 
#define PPI_CHG_CH14_Included   (1UL)
 
#define PPI_CHG_CH13_Pos   (13UL)
 
#define PPI_CHG_CH13_Msk   (0x1UL << PPI_CHG_CH13_Pos)
 
#define PPI_CHG_CH13_Excluded   (0UL)
 
#define PPI_CHG_CH13_Included   (1UL)
 
#define PPI_CHG_CH12_Pos   (12UL)
 
#define PPI_CHG_CH12_Msk   (0x1UL << PPI_CHG_CH12_Pos)
 
#define PPI_CHG_CH12_Excluded   (0UL)
 
#define PPI_CHG_CH12_Included   (1UL)
 
#define PPI_CHG_CH11_Pos   (11UL)
 
#define PPI_CHG_CH11_Msk   (0x1UL << PPI_CHG_CH11_Pos)
 
#define PPI_CHG_CH11_Excluded   (0UL)
 
#define PPI_CHG_CH11_Included   (1UL)
 
#define PPI_CHG_CH10_Pos   (10UL)
 
#define PPI_CHG_CH10_Msk   (0x1UL << PPI_CHG_CH10_Pos)
 
#define PPI_CHG_CH10_Excluded   (0UL)
 
#define PPI_CHG_CH10_Included   (1UL)
 
#define PPI_CHG_CH9_Pos   (9UL)
 
#define PPI_CHG_CH9_Msk   (0x1UL << PPI_CHG_CH9_Pos)
 
#define PPI_CHG_CH9_Excluded   (0UL)
 
#define PPI_CHG_CH9_Included   (1UL)
 
#define PPI_CHG_CH8_Pos   (8UL)
 
#define PPI_CHG_CH8_Msk   (0x1UL << PPI_CHG_CH8_Pos)
 
#define PPI_CHG_CH8_Excluded   (0UL)
 
#define PPI_CHG_CH8_Included   (1UL)
 
#define PPI_CHG_CH7_Pos   (7UL)
 
#define PPI_CHG_CH7_Msk   (0x1UL << PPI_CHG_CH7_Pos)
 
#define PPI_CHG_CH7_Excluded   (0UL)
 
#define PPI_CHG_CH7_Included   (1UL)
 
#define PPI_CHG_CH6_Pos   (6UL)
 
#define PPI_CHG_CH6_Msk   (0x1UL << PPI_CHG_CH6_Pos)
 
#define PPI_CHG_CH6_Excluded   (0UL)
 
#define PPI_CHG_CH6_Included   (1UL)
 
#define PPI_CHG_CH5_Pos   (5UL)
 
#define PPI_CHG_CH5_Msk   (0x1UL << PPI_CHG_CH5_Pos)
 
#define PPI_CHG_CH5_Excluded   (0UL)
 
#define PPI_CHG_CH5_Included   (1UL)
 
#define PPI_CHG_CH4_Pos   (4UL)
 
#define PPI_CHG_CH4_Msk   (0x1UL << PPI_CHG_CH4_Pos)
 
#define PPI_CHG_CH4_Excluded   (0UL)
 
#define PPI_CHG_CH4_Included   (1UL)
 
#define PPI_CHG_CH3_Pos   (3UL)
 
#define PPI_CHG_CH3_Msk   (0x1UL << PPI_CHG_CH3_Pos)
 
#define PPI_CHG_CH3_Excluded   (0UL)
 
#define PPI_CHG_CH3_Included   (1UL)
 
#define PPI_CHG_CH2_Pos   (2UL)
 
#define PPI_CHG_CH2_Msk   (0x1UL << PPI_CHG_CH2_Pos)
 
#define PPI_CHG_CH2_Excluded   (0UL)
 
#define PPI_CHG_CH2_Included   (1UL)
 
#define PPI_CHG_CH1_Pos   (1UL)
 
#define PPI_CHG_CH1_Msk   (0x1UL << PPI_CHG_CH1_Pos)
 
#define PPI_CHG_CH1_Excluded   (0UL)
 
#define PPI_CHG_CH1_Included   (1UL)
 
#define PPI_CHG_CH0_Pos   (0UL)
 
#define PPI_CHG_CH0_Msk   (0x1UL << PPI_CHG_CH0_Pos)
 
#define PPI_CHG_CH0_Excluded   (0UL)
 
#define PPI_CHG_CH0_Included   (1UL)
 
#define PPI_FORK_TEP_TEP_Pos   (0UL)
 
#define PPI_FORK_TEP_TEP_Msk   (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos)
 
#define PWM_SHORTS_LOOPSDONE_STOP_Pos   (4UL)
 
#define PWM_SHORTS_LOOPSDONE_STOP_Msk   (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos)
 
#define PWM_SHORTS_LOOPSDONE_STOP_Disabled   (0UL)
 
#define PWM_SHORTS_LOOPSDONE_STOP_Enabled   (1UL)
 
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos   (3UL)
 
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk   (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos)
 
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled   (0UL)
 
#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled   (1UL)
 
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos   (2UL)
 
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk   (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos)
 
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled   (0UL)
 
#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled   (1UL)
 
#define PWM_SHORTS_SEQEND1_STOP_Pos   (1UL)
 
#define PWM_SHORTS_SEQEND1_STOP_Msk   (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos)
 
#define PWM_SHORTS_SEQEND1_STOP_Disabled   (0UL)
 
#define PWM_SHORTS_SEQEND1_STOP_Enabled   (1UL)
 
#define PWM_SHORTS_SEQEND0_STOP_Pos   (0UL)
 
#define PWM_SHORTS_SEQEND0_STOP_Msk   (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos)
 
#define PWM_SHORTS_SEQEND0_STOP_Disabled   (0UL)
 
#define PWM_SHORTS_SEQEND0_STOP_Enabled   (1UL)
 
#define PWM_INTEN_LOOPSDONE_Pos   (7UL)
 
#define PWM_INTEN_LOOPSDONE_Msk   (0x1UL << PWM_INTEN_LOOPSDONE_Pos)
 
#define PWM_INTEN_LOOPSDONE_Disabled   (0UL)
 
#define PWM_INTEN_LOOPSDONE_Enabled   (1UL)
 
#define PWM_INTEN_PWMPERIODEND_Pos   (6UL)
 
#define PWM_INTEN_PWMPERIODEND_Msk   (0x1UL << PWM_INTEN_PWMPERIODEND_Pos)
 
#define PWM_INTEN_PWMPERIODEND_Disabled   (0UL)
 
#define PWM_INTEN_PWMPERIODEND_Enabled   (1UL)
 
#define PWM_INTEN_SEQEND1_Pos   (5UL)
 
#define PWM_INTEN_SEQEND1_Msk   (0x1UL << PWM_INTEN_SEQEND1_Pos)
 
#define PWM_INTEN_SEQEND1_Disabled   (0UL)
 
#define PWM_INTEN_SEQEND1_Enabled   (1UL)
 
#define PWM_INTEN_SEQEND0_Pos   (4UL)
 
#define PWM_INTEN_SEQEND0_Msk   (0x1UL << PWM_INTEN_SEQEND0_Pos)
 
#define PWM_INTEN_SEQEND0_Disabled   (0UL)
 
#define PWM_INTEN_SEQEND0_Enabled   (1UL)
 
#define PWM_INTEN_SEQSTARTED1_Pos   (3UL)
 
#define PWM_INTEN_SEQSTARTED1_Msk   (0x1UL << PWM_INTEN_SEQSTARTED1_Pos)
 
#define PWM_INTEN_SEQSTARTED1_Disabled   (0UL)
 
#define PWM_INTEN_SEQSTARTED1_Enabled   (1UL)
 
#define PWM_INTEN_SEQSTARTED0_Pos   (2UL)
 
#define PWM_INTEN_SEQSTARTED0_Msk   (0x1UL << PWM_INTEN_SEQSTARTED0_Pos)
 
#define PWM_INTEN_SEQSTARTED0_Disabled   (0UL)
 
#define PWM_INTEN_SEQSTARTED0_Enabled   (1UL)
 
#define PWM_INTEN_STOPPED_Pos   (1UL)
 
#define PWM_INTEN_STOPPED_Msk   (0x1UL << PWM_INTEN_STOPPED_Pos)
 
#define PWM_INTEN_STOPPED_Disabled   (0UL)
 
#define PWM_INTEN_STOPPED_Enabled   (1UL)
 
#define PWM_INTENSET_LOOPSDONE_Pos   (7UL)
 
#define PWM_INTENSET_LOOPSDONE_Msk   (0x1UL << PWM_INTENSET_LOOPSDONE_Pos)
 
#define PWM_INTENSET_LOOPSDONE_Disabled   (0UL)
 
#define PWM_INTENSET_LOOPSDONE_Enabled   (1UL)
 
#define PWM_INTENSET_LOOPSDONE_Set   (1UL)
 
#define PWM_INTENSET_PWMPERIODEND_Pos   (6UL)
 
#define PWM_INTENSET_PWMPERIODEND_Msk   (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos)
 
#define PWM_INTENSET_PWMPERIODEND_Disabled   (0UL)
 
#define PWM_INTENSET_PWMPERIODEND_Enabled   (1UL)
 
#define PWM_INTENSET_PWMPERIODEND_Set   (1UL)
 
#define PWM_INTENSET_SEQEND1_Pos   (5UL)
 
#define PWM_INTENSET_SEQEND1_Msk   (0x1UL << PWM_INTENSET_SEQEND1_Pos)
 
#define PWM_INTENSET_SEQEND1_Disabled   (0UL)
 
#define PWM_INTENSET_SEQEND1_Enabled   (1UL)
 
#define PWM_INTENSET_SEQEND1_Set   (1UL)
 
#define PWM_INTENSET_SEQEND0_Pos   (4UL)
 
#define PWM_INTENSET_SEQEND0_Msk   (0x1UL << PWM_INTENSET_SEQEND0_Pos)
 
#define PWM_INTENSET_SEQEND0_Disabled   (0UL)
 
#define PWM_INTENSET_SEQEND0_Enabled   (1UL)
 
#define PWM_INTENSET_SEQEND0_Set   (1UL)
 
#define PWM_INTENSET_SEQSTARTED1_Pos   (3UL)
 
#define PWM_INTENSET_SEQSTARTED1_Msk   (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos)
 
#define PWM_INTENSET_SEQSTARTED1_Disabled   (0UL)
 
#define PWM_INTENSET_SEQSTARTED1_Enabled   (1UL)
 
#define PWM_INTENSET_SEQSTARTED1_Set   (1UL)
 
#define PWM_INTENSET_SEQSTARTED0_Pos   (2UL)
 
#define PWM_INTENSET_SEQSTARTED0_Msk   (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos)
 
#define PWM_INTENSET_SEQSTARTED0_Disabled   (0UL)
 
#define PWM_INTENSET_SEQSTARTED0_Enabled   (1UL)
 
#define PWM_INTENSET_SEQSTARTED0_Set   (1UL)
 
#define PWM_INTENSET_STOPPED_Pos   (1UL)
 
#define PWM_INTENSET_STOPPED_Msk   (0x1UL << PWM_INTENSET_STOPPED_Pos)
 
#define PWM_INTENSET_STOPPED_Disabled   (0UL)
 
#define PWM_INTENSET_STOPPED_Enabled   (1UL)
 
#define PWM_INTENSET_STOPPED_Set   (1UL)
 
#define PWM_INTENCLR_LOOPSDONE_Pos   (7UL)
 
#define PWM_INTENCLR_LOOPSDONE_Msk   (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos)
 
#define PWM_INTENCLR_LOOPSDONE_Disabled   (0UL)
 
#define PWM_INTENCLR_LOOPSDONE_Enabled   (1UL)
 
#define PWM_INTENCLR_LOOPSDONE_Clear   (1UL)
 
#define PWM_INTENCLR_PWMPERIODEND_Pos   (6UL)
 
#define PWM_INTENCLR_PWMPERIODEND_Msk   (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos)
 
#define PWM_INTENCLR_PWMPERIODEND_Disabled   (0UL)
 
#define PWM_INTENCLR_PWMPERIODEND_Enabled   (1UL)
 
#define PWM_INTENCLR_PWMPERIODEND_Clear   (1UL)
 
#define PWM_INTENCLR_SEQEND1_Pos   (5UL)
 
#define PWM_INTENCLR_SEQEND1_Msk   (0x1UL << PWM_INTENCLR_SEQEND1_Pos)
 
#define PWM_INTENCLR_SEQEND1_Disabled   (0UL)
 
#define PWM_INTENCLR_SEQEND1_Enabled   (1UL)
 
#define PWM_INTENCLR_SEQEND1_Clear   (1UL)
 
#define PWM_INTENCLR_SEQEND0_Pos   (4UL)
 
#define PWM_INTENCLR_SEQEND0_Msk   (0x1UL << PWM_INTENCLR_SEQEND0_Pos)
 
#define PWM_INTENCLR_SEQEND0_Disabled   (0UL)
 
#define PWM_INTENCLR_SEQEND0_Enabled   (1UL)
 
#define PWM_INTENCLR_SEQEND0_Clear   (1UL)
 
#define PWM_INTENCLR_SEQSTARTED1_Pos   (3UL)
 
#define PWM_INTENCLR_SEQSTARTED1_Msk   (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos)
 
#define PWM_INTENCLR_SEQSTARTED1_Disabled   (0UL)
 
#define PWM_INTENCLR_SEQSTARTED1_Enabled   (1UL)
 
#define PWM_INTENCLR_SEQSTARTED1_Clear   (1UL)
 
#define PWM_INTENCLR_SEQSTARTED0_Pos   (2UL)
 
#define PWM_INTENCLR_SEQSTARTED0_Msk   (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos)
 
#define PWM_INTENCLR_SEQSTARTED0_Disabled   (0UL)
 
#define PWM_INTENCLR_SEQSTARTED0_Enabled   (1UL)
 
#define PWM_INTENCLR_SEQSTARTED0_Clear   (1UL)
 
#define PWM_INTENCLR_STOPPED_Pos   (1UL)
 
#define PWM_INTENCLR_STOPPED_Msk   (0x1UL << PWM_INTENCLR_STOPPED_Pos)
 
#define PWM_INTENCLR_STOPPED_Disabled   (0UL)
 
#define PWM_INTENCLR_STOPPED_Enabled   (1UL)
 
#define PWM_INTENCLR_STOPPED_Clear   (1UL)
 
#define PWM_ENABLE_ENABLE_Pos   (0UL)
 
#define PWM_ENABLE_ENABLE_Msk   (0x1UL << PWM_ENABLE_ENABLE_Pos)
 
#define PWM_ENABLE_ENABLE_Disabled   (0UL)
 
#define PWM_ENABLE_ENABLE_Enabled   (1UL)
 
#define PWM_MODE_UPDOWN_Pos   (0UL)
 
#define PWM_MODE_UPDOWN_Msk   (0x1UL << PWM_MODE_UPDOWN_Pos)
 
#define PWM_MODE_UPDOWN_Up   (0UL)
 
#define PWM_MODE_UPDOWN_UpAndDown   (1UL)
 
#define PWM_COUNTERTOP_COUNTERTOP_Pos   (0UL)
 
#define PWM_COUNTERTOP_COUNTERTOP_Msk   (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos)
 
#define PWM_PRESCALER_PRESCALER_Pos   (0UL)
 
#define PWM_PRESCALER_PRESCALER_Msk   (0x7UL << PWM_PRESCALER_PRESCALER_Pos)
 
#define PWM_PRESCALER_PRESCALER_DIV_1   (0UL)
 
#define PWM_PRESCALER_PRESCALER_DIV_2   (1UL)
 
#define PWM_PRESCALER_PRESCALER_DIV_4   (2UL)
 
#define PWM_PRESCALER_PRESCALER_DIV_8   (3UL)
 
#define PWM_PRESCALER_PRESCALER_DIV_16   (4UL)
 
#define PWM_PRESCALER_PRESCALER_DIV_32   (5UL)
 
#define PWM_PRESCALER_PRESCALER_DIV_64   (6UL)
 
#define PWM_PRESCALER_PRESCALER_DIV_128   (7UL)
 
#define PWM_DECODER_MODE_Pos   (8UL)
 
#define PWM_DECODER_MODE_Msk   (0x1UL << PWM_DECODER_MODE_Pos)
 
#define PWM_DECODER_MODE_RefreshCount   (0UL)
 
#define PWM_DECODER_MODE_NextStep   (1UL)
 
#define PWM_DECODER_LOAD_Pos   (0UL)
 
#define PWM_DECODER_LOAD_Msk   (0x3UL << PWM_DECODER_LOAD_Pos)
 
#define PWM_DECODER_LOAD_Common   (0UL)
 
#define PWM_DECODER_LOAD_Grouped   (1UL)
 
#define PWM_DECODER_LOAD_Individual   (2UL)
 
#define PWM_DECODER_LOAD_WaveForm   (3UL)
 
#define PWM_LOOP_CNT_Pos   (0UL)
 
#define PWM_LOOP_CNT_Msk   (0xFFFFUL << PWM_LOOP_CNT_Pos)
 
#define PWM_LOOP_CNT_Disabled   (0UL)
 
#define PWM_SEQ_PTR_PTR_Pos   (0UL)
 
#define PWM_SEQ_PTR_PTR_Msk   (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos)
 
#define PWM_SEQ_CNT_CNT_Pos   (0UL)
 
#define PWM_SEQ_CNT_CNT_Msk   (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos)
 
#define PWM_SEQ_CNT_CNT_Disabled   (0UL)
 
#define PWM_SEQ_REFRESH_CNT_Pos   (0UL)
 
#define PWM_SEQ_REFRESH_CNT_Msk   (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos)
 
#define PWM_SEQ_REFRESH_CNT_Continuous   (0UL)
 
#define PWM_SEQ_ENDDELAY_CNT_Pos   (0UL)
 
#define PWM_SEQ_ENDDELAY_CNT_Msk   (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos)
 
#define PWM_PSEL_OUT_CONNECT_Pos   (31UL)
 
#define PWM_PSEL_OUT_CONNECT_Msk   (0x1UL << PWM_PSEL_OUT_CONNECT_Pos)
 
#define PWM_PSEL_OUT_CONNECT_Connected   (0UL)
 
#define PWM_PSEL_OUT_CONNECT_Disconnected   (1UL)
 
#define PWM_PSEL_OUT_PIN_Pos   (0UL)
 
#define PWM_PSEL_OUT_PIN_Msk   (0x1FUL << PWM_PSEL_OUT_PIN_Pos)
 
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos   (6UL)
 
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk   (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos)
 
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled   (0UL)
 
#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled   (1UL)
 
#define QDEC_SHORTS_DBLRDY_STOP_Pos   (5UL)
 
#define QDEC_SHORTS_DBLRDY_STOP_Msk   (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos)
 
#define QDEC_SHORTS_DBLRDY_STOP_Disabled   (0UL)
 
#define QDEC_SHORTS_DBLRDY_STOP_Enabled   (1UL)
 
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos   (4UL)
 
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk   (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos)
 
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled   (0UL)
 
#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled   (1UL)
 
#define QDEC_SHORTS_REPORTRDY_STOP_Pos   (3UL)
 
#define QDEC_SHORTS_REPORTRDY_STOP_Msk   (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos)
 
#define QDEC_SHORTS_REPORTRDY_STOP_Disabled   (0UL)
 
#define QDEC_SHORTS_REPORTRDY_STOP_Enabled   (1UL)
 
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos   (2UL)
 
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk   (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos)
 
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled   (0UL)
 
#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled   (1UL)
 
#define QDEC_SHORTS_SAMPLERDY_STOP_Pos   (1UL)
 
#define QDEC_SHORTS_SAMPLERDY_STOP_Msk   (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos)
 
#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled   (0UL)
 
#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled   (1UL)
 
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos   (0UL)
 
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk   (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos)
 
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled   (0UL)
 
#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled   (1UL)
 
#define QDEC_INTENSET_STOPPED_Pos   (4UL)
 
#define QDEC_INTENSET_STOPPED_Msk   (0x1UL << QDEC_INTENSET_STOPPED_Pos)
 
#define QDEC_INTENSET_STOPPED_Disabled   (0UL)
 
#define QDEC_INTENSET_STOPPED_Enabled   (1UL)
 
#define QDEC_INTENSET_STOPPED_Set   (1UL)
 
#define QDEC_INTENSET_DBLRDY_Pos   (3UL)
 
#define QDEC_INTENSET_DBLRDY_Msk   (0x1UL << QDEC_INTENSET_DBLRDY_Pos)
 
#define QDEC_INTENSET_DBLRDY_Disabled   (0UL)
 
#define QDEC_INTENSET_DBLRDY_Enabled   (1UL)
 
#define QDEC_INTENSET_DBLRDY_Set   (1UL)
 
#define QDEC_INTENSET_ACCOF_Pos   (2UL)
 
#define QDEC_INTENSET_ACCOF_Msk   (0x1UL << QDEC_INTENSET_ACCOF_Pos)
 
#define QDEC_INTENSET_ACCOF_Disabled   (0UL)
 
#define QDEC_INTENSET_ACCOF_Enabled   (1UL)
 
#define QDEC_INTENSET_ACCOF_Set   (1UL)
 
#define QDEC_INTENSET_REPORTRDY_Pos   (1UL)
 
#define QDEC_INTENSET_REPORTRDY_Msk   (0x1UL << QDEC_INTENSET_REPORTRDY_Pos)
 
#define QDEC_INTENSET_REPORTRDY_Disabled   (0UL)
 
#define QDEC_INTENSET_REPORTRDY_Enabled   (1UL)
 
#define QDEC_INTENSET_REPORTRDY_Set   (1UL)
 
#define QDEC_INTENSET_SAMPLERDY_Pos   (0UL)
 
#define QDEC_INTENSET_SAMPLERDY_Msk   (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos)
 
#define QDEC_INTENSET_SAMPLERDY_Disabled   (0UL)
 
#define QDEC_INTENSET_SAMPLERDY_Enabled   (1UL)
 
#define QDEC_INTENSET_SAMPLERDY_Set   (1UL)
 
#define QDEC_INTENCLR_STOPPED_Pos   (4UL)
 
#define QDEC_INTENCLR_STOPPED_Msk   (0x1UL << QDEC_INTENCLR_STOPPED_Pos)
 
#define QDEC_INTENCLR_STOPPED_Disabled   (0UL)
 
#define QDEC_INTENCLR_STOPPED_Enabled   (1UL)
 
#define QDEC_INTENCLR_STOPPED_Clear   (1UL)
 
#define QDEC_INTENCLR_DBLRDY_Pos   (3UL)
 
#define QDEC_INTENCLR_DBLRDY_Msk   (0x1UL << QDEC_INTENCLR_DBLRDY_Pos)
 
#define QDEC_INTENCLR_DBLRDY_Disabled   (0UL)
 
#define QDEC_INTENCLR_DBLRDY_Enabled   (1UL)
 
#define QDEC_INTENCLR_DBLRDY_Clear   (1UL)
 
#define QDEC_INTENCLR_ACCOF_Pos   (2UL)
 
#define QDEC_INTENCLR_ACCOF_Msk   (0x1UL << QDEC_INTENCLR_ACCOF_Pos)
 
#define QDEC_INTENCLR_ACCOF_Disabled   (0UL)
 
#define QDEC_INTENCLR_ACCOF_Enabled   (1UL)
 
#define QDEC_INTENCLR_ACCOF_Clear   (1UL)
 
#define QDEC_INTENCLR_REPORTRDY_Pos   (1UL)
 
#define QDEC_INTENCLR_REPORTRDY_Msk   (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos)
 
#define QDEC_INTENCLR_REPORTRDY_Disabled   (0UL)
 
#define QDEC_INTENCLR_REPORTRDY_Enabled   (1UL)
 
#define QDEC_INTENCLR_REPORTRDY_Clear   (1UL)
 
#define QDEC_INTENCLR_SAMPLERDY_Pos   (0UL)
 
#define QDEC_INTENCLR_SAMPLERDY_Msk   (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos)
 
#define QDEC_INTENCLR_SAMPLERDY_Disabled   (0UL)
 
#define QDEC_INTENCLR_SAMPLERDY_Enabled   (1UL)
 
#define QDEC_INTENCLR_SAMPLERDY_Clear   (1UL)
 
#define QDEC_ENABLE_ENABLE_Pos   (0UL)
 
#define QDEC_ENABLE_ENABLE_Msk   (0x1UL << QDEC_ENABLE_ENABLE_Pos)
 
#define QDEC_ENABLE_ENABLE_Disabled   (0UL)
 
#define QDEC_ENABLE_ENABLE_Enabled   (1UL)
 
#define QDEC_LEDPOL_LEDPOL_Pos   (0UL)
 
#define QDEC_LEDPOL_LEDPOL_Msk   (0x1UL << QDEC_LEDPOL_LEDPOL_Pos)
 
#define QDEC_LEDPOL_LEDPOL_ActiveLow   (0UL)
 
#define QDEC_LEDPOL_LEDPOL_ActiveHigh   (1UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_Pos   (0UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_Msk   (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos)
 
#define QDEC_SAMPLEPER_SAMPLEPER_128us   (0UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_256us   (1UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_512us   (2UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_1024us   (3UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_2048us   (4UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_4096us   (5UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_8192us   (6UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_16384us   (7UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_32ms   (8UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_65ms   (9UL)
 
#define QDEC_SAMPLEPER_SAMPLEPER_131ms   (10UL)
 
#define QDEC_SAMPLE_SAMPLE_Pos   (0UL)
 
#define QDEC_SAMPLE_SAMPLE_Msk   (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos)
 
#define QDEC_REPORTPER_REPORTPER_Pos   (0UL)
 
#define QDEC_REPORTPER_REPORTPER_Msk   (0xFUL << QDEC_REPORTPER_REPORTPER_Pos)
 
#define QDEC_REPORTPER_REPORTPER_10Smpl   (0UL)
 
#define QDEC_REPORTPER_REPORTPER_40Smpl   (1UL)
 
#define QDEC_REPORTPER_REPORTPER_80Smpl   (2UL)
 
#define QDEC_REPORTPER_REPORTPER_120Smpl   (3UL)
 
#define QDEC_REPORTPER_REPORTPER_160Smpl   (4UL)
 
#define QDEC_REPORTPER_REPORTPER_200Smpl   (5UL)
 
#define QDEC_REPORTPER_REPORTPER_240Smpl   (6UL)
 
#define QDEC_REPORTPER_REPORTPER_280Smpl   (7UL)
 
#define QDEC_REPORTPER_REPORTPER_1Smpl   (8UL)
 
#define QDEC_ACC_ACC_Pos   (0UL)
 
#define QDEC_ACC_ACC_Msk   (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos)
 
#define QDEC_ACCREAD_ACCREAD_Pos   (0UL)
 
#define QDEC_ACCREAD_ACCREAD_Msk   (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos)
 
#define QDEC_PSEL_LED_CONNECT_Pos   (31UL)
 
#define QDEC_PSEL_LED_CONNECT_Msk   (0x1UL << QDEC_PSEL_LED_CONNECT_Pos)
 
#define QDEC_PSEL_LED_CONNECT_Connected   (0UL)
 
#define QDEC_PSEL_LED_CONNECT_Disconnected   (1UL)
 
#define QDEC_PSEL_LED_PIN_Pos   (0UL)
 
#define QDEC_PSEL_LED_PIN_Msk   (0x1FUL << QDEC_PSEL_LED_PIN_Pos)
 
#define QDEC_PSEL_A_CONNECT_Pos   (31UL)
 
#define QDEC_PSEL_A_CONNECT_Msk   (0x1UL << QDEC_PSEL_A_CONNECT_Pos)
 
#define QDEC_PSEL_A_CONNECT_Connected   (0UL)
 
#define QDEC_PSEL_A_CONNECT_Disconnected   (1UL)
 
#define QDEC_PSEL_A_PIN_Pos   (0UL)
 
#define QDEC_PSEL_A_PIN_Msk   (0x1FUL << QDEC_PSEL_A_PIN_Pos)
 
#define QDEC_PSEL_B_CONNECT_Pos   (31UL)
 
#define QDEC_PSEL_B_CONNECT_Msk   (0x1UL << QDEC_PSEL_B_CONNECT_Pos)
 
#define QDEC_PSEL_B_CONNECT_Connected   (0UL)
 
#define QDEC_PSEL_B_CONNECT_Disconnected   (1UL)
 
#define QDEC_PSEL_B_PIN_Pos   (0UL)
 
#define QDEC_PSEL_B_PIN_Msk   (0x1FUL << QDEC_PSEL_B_PIN_Pos)
 
#define QDEC_DBFEN_DBFEN_Pos   (0UL)
 
#define QDEC_DBFEN_DBFEN_Msk   (0x1UL << QDEC_DBFEN_DBFEN_Pos)
 
#define QDEC_DBFEN_DBFEN_Disabled   (0UL)
 
#define QDEC_DBFEN_DBFEN_Enabled   (1UL)
 
#define QDEC_LEDPRE_LEDPRE_Pos   (0UL)
 
#define QDEC_LEDPRE_LEDPRE_Msk   (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos)
 
#define QDEC_ACCDBL_ACCDBL_Pos   (0UL)
 
#define QDEC_ACCDBL_ACCDBL_Msk   (0xFUL << QDEC_ACCDBL_ACCDBL_Pos)
 
#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos   (0UL)
 
#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk   (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos)
 
#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos   (8UL)
 
#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk   (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos)
 
#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled   (0UL)
 
#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled   (1UL)
 
#define RADIO_SHORTS_ADDRESS_BCSTART_Pos   (6UL)
 
#define RADIO_SHORTS_ADDRESS_BCSTART_Msk   (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos)
 
#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled   (0UL)
 
#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled   (1UL)
 
#define RADIO_SHORTS_END_START_Pos   (5UL)
 
#define RADIO_SHORTS_END_START_Msk   (0x1UL << RADIO_SHORTS_END_START_Pos)
 
#define RADIO_SHORTS_END_START_Disabled   (0UL)
 
#define RADIO_SHORTS_END_START_Enabled   (1UL)
 
#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos   (4UL)
 
#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk   (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos)
 
#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled   (0UL)
 
#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled   (1UL)
 
#define RADIO_SHORTS_DISABLED_RXEN_Pos   (3UL)
 
#define RADIO_SHORTS_DISABLED_RXEN_Msk   (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos)
 
#define RADIO_SHORTS_DISABLED_RXEN_Disabled   (0UL)
 
#define RADIO_SHORTS_DISABLED_RXEN_Enabled   (1UL)
 
#define RADIO_SHORTS_DISABLED_TXEN_Pos   (2UL)
 
#define RADIO_SHORTS_DISABLED_TXEN_Msk   (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos)
 
#define RADIO_SHORTS_DISABLED_TXEN_Disabled   (0UL)
 
#define RADIO_SHORTS_DISABLED_TXEN_Enabled   (1UL)
 
#define RADIO_SHORTS_END_DISABLE_Pos   (1UL)
 
#define RADIO_SHORTS_END_DISABLE_Msk   (0x1UL << RADIO_SHORTS_END_DISABLE_Pos)
 
#define RADIO_SHORTS_END_DISABLE_Disabled   (0UL)
 
#define RADIO_SHORTS_END_DISABLE_Enabled   (1UL)
 
#define RADIO_SHORTS_READY_START_Pos   (0UL)
 
#define RADIO_SHORTS_READY_START_Msk   (0x1UL << RADIO_SHORTS_READY_START_Pos)
 
#define RADIO_SHORTS_READY_START_Disabled   (0UL)
 
#define RADIO_SHORTS_READY_START_Enabled   (1UL)
 
#define RADIO_INTENSET_CRCERROR_Pos   (13UL)
 
#define RADIO_INTENSET_CRCERROR_Msk   (0x1UL << RADIO_INTENSET_CRCERROR_Pos)
 
#define RADIO_INTENSET_CRCERROR_Disabled   (0UL)
 
#define RADIO_INTENSET_CRCERROR_Enabled   (1UL)
 
#define RADIO_INTENSET_CRCERROR_Set   (1UL)
 
#define RADIO_INTENSET_CRCOK_Pos   (12UL)
 
#define RADIO_INTENSET_CRCOK_Msk   (0x1UL << RADIO_INTENSET_CRCOK_Pos)
 
#define RADIO_INTENSET_CRCOK_Disabled   (0UL)
 
#define RADIO_INTENSET_CRCOK_Enabled   (1UL)
 
#define RADIO_INTENSET_CRCOK_Set   (1UL)
 
#define RADIO_INTENSET_BCMATCH_Pos   (10UL)
 
#define RADIO_INTENSET_BCMATCH_Msk   (0x1UL << RADIO_INTENSET_BCMATCH_Pos)
 
#define RADIO_INTENSET_BCMATCH_Disabled   (0UL)
 
#define RADIO_INTENSET_BCMATCH_Enabled   (1UL)
 
#define RADIO_INTENSET_BCMATCH_Set   (1UL)
 
#define RADIO_INTENSET_RSSIEND_Pos   (7UL)
 
#define RADIO_INTENSET_RSSIEND_Msk   (0x1UL << RADIO_INTENSET_RSSIEND_Pos)
 
#define RADIO_INTENSET_RSSIEND_Disabled   (0UL)
 
#define RADIO_INTENSET_RSSIEND_Enabled   (1UL)
 
#define RADIO_INTENSET_RSSIEND_Set   (1UL)
 
#define RADIO_INTENSET_DEVMISS_Pos   (6UL)
 
#define RADIO_INTENSET_DEVMISS_Msk   (0x1UL << RADIO_INTENSET_DEVMISS_Pos)
 
#define RADIO_INTENSET_DEVMISS_Disabled   (0UL)
 
#define RADIO_INTENSET_DEVMISS_Enabled   (1UL)
 
#define RADIO_INTENSET_DEVMISS_Set   (1UL)
 
#define RADIO_INTENSET_DEVMATCH_Pos   (5UL)
 
#define RADIO_INTENSET_DEVMATCH_Msk   (0x1UL << RADIO_INTENSET_DEVMATCH_Pos)
 
#define RADIO_INTENSET_DEVMATCH_Disabled   (0UL)
 
#define RADIO_INTENSET_DEVMATCH_Enabled   (1UL)
 
#define RADIO_INTENSET_DEVMATCH_Set   (1UL)
 
#define RADIO_INTENSET_DISABLED_Pos   (4UL)
 
#define RADIO_INTENSET_DISABLED_Msk   (0x1UL << RADIO_INTENSET_DISABLED_Pos)
 
#define RADIO_INTENSET_DISABLED_Disabled   (0UL)
 
#define RADIO_INTENSET_DISABLED_Enabled   (1UL)
 
#define RADIO_INTENSET_DISABLED_Set   (1UL)
 
#define RADIO_INTENSET_END_Pos   (3UL)
 
#define RADIO_INTENSET_END_Msk   (0x1UL << RADIO_INTENSET_END_Pos)
 
#define RADIO_INTENSET_END_Disabled   (0UL)
 
#define RADIO_INTENSET_END_Enabled   (1UL)
 
#define RADIO_INTENSET_END_Set   (1UL)
 
#define RADIO_INTENSET_PAYLOAD_Pos   (2UL)
 
#define RADIO_INTENSET_PAYLOAD_Msk   (0x1UL << RADIO_INTENSET_PAYLOAD_Pos)
 
#define RADIO_INTENSET_PAYLOAD_Disabled   (0UL)
 
#define RADIO_INTENSET_PAYLOAD_Enabled   (1UL)
 
#define RADIO_INTENSET_PAYLOAD_Set   (1UL)
 
#define RADIO_INTENSET_ADDRESS_Pos   (1UL)
 
#define RADIO_INTENSET_ADDRESS_Msk   (0x1UL << RADIO_INTENSET_ADDRESS_Pos)
 
#define RADIO_INTENSET_ADDRESS_Disabled   (0UL)
 
#define RADIO_INTENSET_ADDRESS_Enabled   (1UL)
 
#define RADIO_INTENSET_ADDRESS_Set   (1UL)
 
#define RADIO_INTENSET_READY_Pos   (0UL)
 
#define RADIO_INTENSET_READY_Msk   (0x1UL << RADIO_INTENSET_READY_Pos)
 
#define RADIO_INTENSET_READY_Disabled   (0UL)
 
#define RADIO_INTENSET_READY_Enabled   (1UL)
 
#define RADIO_INTENSET_READY_Set   (1UL)
 
#define RADIO_INTENCLR_CRCERROR_Pos   (13UL)
 
#define RADIO_INTENCLR_CRCERROR_Msk   (0x1UL << RADIO_INTENCLR_CRCERROR_Pos)
 
#define RADIO_INTENCLR_CRCERROR_Disabled   (0UL)
 
#define RADIO_INTENCLR_CRCERROR_Enabled   (1UL)
 
#define RADIO_INTENCLR_CRCERROR_Clear   (1UL)
 
#define RADIO_INTENCLR_CRCOK_Pos   (12UL)
 
#define RADIO_INTENCLR_CRCOK_Msk   (0x1UL << RADIO_INTENCLR_CRCOK_Pos)
 
#define RADIO_INTENCLR_CRCOK_Disabled   (0UL)
 
#define RADIO_INTENCLR_CRCOK_Enabled   (1UL)
 
#define RADIO_INTENCLR_CRCOK_Clear   (1UL)
 
#define RADIO_INTENCLR_BCMATCH_Pos   (10UL)
 
#define RADIO_INTENCLR_BCMATCH_Msk   (0x1UL << RADIO_INTENCLR_BCMATCH_Pos)
 
#define RADIO_INTENCLR_BCMATCH_Disabled   (0UL)
 
#define RADIO_INTENCLR_BCMATCH_Enabled   (1UL)
 
#define RADIO_INTENCLR_BCMATCH_Clear   (1UL)
 
#define RADIO_INTENCLR_RSSIEND_Pos   (7UL)
 
#define RADIO_INTENCLR_RSSIEND_Msk   (0x1UL << RADIO_INTENCLR_RSSIEND_Pos)
 
#define RADIO_INTENCLR_RSSIEND_Disabled   (0UL)
 
#define RADIO_INTENCLR_RSSIEND_Enabled   (1UL)
 
#define RADIO_INTENCLR_RSSIEND_Clear   (1UL)
 
#define RADIO_INTENCLR_DEVMISS_Pos   (6UL)
 
#define RADIO_INTENCLR_DEVMISS_Msk   (0x1UL << RADIO_INTENCLR_DEVMISS_Pos)
 
#define RADIO_INTENCLR_DEVMISS_Disabled   (0UL)
 
#define RADIO_INTENCLR_DEVMISS_Enabled   (1UL)
 
#define RADIO_INTENCLR_DEVMISS_Clear   (1UL)
 
#define RADIO_INTENCLR_DEVMATCH_Pos   (5UL)
 
#define RADIO_INTENCLR_DEVMATCH_Msk   (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos)
 
#define RADIO_INTENCLR_DEVMATCH_Disabled   (0UL)
 
#define RADIO_INTENCLR_DEVMATCH_Enabled   (1UL)
 
#define RADIO_INTENCLR_DEVMATCH_Clear   (1UL)
 
#define RADIO_INTENCLR_DISABLED_Pos   (4UL)
 
#define RADIO_INTENCLR_DISABLED_Msk   (0x1UL << RADIO_INTENCLR_DISABLED_Pos)
 
#define RADIO_INTENCLR_DISABLED_Disabled   (0UL)
 
#define RADIO_INTENCLR_DISABLED_Enabled   (1UL)
 
#define RADIO_INTENCLR_DISABLED_Clear   (1UL)
 
#define RADIO_INTENCLR_END_Pos   (3UL)
 
#define RADIO_INTENCLR_END_Msk   (0x1UL << RADIO_INTENCLR_END_Pos)
 
#define RADIO_INTENCLR_END_Disabled   (0UL)
 
#define RADIO_INTENCLR_END_Enabled   (1UL)
 
#define RADIO_INTENCLR_END_Clear   (1UL)
 
#define RADIO_INTENCLR_PAYLOAD_Pos   (2UL)
 
#define RADIO_INTENCLR_PAYLOAD_Msk   (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos)
 
#define RADIO_INTENCLR_PAYLOAD_Disabled   (0UL)
 
#define RADIO_INTENCLR_PAYLOAD_Enabled   (1UL)
 
#define RADIO_INTENCLR_PAYLOAD_Clear   (1UL)
 
#define RADIO_INTENCLR_ADDRESS_Pos   (1UL)
 
#define RADIO_INTENCLR_ADDRESS_Msk   (0x1UL << RADIO_INTENCLR_ADDRESS_Pos)
 
#define RADIO_INTENCLR_ADDRESS_Disabled   (0UL)
 
#define RADIO_INTENCLR_ADDRESS_Enabled   (1UL)
 
#define RADIO_INTENCLR_ADDRESS_Clear   (1UL)
 
#define RADIO_INTENCLR_READY_Pos   (0UL)
 
#define RADIO_INTENCLR_READY_Msk   (0x1UL << RADIO_INTENCLR_READY_Pos)
 
#define RADIO_INTENCLR_READY_Disabled   (0UL)
 
#define RADIO_INTENCLR_READY_Enabled   (1UL)
 
#define RADIO_INTENCLR_READY_Clear   (1UL)
 
#define RADIO_CRCSTATUS_CRCSTATUS_Pos   (0UL)
 
#define RADIO_CRCSTATUS_CRCSTATUS_Msk   (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos)
 
#define RADIO_CRCSTATUS_CRCSTATUS_CRCError   (0UL)
 
#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk   (1UL)
 
#define RADIO_RXMATCH_RXMATCH_Pos   (0UL)
 
#define RADIO_RXMATCH_RXMATCH_Msk   (0x7UL << RADIO_RXMATCH_RXMATCH_Pos)
 
#define RADIO_RXCRC_RXCRC_Pos   (0UL)
 
#define RADIO_RXCRC_RXCRC_Msk   (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos)
 
#define RADIO_DAI_DAI_Pos   (0UL)
 
#define RADIO_DAI_DAI_Msk   (0x7UL << RADIO_DAI_DAI_Pos)
 
#define RADIO_PACKETPTR_PACKETPTR_Pos   (0UL)
 
#define RADIO_PACKETPTR_PACKETPTR_Msk   (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos)
 
#define RADIO_FREQUENCY_MAP_Pos   (8UL)
 
#define RADIO_FREQUENCY_MAP_Msk   (0x1UL << RADIO_FREQUENCY_MAP_Pos)
 
#define RADIO_FREQUENCY_MAP_Default   (0UL)
 
#define RADIO_FREQUENCY_MAP_Low   (1UL)
 
#define RADIO_FREQUENCY_FREQUENCY_Pos   (0UL)
 
#define RADIO_FREQUENCY_FREQUENCY_Msk   (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos)
 
#define RADIO_TXPOWER_TXPOWER_Pos   (0UL)
 
#define RADIO_TXPOWER_TXPOWER_Msk   (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos)
 
#define RADIO_TXPOWER_TXPOWER_0dBm   (0x00UL)
 
#define RADIO_TXPOWER_TXPOWER_Pos3dBm   (0x03UL)
 
#define RADIO_TXPOWER_TXPOWER_Pos4dBm   (0x04UL)
 
#define RADIO_TXPOWER_TXPOWER_Neg40dBm   (0xD8UL)
 
#define RADIO_TXPOWER_TXPOWER_Neg20dBm   (0xECUL)
 
#define RADIO_TXPOWER_TXPOWER_Neg16dBm   (0xF0UL)
 
#define RADIO_TXPOWER_TXPOWER_Neg12dBm   (0xF4UL)
 
#define RADIO_TXPOWER_TXPOWER_Neg8dBm   (0xF8UL)
 
#define RADIO_TXPOWER_TXPOWER_Neg4dBm   (0xFCUL)
 
#define RADIO_TXPOWER_TXPOWER_Neg30dBm   (0xFFUL)
 
#define RADIO_MODE_MODE_Pos   (0UL)
 
#define RADIO_MODE_MODE_Msk   (0xFUL << RADIO_MODE_MODE_Pos)
 
#define RADIO_MODE_MODE_Nrf_1Mbit   (0UL)
 
#define RADIO_MODE_MODE_Nrf_2Mbit   (1UL)
 
#define RADIO_MODE_MODE_Nrf_250Kbit   (2UL)
 
#define RADIO_MODE_MODE_Ble_1Mbit   (3UL)
 
#define RADIO_MODE_MODE_Ble_2Mbit   (4UL)
 
#define RADIO_PCNF0_PLEN_Pos   (24UL)
 
#define RADIO_PCNF0_PLEN_Msk   (0x1UL << RADIO_PCNF0_PLEN_Pos)
 
#define RADIO_PCNF0_PLEN_8bit   (0UL)
 
#define RADIO_PCNF0_PLEN_16bit   (1UL)
 
#define RADIO_PCNF0_S1INCL_Pos   (20UL)
 
#define RADIO_PCNF0_S1INCL_Msk   (0x1UL << RADIO_PCNF0_S1INCL_Pos)
 
#define RADIO_PCNF0_S1INCL_Automatic   (0UL)
 
#define RADIO_PCNF0_S1INCL_Include   (1UL)
 
#define RADIO_PCNF0_S1LEN_Pos   (16UL)
 
#define RADIO_PCNF0_S1LEN_Msk   (0xFUL << RADIO_PCNF0_S1LEN_Pos)
 
#define RADIO_PCNF0_S0LEN_Pos   (8UL)
 
#define RADIO_PCNF0_S0LEN_Msk   (0x1UL << RADIO_PCNF0_S0LEN_Pos)
 
#define RADIO_PCNF0_LFLEN_Pos   (0UL)
 
#define RADIO_PCNF0_LFLEN_Msk   (0xFUL << RADIO_PCNF0_LFLEN_Pos)
 
#define RADIO_PCNF1_WHITEEN_Pos   (25UL)
 
#define RADIO_PCNF1_WHITEEN_Msk   (0x1UL << RADIO_PCNF1_WHITEEN_Pos)
 
#define RADIO_PCNF1_WHITEEN_Disabled   (0UL)
 
#define RADIO_PCNF1_WHITEEN_Enabled   (1UL)
 
#define RADIO_PCNF1_ENDIAN_Pos   (24UL)
 
#define RADIO_PCNF1_ENDIAN_Msk   (0x1UL << RADIO_PCNF1_ENDIAN_Pos)
 
#define RADIO_PCNF1_ENDIAN_Little   (0UL)
 
#define RADIO_PCNF1_ENDIAN_Big   (1UL)
 
#define RADIO_PCNF1_BALEN_Pos   (16UL)
 
#define RADIO_PCNF1_BALEN_Msk   (0x7UL << RADIO_PCNF1_BALEN_Pos)
 
#define RADIO_PCNF1_STATLEN_Pos   (8UL)
 
#define RADIO_PCNF1_STATLEN_Msk   (0xFFUL << RADIO_PCNF1_STATLEN_Pos)
 
#define RADIO_PCNF1_MAXLEN_Pos   (0UL)
 
#define RADIO_PCNF1_MAXLEN_Msk   (0xFFUL << RADIO_PCNF1_MAXLEN_Pos)
 
#define RADIO_BASE0_BASE0_Pos   (0UL)
 
#define RADIO_BASE0_BASE0_Msk   (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos)
 
#define RADIO_BASE1_BASE1_Pos   (0UL)
 
#define RADIO_BASE1_BASE1_Msk   (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos)
 
#define RADIO_PREFIX0_AP3_Pos   (24UL)
 
#define RADIO_PREFIX0_AP3_Msk   (0xFFUL << RADIO_PREFIX0_AP3_Pos)
 
#define RADIO_PREFIX0_AP2_Pos   (16UL)
 
#define RADIO_PREFIX0_AP2_Msk   (0xFFUL << RADIO_PREFIX0_AP2_Pos)
 
#define RADIO_PREFIX0_AP1_Pos   (8UL)
 
#define RADIO_PREFIX0_AP1_Msk   (0xFFUL << RADIO_PREFIX0_AP1_Pos)
 
#define RADIO_PREFIX0_AP0_Pos   (0UL)
 
#define RADIO_PREFIX0_AP0_Msk   (0xFFUL << RADIO_PREFIX0_AP0_Pos)
 
#define RADIO_PREFIX1_AP7_Pos   (24UL)
 
#define RADIO_PREFIX1_AP7_Msk   (0xFFUL << RADIO_PREFIX1_AP7_Pos)
 
#define RADIO_PREFIX1_AP6_Pos   (16UL)
 
#define RADIO_PREFIX1_AP6_Msk   (0xFFUL << RADIO_PREFIX1_AP6_Pos)
 
#define RADIO_PREFIX1_AP5_Pos   (8UL)
 
#define RADIO_PREFIX1_AP5_Msk   (0xFFUL << RADIO_PREFIX1_AP5_Pos)
 
#define RADIO_PREFIX1_AP4_Pos   (0UL)
 
#define RADIO_PREFIX1_AP4_Msk   (0xFFUL << RADIO_PREFIX1_AP4_Pos)
 
#define RADIO_TXADDRESS_TXADDRESS_Pos   (0UL)
 
#define RADIO_TXADDRESS_TXADDRESS_Msk   (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos)
 
#define RADIO_RXADDRESSES_ADDR7_Pos   (7UL)
 
#define RADIO_RXADDRESSES_ADDR7_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos)
 
#define RADIO_RXADDRESSES_ADDR7_Disabled   (0UL)
 
#define RADIO_RXADDRESSES_ADDR7_Enabled   (1UL)
 
#define RADIO_RXADDRESSES_ADDR6_Pos   (6UL)
 
#define RADIO_RXADDRESSES_ADDR6_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos)
 
#define RADIO_RXADDRESSES_ADDR6_Disabled   (0UL)
 
#define RADIO_RXADDRESSES_ADDR6_Enabled   (1UL)
 
#define RADIO_RXADDRESSES_ADDR5_Pos   (5UL)
 
#define RADIO_RXADDRESSES_ADDR5_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos)
 
#define RADIO_RXADDRESSES_ADDR5_Disabled   (0UL)
 
#define RADIO_RXADDRESSES_ADDR5_Enabled   (1UL)
 
#define RADIO_RXADDRESSES_ADDR4_Pos   (4UL)
 
#define RADIO_RXADDRESSES_ADDR4_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos)
 
#define RADIO_RXADDRESSES_ADDR4_Disabled   (0UL)
 
#define RADIO_RXADDRESSES_ADDR4_Enabled   (1UL)
 
#define RADIO_RXADDRESSES_ADDR3_Pos   (3UL)
 
#define RADIO_RXADDRESSES_ADDR3_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos)
 
#define RADIO_RXADDRESSES_ADDR3_Disabled   (0UL)
 
#define RADIO_RXADDRESSES_ADDR3_Enabled   (1UL)
 
#define RADIO_RXADDRESSES_ADDR2_Pos   (2UL)
 
#define RADIO_RXADDRESSES_ADDR2_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos)
 
#define RADIO_RXADDRESSES_ADDR2_Disabled   (0UL)
 
#define RADIO_RXADDRESSES_ADDR2_Enabled   (1UL)
 
#define RADIO_RXADDRESSES_ADDR1_Pos   (1UL)
 
#define RADIO_RXADDRESSES_ADDR1_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos)
 
#define RADIO_RXADDRESSES_ADDR1_Disabled   (0UL)
 
#define RADIO_RXADDRESSES_ADDR1_Enabled   (1UL)
 
#define RADIO_RXADDRESSES_ADDR0_Pos   (0UL)
 
#define RADIO_RXADDRESSES_ADDR0_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos)
 
#define RADIO_RXADDRESSES_ADDR0_Disabled   (0UL)
 
#define RADIO_RXADDRESSES_ADDR0_Enabled   (1UL)
 
#define RADIO_CRCCNF_SKIPADDR_Pos   (8UL)
 
#define RADIO_CRCCNF_SKIPADDR_Msk   (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos)
 
#define RADIO_CRCCNF_SKIPADDR_Include   (0UL)
 
#define RADIO_CRCCNF_SKIPADDR_Skip   (1UL)
 
#define RADIO_CRCCNF_LEN_Pos   (0UL)
 
#define RADIO_CRCCNF_LEN_Msk   (0x3UL << RADIO_CRCCNF_LEN_Pos)
 
#define RADIO_CRCCNF_LEN_Disabled   (0UL)
 
#define RADIO_CRCCNF_LEN_One   (1UL)
 
#define RADIO_CRCCNF_LEN_Two   (2UL)
 
#define RADIO_CRCCNF_LEN_Three   (3UL)
 
#define RADIO_CRCPOLY_CRCPOLY_Pos   (0UL)
 
#define RADIO_CRCPOLY_CRCPOLY_Msk   (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos)
 
#define RADIO_CRCINIT_CRCINIT_Pos   (0UL)
 
#define RADIO_CRCINIT_CRCINIT_Msk   (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos)
 
#define RADIO_TIFS_TIFS_Pos   (0UL)
 
#define RADIO_TIFS_TIFS_Msk   (0xFFUL << RADIO_TIFS_TIFS_Pos)
 
#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos   (0UL)
 
#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk   (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos)
 
#define RADIO_STATE_STATE_Pos   (0UL)
 
#define RADIO_STATE_STATE_Msk   (0xFUL << RADIO_STATE_STATE_Pos)
 
#define RADIO_STATE_STATE_Disabled   (0UL)
 
#define RADIO_STATE_STATE_RxRu   (1UL)
 
#define RADIO_STATE_STATE_RxIdle   (2UL)
 
#define RADIO_STATE_STATE_Rx   (3UL)
 
#define RADIO_STATE_STATE_RxDisable   (4UL)
 
#define RADIO_STATE_STATE_TxRu   (9UL)
 
#define RADIO_STATE_STATE_TxIdle   (10UL)
 
#define RADIO_STATE_STATE_Tx   (11UL)
 
#define RADIO_STATE_STATE_TxDisable   (12UL)
 
#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos   (0UL)
 
#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk   (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos)
 
#define RADIO_BCC_BCC_Pos   (0UL)
 
#define RADIO_BCC_BCC_Msk   (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos)
 
#define RADIO_DAB_DAB_Pos   (0UL)
 
#define RADIO_DAB_DAB_Msk   (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos)
 
#define RADIO_DAP_DAP_Pos   (0UL)
 
#define RADIO_DAP_DAP_Msk   (0xFFFFUL << RADIO_DAP_DAP_Pos)
 
#define RADIO_DACNF_TXADD7_Pos   (15UL)
 
#define RADIO_DACNF_TXADD7_Msk   (0x1UL << RADIO_DACNF_TXADD7_Pos)
 
#define RADIO_DACNF_TXADD6_Pos   (14UL)
 
#define RADIO_DACNF_TXADD6_Msk   (0x1UL << RADIO_DACNF_TXADD6_Pos)
 
#define RADIO_DACNF_TXADD5_Pos   (13UL)
 
#define RADIO_DACNF_TXADD5_Msk   (0x1UL << RADIO_DACNF_TXADD5_Pos)
 
#define RADIO_DACNF_TXADD4_Pos   (12UL)
 
#define RADIO_DACNF_TXADD4_Msk   (0x1UL << RADIO_DACNF_TXADD4_Pos)
 
#define RADIO_DACNF_TXADD3_Pos   (11UL)
 
#define RADIO_DACNF_TXADD3_Msk   (0x1UL << RADIO_DACNF_TXADD3_Pos)
 
#define RADIO_DACNF_TXADD2_Pos   (10UL)
 
#define RADIO_DACNF_TXADD2_Msk   (0x1UL << RADIO_DACNF_TXADD2_Pos)
 
#define RADIO_DACNF_TXADD1_Pos   (9UL)
 
#define RADIO_DACNF_TXADD1_Msk   (0x1UL << RADIO_DACNF_TXADD1_Pos)
 
#define RADIO_DACNF_TXADD0_Pos   (8UL)
 
#define RADIO_DACNF_TXADD0_Msk   (0x1UL << RADIO_DACNF_TXADD0_Pos)
 
#define RADIO_DACNF_ENA7_Pos   (7UL)
 
#define RADIO_DACNF_ENA7_Msk   (0x1UL << RADIO_DACNF_ENA7_Pos)
 
#define RADIO_DACNF_ENA7_Disabled   (0UL)
 
#define RADIO_DACNF_ENA7_Enabled   (1UL)
 
#define RADIO_DACNF_ENA6_Pos   (6UL)
 
#define RADIO_DACNF_ENA6_Msk   (0x1UL << RADIO_DACNF_ENA6_Pos)
 
#define RADIO_DACNF_ENA6_Disabled   (0UL)
 
#define RADIO_DACNF_ENA6_Enabled   (1UL)
 
#define RADIO_DACNF_ENA5_Pos   (5UL)
 
#define RADIO_DACNF_ENA5_Msk   (0x1UL << RADIO_DACNF_ENA5_Pos)
 
#define RADIO_DACNF_ENA5_Disabled   (0UL)
 
#define RADIO_DACNF_ENA5_Enabled   (1UL)
 
#define RADIO_DACNF_ENA4_Pos   (4UL)
 
#define RADIO_DACNF_ENA4_Msk   (0x1UL << RADIO_DACNF_ENA4_Pos)
 
#define RADIO_DACNF_ENA4_Disabled   (0UL)
 
#define RADIO_DACNF_ENA4_Enabled   (1UL)
 
#define RADIO_DACNF_ENA3_Pos   (3UL)
 
#define RADIO_DACNF_ENA3_Msk   (0x1UL << RADIO_DACNF_ENA3_Pos)
 
#define RADIO_DACNF_ENA3_Disabled   (0UL)
 
#define RADIO_DACNF_ENA3_Enabled   (1UL)
 
#define RADIO_DACNF_ENA2_Pos   (2UL)
 
#define RADIO_DACNF_ENA2_Msk   (0x1UL << RADIO_DACNF_ENA2_Pos)
 
#define RADIO_DACNF_ENA2_Disabled   (0UL)
 
#define RADIO_DACNF_ENA2_Enabled   (1UL)
 
#define RADIO_DACNF_ENA1_Pos   (1UL)
 
#define RADIO_DACNF_ENA1_Msk   (0x1UL << RADIO_DACNF_ENA1_Pos)
 
#define RADIO_DACNF_ENA1_Disabled   (0UL)
 
#define RADIO_DACNF_ENA1_Enabled   (1UL)
 
#define RADIO_DACNF_ENA0_Pos   (0UL)
 
#define RADIO_DACNF_ENA0_Msk   (0x1UL << RADIO_DACNF_ENA0_Pos)
 
#define RADIO_DACNF_ENA0_Disabled   (0UL)
 
#define RADIO_DACNF_ENA0_Enabled   (1UL)
 
#define RADIO_MODECNF0_DTX_Pos   (8UL)
 
#define RADIO_MODECNF0_DTX_Msk   (0x3UL << RADIO_MODECNF0_DTX_Pos)
 
#define RADIO_MODECNF0_DTX_B1   (0UL)
 
#define RADIO_MODECNF0_DTX_B0   (1UL)
 
#define RADIO_MODECNF0_DTX_Center   (2UL)
 
#define RADIO_MODECNF0_RU_Pos   (0UL)
 
#define RADIO_MODECNF0_RU_Msk   (0x1UL << RADIO_MODECNF0_RU_Pos)
 
#define RADIO_MODECNF0_RU_Default   (0UL)
 
#define RADIO_MODECNF0_RU_Fast   (1UL)
 
#define RADIO_POWER_POWER_Pos   (0UL)
 
#define RADIO_POWER_POWER_Msk   (0x1UL << RADIO_POWER_POWER_Pos)
 
#define RADIO_POWER_POWER_Disabled   (0UL)
 
#define RADIO_POWER_POWER_Enabled   (1UL)
 
#define RNG_SHORTS_VALRDY_STOP_Pos   (0UL)
 
#define RNG_SHORTS_VALRDY_STOP_Msk   (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos)
 
#define RNG_SHORTS_VALRDY_STOP_Disabled   (0UL)
 
#define RNG_SHORTS_VALRDY_STOP_Enabled   (1UL)
 
#define RNG_INTENSET_VALRDY_Pos   (0UL)
 
#define RNG_INTENSET_VALRDY_Msk   (0x1UL << RNG_INTENSET_VALRDY_Pos)
 
#define RNG_INTENSET_VALRDY_Disabled   (0UL)
 
#define RNG_INTENSET_VALRDY_Enabled   (1UL)
 
#define RNG_INTENSET_VALRDY_Set   (1UL)
 
#define RNG_INTENCLR_VALRDY_Pos   (0UL)
 
#define RNG_INTENCLR_VALRDY_Msk   (0x1UL << RNG_INTENCLR_VALRDY_Pos)
 
#define RNG_INTENCLR_VALRDY_Disabled   (0UL)
 
#define RNG_INTENCLR_VALRDY_Enabled   (1UL)
 
#define RNG_INTENCLR_VALRDY_Clear   (1UL)
 
#define RNG_CONFIG_DERCEN_Pos   (0UL)
 
#define RNG_CONFIG_DERCEN_Msk   (0x1UL << RNG_CONFIG_DERCEN_Pos)
 
#define RNG_CONFIG_DERCEN_Disabled   (0UL)
 
#define RNG_CONFIG_DERCEN_Enabled   (1UL)
 
#define RNG_VALUE_VALUE_Pos   (0UL)
 
#define RNG_VALUE_VALUE_Msk   (0xFFUL << RNG_VALUE_VALUE_Pos)
 
#define RTC_INTENSET_COMPARE3_Pos   (19UL)
 
#define RTC_INTENSET_COMPARE3_Msk   (0x1UL << RTC_INTENSET_COMPARE3_Pos)
 
#define RTC_INTENSET_COMPARE3_Disabled   (0UL)
 
#define RTC_INTENSET_COMPARE3_Enabled   (1UL)
 
#define RTC_INTENSET_COMPARE3_Set   (1UL)
 
#define RTC_INTENSET_COMPARE2_Pos   (18UL)
 
#define RTC_INTENSET_COMPARE2_Msk   (0x1UL << RTC_INTENSET_COMPARE2_Pos)
 
#define RTC_INTENSET_COMPARE2_Disabled   (0UL)
 
#define RTC_INTENSET_COMPARE2_Enabled   (1UL)
 
#define RTC_INTENSET_COMPARE2_Set   (1UL)
 
#define RTC_INTENSET_COMPARE1_Pos   (17UL)
 
#define RTC_INTENSET_COMPARE1_Msk   (0x1UL << RTC_INTENSET_COMPARE1_Pos)
 
#define RTC_INTENSET_COMPARE1_Disabled   (0UL)
 
#define RTC_INTENSET_COMPARE1_Enabled   (1UL)
 
#define RTC_INTENSET_COMPARE1_Set   (1UL)
 
#define RTC_INTENSET_COMPARE0_Pos   (16UL)
 
#define RTC_INTENSET_COMPARE0_Msk   (0x1UL << RTC_INTENSET_COMPARE0_Pos)
 
#define RTC_INTENSET_COMPARE0_Disabled   (0UL)
 
#define RTC_INTENSET_COMPARE0_Enabled   (1UL)
 
#define RTC_INTENSET_COMPARE0_Set   (1UL)
 
#define RTC_INTENSET_OVRFLW_Pos   (1UL)
 
#define RTC_INTENSET_OVRFLW_Msk   (0x1UL << RTC_INTENSET_OVRFLW_Pos)
 
#define RTC_INTENSET_OVRFLW_Disabled   (0UL)
 
#define RTC_INTENSET_OVRFLW_Enabled   (1UL)
 
#define RTC_INTENSET_OVRFLW_Set   (1UL)
 
#define RTC_INTENSET_TICK_Pos   (0UL)
 
#define RTC_INTENSET_TICK_Msk   (0x1UL << RTC_INTENSET_TICK_Pos)
 
#define RTC_INTENSET_TICK_Disabled   (0UL)
 
#define RTC_INTENSET_TICK_Enabled   (1UL)
 
#define RTC_INTENSET_TICK_Set   (1UL)
 
#define RTC_INTENCLR_COMPARE3_Pos   (19UL)
 
#define RTC_INTENCLR_COMPARE3_Msk   (0x1UL << RTC_INTENCLR_COMPARE3_Pos)
 
#define RTC_INTENCLR_COMPARE3_Disabled   (0UL)
 
#define RTC_INTENCLR_COMPARE3_Enabled   (1UL)
 
#define RTC_INTENCLR_COMPARE3_Clear   (1UL)
 
#define RTC_INTENCLR_COMPARE2_Pos   (18UL)
 
#define RTC_INTENCLR_COMPARE2_Msk   (0x1UL << RTC_INTENCLR_COMPARE2_Pos)
 
#define RTC_INTENCLR_COMPARE2_Disabled   (0UL)
 
#define RTC_INTENCLR_COMPARE2_Enabled   (1UL)
 
#define RTC_INTENCLR_COMPARE2_Clear   (1UL)
 
#define RTC_INTENCLR_COMPARE1_Pos   (17UL)
 
#define RTC_INTENCLR_COMPARE1_Msk   (0x1UL << RTC_INTENCLR_COMPARE1_Pos)
 
#define RTC_INTENCLR_COMPARE1_Disabled   (0UL)
 
#define RTC_INTENCLR_COMPARE1_Enabled   (1UL)
 
#define RTC_INTENCLR_COMPARE1_Clear   (1UL)
 
#define RTC_INTENCLR_COMPARE0_Pos   (16UL)
 
#define RTC_INTENCLR_COMPARE0_Msk   (0x1UL << RTC_INTENCLR_COMPARE0_Pos)
 
#define RTC_INTENCLR_COMPARE0_Disabled   (0UL)
 
#define RTC_INTENCLR_COMPARE0_Enabled   (1UL)
 
#define RTC_INTENCLR_COMPARE0_Clear   (1UL)
 
#define RTC_INTENCLR_OVRFLW_Pos   (1UL)
 
#define RTC_INTENCLR_OVRFLW_Msk   (0x1UL << RTC_INTENCLR_OVRFLW_Pos)
 
#define RTC_INTENCLR_OVRFLW_Disabled   (0UL)
 
#define RTC_INTENCLR_OVRFLW_Enabled   (1UL)
 
#define RTC_INTENCLR_OVRFLW_Clear   (1UL)
 
#define RTC_INTENCLR_TICK_Pos   (0UL)
 
#define RTC_INTENCLR_TICK_Msk   (0x1UL << RTC_INTENCLR_TICK_Pos)
 
#define RTC_INTENCLR_TICK_Disabled   (0UL)
 
#define RTC_INTENCLR_TICK_Enabled   (1UL)
 
#define RTC_INTENCLR_TICK_Clear   (1UL)
 
#define RTC_EVTEN_COMPARE3_Pos   (19UL)
 
#define RTC_EVTEN_COMPARE3_Msk   (0x1UL << RTC_EVTEN_COMPARE3_Pos)
 
#define RTC_EVTEN_COMPARE3_Disabled   (0UL)
 
#define RTC_EVTEN_COMPARE3_Enabled   (1UL)
 
#define RTC_EVTEN_COMPARE2_Pos   (18UL)
 
#define RTC_EVTEN_COMPARE2_Msk   (0x1UL << RTC_EVTEN_COMPARE2_Pos)
 
#define RTC_EVTEN_COMPARE2_Disabled   (0UL)
 
#define RTC_EVTEN_COMPARE2_Enabled   (1UL)
 
#define RTC_EVTEN_COMPARE1_Pos   (17UL)
 
#define RTC_EVTEN_COMPARE1_Msk   (0x1UL << RTC_EVTEN_COMPARE1_Pos)
 
#define RTC_EVTEN_COMPARE1_Disabled   (0UL)
 
#define RTC_EVTEN_COMPARE1_Enabled   (1UL)
 
#define RTC_EVTEN_COMPARE0_Pos   (16UL)
 
#define RTC_EVTEN_COMPARE0_Msk   (0x1UL << RTC_EVTEN_COMPARE0_Pos)
 
#define RTC_EVTEN_COMPARE0_Disabled   (0UL)
 
#define RTC_EVTEN_COMPARE0_Enabled   (1UL)
 
#define RTC_EVTEN_OVRFLW_Pos   (1UL)
 
#define RTC_EVTEN_OVRFLW_Msk   (0x1UL << RTC_EVTEN_OVRFLW_Pos)
 
#define RTC_EVTEN_OVRFLW_Disabled   (0UL)
 
#define RTC_EVTEN_OVRFLW_Enabled   (1UL)
 
#define RTC_EVTEN_TICK_Pos   (0UL)
 
#define RTC_EVTEN_TICK_Msk   (0x1UL << RTC_EVTEN_TICK_Pos)
 
#define RTC_EVTEN_TICK_Disabled   (0UL)
 
#define RTC_EVTEN_TICK_Enabled   (1UL)
 
#define RTC_EVTENSET_COMPARE3_Pos   (19UL)
 
#define RTC_EVTENSET_COMPARE3_Msk   (0x1UL << RTC_EVTENSET_COMPARE3_Pos)
 
#define RTC_EVTENSET_COMPARE3_Disabled   (0UL)
 
#define RTC_EVTENSET_COMPARE3_Enabled   (1UL)
 
#define RTC_EVTENSET_COMPARE3_Set   (1UL)
 
#define RTC_EVTENSET_COMPARE2_Pos   (18UL)
 
#define RTC_EVTENSET_COMPARE2_Msk   (0x1UL << RTC_EVTENSET_COMPARE2_Pos)
 
#define RTC_EVTENSET_COMPARE2_Disabled   (0UL)
 
#define RTC_EVTENSET_COMPARE2_Enabled   (1UL)
 
#define RTC_EVTENSET_COMPARE2_Set   (1UL)
 
#define RTC_EVTENSET_COMPARE1_Pos   (17UL)
 
#define RTC_EVTENSET_COMPARE1_Msk   (0x1UL << RTC_EVTENSET_COMPARE1_Pos)
 
#define RTC_EVTENSET_COMPARE1_Disabled   (0UL)
 
#define RTC_EVTENSET_COMPARE1_Enabled   (1UL)
 
#define RTC_EVTENSET_COMPARE1_Set   (1UL)
 
#define RTC_EVTENSET_COMPARE0_Pos   (16UL)
 
#define RTC_EVTENSET_COMPARE0_Msk   (0x1UL << RTC_EVTENSET_COMPARE0_Pos)
 
#define RTC_EVTENSET_COMPARE0_Disabled   (0UL)
 
#define RTC_EVTENSET_COMPARE0_Enabled   (1UL)
 
#define RTC_EVTENSET_COMPARE0_Set   (1UL)
 
#define RTC_EVTENSET_OVRFLW_Pos   (1UL)
 
#define RTC_EVTENSET_OVRFLW_Msk   (0x1UL << RTC_EVTENSET_OVRFLW_Pos)
 
#define RTC_EVTENSET_OVRFLW_Disabled   (0UL)
 
#define RTC_EVTENSET_OVRFLW_Enabled   (1UL)
 
#define RTC_EVTENSET_OVRFLW_Set   (1UL)
 
#define RTC_EVTENSET_TICK_Pos   (0UL)
 
#define RTC_EVTENSET_TICK_Msk   (0x1UL << RTC_EVTENSET_TICK_Pos)
 
#define RTC_EVTENSET_TICK_Disabled   (0UL)
 
#define RTC_EVTENSET_TICK_Enabled   (1UL)
 
#define RTC_EVTENSET_TICK_Set   (1UL)
 
#define RTC_EVTENCLR_COMPARE3_Pos   (19UL)
 
#define RTC_EVTENCLR_COMPARE3_Msk   (0x1UL << RTC_EVTENCLR_COMPARE3_Pos)
 
#define RTC_EVTENCLR_COMPARE3_Disabled   (0UL)
 
#define RTC_EVTENCLR_COMPARE3_Enabled   (1UL)
 
#define RTC_EVTENCLR_COMPARE3_Clear   (1UL)
 
#define RTC_EVTENCLR_COMPARE2_Pos   (18UL)
 
#define RTC_EVTENCLR_COMPARE2_Msk   (0x1UL << RTC_EVTENCLR_COMPARE2_Pos)
 
#define RTC_EVTENCLR_COMPARE2_Disabled   (0UL)
 
#define RTC_EVTENCLR_COMPARE2_Enabled   (1UL)
 
#define RTC_EVTENCLR_COMPARE2_Clear   (1UL)
 
#define RTC_EVTENCLR_COMPARE1_Pos   (17UL)
 
#define RTC_EVTENCLR_COMPARE1_Msk   (0x1UL << RTC_EVTENCLR_COMPARE1_Pos)
 
#define RTC_EVTENCLR_COMPARE1_Disabled   (0UL)
 
#define RTC_EVTENCLR_COMPARE1_Enabled   (1UL)
 
#define RTC_EVTENCLR_COMPARE1_Clear   (1UL)
 
#define RTC_EVTENCLR_COMPARE0_Pos   (16UL)
 
#define RTC_EVTENCLR_COMPARE0_Msk   (0x1UL << RTC_EVTENCLR_COMPARE0_Pos)
 
#define RTC_EVTENCLR_COMPARE0_Disabled   (0UL)
 
#define RTC_EVTENCLR_COMPARE0_Enabled   (1UL)
 
#define RTC_EVTENCLR_COMPARE0_Clear   (1UL)
 
#define RTC_EVTENCLR_OVRFLW_Pos   (1UL)
 
#define RTC_EVTENCLR_OVRFLW_Msk   (0x1UL << RTC_EVTENCLR_OVRFLW_Pos)
 
#define RTC_EVTENCLR_OVRFLW_Disabled   (0UL)
 
#define RTC_EVTENCLR_OVRFLW_Enabled   (1UL)
 
#define RTC_EVTENCLR_OVRFLW_Clear   (1UL)
 
#define RTC_EVTENCLR_TICK_Pos   (0UL)
 
#define RTC_EVTENCLR_TICK_Msk   (0x1UL << RTC_EVTENCLR_TICK_Pos)
 
#define RTC_EVTENCLR_TICK_Disabled   (0UL)
 
#define RTC_EVTENCLR_TICK_Enabled   (1UL)
 
#define RTC_EVTENCLR_TICK_Clear   (1UL)
 
#define RTC_COUNTER_COUNTER_Pos   (0UL)
 
#define RTC_COUNTER_COUNTER_Msk   (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos)
 
#define RTC_PRESCALER_PRESCALER_Pos   (0UL)
 
#define RTC_PRESCALER_PRESCALER_Msk   (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos)
 
#define RTC_CC_COMPARE_Pos   (0UL)
 
#define RTC_CC_COMPARE_Msk   (0xFFFFFFUL << RTC_CC_COMPARE_Pos)
 
#define SAADC_INTEN_CH7LIMITL_Pos   (21UL)
 
#define SAADC_INTEN_CH7LIMITL_Msk   (0x1UL << SAADC_INTEN_CH7LIMITL_Pos)
 
#define SAADC_INTEN_CH7LIMITL_Disabled   (0UL)
 
#define SAADC_INTEN_CH7LIMITL_Enabled   (1UL)
 
#define SAADC_INTEN_CH7LIMITH_Pos   (20UL)
 
#define SAADC_INTEN_CH7LIMITH_Msk   (0x1UL << SAADC_INTEN_CH7LIMITH_Pos)
 
#define SAADC_INTEN_CH7LIMITH_Disabled   (0UL)
 
#define SAADC_INTEN_CH7LIMITH_Enabled   (1UL)
 
#define SAADC_INTEN_CH6LIMITL_Pos   (19UL)
 
#define SAADC_INTEN_CH6LIMITL_Msk   (0x1UL << SAADC_INTEN_CH6LIMITL_Pos)
 
#define SAADC_INTEN_CH6LIMITL_Disabled   (0UL)
 
#define SAADC_INTEN_CH6LIMITL_Enabled   (1UL)
 
#define SAADC_INTEN_CH6LIMITH_Pos   (18UL)
 
#define SAADC_INTEN_CH6LIMITH_Msk   (0x1UL << SAADC_INTEN_CH6LIMITH_Pos)
 
#define SAADC_INTEN_CH6LIMITH_Disabled   (0UL)
 
#define SAADC_INTEN_CH6LIMITH_Enabled   (1UL)
 
#define SAADC_INTEN_CH5LIMITL_Pos   (17UL)
 
#define SAADC_INTEN_CH5LIMITL_Msk   (0x1UL << SAADC_INTEN_CH5LIMITL_Pos)
 
#define SAADC_INTEN_CH5LIMITL_Disabled   (0UL)
 
#define SAADC_INTEN_CH5LIMITL_Enabled   (1UL)
 
#define SAADC_INTEN_CH5LIMITH_Pos   (16UL)
 
#define SAADC_INTEN_CH5LIMITH_Msk   (0x1UL << SAADC_INTEN_CH5LIMITH_Pos)
 
#define SAADC_INTEN_CH5LIMITH_Disabled   (0UL)
 
#define SAADC_INTEN_CH5LIMITH_Enabled   (1UL)
 
#define SAADC_INTEN_CH4LIMITL_Pos   (15UL)
 
#define SAADC_INTEN_CH4LIMITL_Msk   (0x1UL << SAADC_INTEN_CH4LIMITL_Pos)
 
#define SAADC_INTEN_CH4LIMITL_Disabled   (0UL)
 
#define SAADC_INTEN_CH4LIMITL_Enabled   (1UL)
 
#define SAADC_INTEN_CH4LIMITH_Pos   (14UL)
 
#define SAADC_INTEN_CH4LIMITH_Msk   (0x1UL << SAADC_INTEN_CH4LIMITH_Pos)
 
#define SAADC_INTEN_CH4LIMITH_Disabled   (0UL)
 
#define SAADC_INTEN_CH4LIMITH_Enabled   (1UL)
 
#define SAADC_INTEN_CH3LIMITL_Pos   (13UL)
 
#define SAADC_INTEN_CH3LIMITL_Msk   (0x1UL << SAADC_INTEN_CH3LIMITL_Pos)
 
#define SAADC_INTEN_CH3LIMITL_Disabled   (0UL)
 
#define SAADC_INTEN_CH3LIMITL_Enabled   (1UL)
 
#define SAADC_INTEN_CH3LIMITH_Pos   (12UL)
 
#define SAADC_INTEN_CH3LIMITH_Msk   (0x1UL << SAADC_INTEN_CH3LIMITH_Pos)
 
#define SAADC_INTEN_CH3LIMITH_Disabled   (0UL)
 
#define SAADC_INTEN_CH3LIMITH_Enabled   (1UL)
 
#define SAADC_INTEN_CH2LIMITL_Pos   (11UL)
 
#define SAADC_INTEN_CH2LIMITL_Msk   (0x1UL << SAADC_INTEN_CH2LIMITL_Pos)
 
#define SAADC_INTEN_CH2LIMITL_Disabled   (0UL)
 
#define SAADC_INTEN_CH2LIMITL_Enabled   (1UL)
 
#define SAADC_INTEN_CH2LIMITH_Pos   (10UL)
 
#define SAADC_INTEN_CH2LIMITH_Msk   (0x1UL << SAADC_INTEN_CH2LIMITH_Pos)
 
#define SAADC_INTEN_CH2LIMITH_Disabled   (0UL)
 
#define SAADC_INTEN_CH2LIMITH_Enabled   (1UL)
 
#define SAADC_INTEN_CH1LIMITL_Pos   (9UL)
 
#define SAADC_INTEN_CH1LIMITL_Msk   (0x1UL << SAADC_INTEN_CH1LIMITL_Pos)
 
#define SAADC_INTEN_CH1LIMITL_Disabled   (0UL)
 
#define SAADC_INTEN_CH1LIMITL_Enabled   (1UL)
 
#define SAADC_INTEN_CH1LIMITH_Pos   (8UL)
 
#define SAADC_INTEN_CH1LIMITH_Msk   (0x1UL << SAADC_INTEN_CH1LIMITH_Pos)
 
#define SAADC_INTEN_CH1LIMITH_Disabled   (0UL)
 
#define SAADC_INTEN_CH1LIMITH_Enabled   (1UL)
 
#define SAADC_INTEN_CH0LIMITL_Pos   (7UL)
 
#define SAADC_INTEN_CH0LIMITL_Msk   (0x1UL << SAADC_INTEN_CH0LIMITL_Pos)
 
#define SAADC_INTEN_CH0LIMITL_Disabled   (0UL)
 
#define SAADC_INTEN_CH0LIMITL_Enabled   (1UL)
 
#define SAADC_INTEN_CH0LIMITH_Pos   (6UL)
 
#define SAADC_INTEN_CH0LIMITH_Msk   (0x1UL << SAADC_INTEN_CH0LIMITH_Pos)
 
#define SAADC_INTEN_CH0LIMITH_Disabled   (0UL)
 
#define SAADC_INTEN_CH0LIMITH_Enabled   (1UL)
 
#define SAADC_INTEN_STOPPED_Pos   (5UL)
 
#define SAADC_INTEN_STOPPED_Msk   (0x1UL << SAADC_INTEN_STOPPED_Pos)
 
#define SAADC_INTEN_STOPPED_Disabled   (0UL)
 
#define SAADC_INTEN_STOPPED_Enabled   (1UL)
 
#define SAADC_INTEN_CALIBRATEDONE_Pos   (4UL)
 
#define SAADC_INTEN_CALIBRATEDONE_Msk   (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos)
 
#define SAADC_INTEN_CALIBRATEDONE_Disabled   (0UL)
 
#define SAADC_INTEN_CALIBRATEDONE_Enabled   (1UL)
 
#define SAADC_INTEN_RESULTDONE_Pos   (3UL)
 
#define SAADC_INTEN_RESULTDONE_Msk   (0x1UL << SAADC_INTEN_RESULTDONE_Pos)
 
#define SAADC_INTEN_RESULTDONE_Disabled   (0UL)
 
#define SAADC_INTEN_RESULTDONE_Enabled   (1UL)
 
#define SAADC_INTEN_DONE_Pos   (2UL)
 
#define SAADC_INTEN_DONE_Msk   (0x1UL << SAADC_INTEN_DONE_Pos)
 
#define SAADC_INTEN_DONE_Disabled   (0UL)
 
#define SAADC_INTEN_DONE_Enabled   (1UL)
 
#define SAADC_INTEN_END_Pos   (1UL)
 
#define SAADC_INTEN_END_Msk   (0x1UL << SAADC_INTEN_END_Pos)
 
#define SAADC_INTEN_END_Disabled   (0UL)
 
#define SAADC_INTEN_END_Enabled   (1UL)
 
#define SAADC_INTEN_STARTED_Pos   (0UL)
 
#define SAADC_INTEN_STARTED_Msk   (0x1UL << SAADC_INTEN_STARTED_Pos)
 
#define SAADC_INTEN_STARTED_Disabled   (0UL)
 
#define SAADC_INTEN_STARTED_Enabled   (1UL)
 
#define SAADC_INTENSET_CH7LIMITL_Pos   (21UL)
 
#define SAADC_INTENSET_CH7LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos)
 
#define SAADC_INTENSET_CH7LIMITL_Disabled   (0UL)
 
#define SAADC_INTENSET_CH7LIMITL_Enabled   (1UL)
 
#define SAADC_INTENSET_CH7LIMITL_Set   (1UL)
 
#define SAADC_INTENSET_CH7LIMITH_Pos   (20UL)
 
#define SAADC_INTENSET_CH7LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos)
 
#define SAADC_INTENSET_CH7LIMITH_Disabled   (0UL)
 
#define SAADC_INTENSET_CH7LIMITH_Enabled   (1UL)
 
#define SAADC_INTENSET_CH7LIMITH_Set   (1UL)
 
#define SAADC_INTENSET_CH6LIMITL_Pos   (19UL)
 
#define SAADC_INTENSET_CH6LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos)
 
#define SAADC_INTENSET_CH6LIMITL_Disabled   (0UL)
 
#define SAADC_INTENSET_CH6LIMITL_Enabled   (1UL)
 
#define SAADC_INTENSET_CH6LIMITL_Set   (1UL)
 
#define SAADC_INTENSET_CH6LIMITH_Pos   (18UL)
 
#define SAADC_INTENSET_CH6LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos)
 
#define SAADC_INTENSET_CH6LIMITH_Disabled   (0UL)
 
#define SAADC_INTENSET_CH6LIMITH_Enabled   (1UL)
 
#define SAADC_INTENSET_CH6LIMITH_Set   (1UL)
 
#define SAADC_INTENSET_CH5LIMITL_Pos   (17UL)
 
#define SAADC_INTENSET_CH5LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos)
 
#define SAADC_INTENSET_CH5LIMITL_Disabled   (0UL)
 
#define SAADC_INTENSET_CH5LIMITL_Enabled   (1UL)
 
#define SAADC_INTENSET_CH5LIMITL_Set   (1UL)
 
#define SAADC_INTENSET_CH5LIMITH_Pos   (16UL)
 
#define SAADC_INTENSET_CH5LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos)
 
#define SAADC_INTENSET_CH5LIMITH_Disabled   (0UL)
 
#define SAADC_INTENSET_CH5LIMITH_Enabled   (1UL)
 
#define SAADC_INTENSET_CH5LIMITH_Set   (1UL)
 
#define SAADC_INTENSET_CH4LIMITL_Pos   (15UL)
 
#define SAADC_INTENSET_CH4LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos)
 
#define SAADC_INTENSET_CH4LIMITL_Disabled   (0UL)
 
#define SAADC_INTENSET_CH4LIMITL_Enabled   (1UL)
 
#define SAADC_INTENSET_CH4LIMITL_Set   (1UL)
 
#define SAADC_INTENSET_CH4LIMITH_Pos   (14UL)
 
#define SAADC_INTENSET_CH4LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos)
 
#define SAADC_INTENSET_CH4LIMITH_Disabled   (0UL)
 
#define SAADC_INTENSET_CH4LIMITH_Enabled   (1UL)
 
#define SAADC_INTENSET_CH4LIMITH_Set   (1UL)
 
#define SAADC_INTENSET_CH3LIMITL_Pos   (13UL)
 
#define SAADC_INTENSET_CH3LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos)
 
#define SAADC_INTENSET_CH3LIMITL_Disabled   (0UL)
 
#define SAADC_INTENSET_CH3LIMITL_Enabled   (1UL)
 
#define SAADC_INTENSET_CH3LIMITL_Set   (1UL)
 
#define SAADC_INTENSET_CH3LIMITH_Pos   (12UL)
 
#define SAADC_INTENSET_CH3LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos)
 
#define SAADC_INTENSET_CH3LIMITH_Disabled   (0UL)
 
#define SAADC_INTENSET_CH3LIMITH_Enabled   (1UL)
 
#define SAADC_INTENSET_CH3LIMITH_Set   (1UL)
 
#define SAADC_INTENSET_CH2LIMITL_Pos   (11UL)
 
#define SAADC_INTENSET_CH2LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos)
 
#define SAADC_INTENSET_CH2LIMITL_Disabled   (0UL)
 
#define SAADC_INTENSET_CH2LIMITL_Enabled   (1UL)
 
#define SAADC_INTENSET_CH2LIMITL_Set   (1UL)
 
#define SAADC_INTENSET_CH2LIMITH_Pos   (10UL)
 
#define SAADC_INTENSET_CH2LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos)
 
#define SAADC_INTENSET_CH2LIMITH_Disabled   (0UL)
 
#define SAADC_INTENSET_CH2LIMITH_Enabled   (1UL)
 
#define SAADC_INTENSET_CH2LIMITH_Set   (1UL)
 
#define SAADC_INTENSET_CH1LIMITL_Pos   (9UL)
 
#define SAADC_INTENSET_CH1LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos)
 
#define SAADC_INTENSET_CH1LIMITL_Disabled   (0UL)
 
#define SAADC_INTENSET_CH1LIMITL_Enabled   (1UL)
 
#define SAADC_INTENSET_CH1LIMITL_Set   (1UL)
 
#define SAADC_INTENSET_CH1LIMITH_Pos   (8UL)
 
#define SAADC_INTENSET_CH1LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos)
 
#define SAADC_INTENSET_CH1LIMITH_Disabled   (0UL)
 
#define SAADC_INTENSET_CH1LIMITH_Enabled   (1UL)
 
#define SAADC_INTENSET_CH1LIMITH_Set   (1UL)
 
#define SAADC_INTENSET_CH0LIMITL_Pos   (7UL)
 
#define SAADC_INTENSET_CH0LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos)
 
#define SAADC_INTENSET_CH0LIMITL_Disabled   (0UL)
 
#define SAADC_INTENSET_CH0LIMITL_Enabled   (1UL)
 
#define SAADC_INTENSET_CH0LIMITL_Set   (1UL)
 
#define SAADC_INTENSET_CH0LIMITH_Pos   (6UL)
 
#define SAADC_INTENSET_CH0LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos)
 
#define SAADC_INTENSET_CH0LIMITH_Disabled   (0UL)
 
#define SAADC_INTENSET_CH0LIMITH_Enabled   (1UL)
 
#define SAADC_INTENSET_CH0LIMITH_Set   (1UL)
 
#define SAADC_INTENSET_STOPPED_Pos   (5UL)
 
#define SAADC_INTENSET_STOPPED_Msk   (0x1UL << SAADC_INTENSET_STOPPED_Pos)
 
#define SAADC_INTENSET_STOPPED_Disabled   (0UL)
 
#define SAADC_INTENSET_STOPPED_Enabled   (1UL)
 
#define SAADC_INTENSET_STOPPED_Set   (1UL)
 
#define SAADC_INTENSET_CALIBRATEDONE_Pos   (4UL)
 
#define SAADC_INTENSET_CALIBRATEDONE_Msk   (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos)
 
#define SAADC_INTENSET_CALIBRATEDONE_Disabled   (0UL)
 
#define SAADC_INTENSET_CALIBRATEDONE_Enabled   (1UL)
 
#define SAADC_INTENSET_CALIBRATEDONE_Set   (1UL)
 
#define SAADC_INTENSET_RESULTDONE_Pos   (3UL)
 
#define SAADC_INTENSET_RESULTDONE_Msk   (0x1UL << SAADC_INTENSET_RESULTDONE_Pos)
 
#define SAADC_INTENSET_RESULTDONE_Disabled   (0UL)
 
#define SAADC_INTENSET_RESULTDONE_Enabled   (1UL)
 
#define SAADC_INTENSET_RESULTDONE_Set   (1UL)
 
#define SAADC_INTENSET_DONE_Pos   (2UL)
 
#define SAADC_INTENSET_DONE_Msk   (0x1UL << SAADC_INTENSET_DONE_Pos)
 
#define SAADC_INTENSET_DONE_Disabled   (0UL)
 
#define SAADC_INTENSET_DONE_Enabled   (1UL)
 
#define SAADC_INTENSET_DONE_Set   (1UL)
 
#define SAADC_INTENSET_END_Pos   (1UL)
 
#define SAADC_INTENSET_END_Msk   (0x1UL << SAADC_INTENSET_END_Pos)
 
#define SAADC_INTENSET_END_Disabled   (0UL)
 
#define SAADC_INTENSET_END_Enabled   (1UL)
 
#define SAADC_INTENSET_END_Set   (1UL)
 
#define SAADC_INTENSET_STARTED_Pos   (0UL)
 
#define SAADC_INTENSET_STARTED_Msk   (0x1UL << SAADC_INTENSET_STARTED_Pos)
 
#define SAADC_INTENSET_STARTED_Disabled   (0UL)
 
#define SAADC_INTENSET_STARTED_Enabled   (1UL)
 
#define SAADC_INTENSET_STARTED_Set   (1UL)
 
#define SAADC_INTENCLR_CH7LIMITL_Pos   (21UL)
 
#define SAADC_INTENCLR_CH7LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos)
 
#define SAADC_INTENCLR_CH7LIMITL_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH7LIMITL_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH7LIMITL_Clear   (1UL)
 
#define SAADC_INTENCLR_CH7LIMITH_Pos   (20UL)
 
#define SAADC_INTENCLR_CH7LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos)
 
#define SAADC_INTENCLR_CH7LIMITH_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH7LIMITH_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH7LIMITH_Clear   (1UL)
 
#define SAADC_INTENCLR_CH6LIMITL_Pos   (19UL)
 
#define SAADC_INTENCLR_CH6LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos)
 
#define SAADC_INTENCLR_CH6LIMITL_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH6LIMITL_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH6LIMITL_Clear   (1UL)
 
#define SAADC_INTENCLR_CH6LIMITH_Pos   (18UL)
 
#define SAADC_INTENCLR_CH6LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos)
 
#define SAADC_INTENCLR_CH6LIMITH_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH6LIMITH_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH6LIMITH_Clear   (1UL)
 
#define SAADC_INTENCLR_CH5LIMITL_Pos   (17UL)
 
#define SAADC_INTENCLR_CH5LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos)
 
#define SAADC_INTENCLR_CH5LIMITL_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH5LIMITL_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH5LIMITL_Clear   (1UL)
 
#define SAADC_INTENCLR_CH5LIMITH_Pos   (16UL)
 
#define SAADC_INTENCLR_CH5LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos)
 
#define SAADC_INTENCLR_CH5LIMITH_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH5LIMITH_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH5LIMITH_Clear   (1UL)
 
#define SAADC_INTENCLR_CH4LIMITL_Pos   (15UL)
 
#define SAADC_INTENCLR_CH4LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos)
 
#define SAADC_INTENCLR_CH4LIMITL_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH4LIMITL_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH4LIMITL_Clear   (1UL)
 
#define SAADC_INTENCLR_CH4LIMITH_Pos   (14UL)
 
#define SAADC_INTENCLR_CH4LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos)
 
#define SAADC_INTENCLR_CH4LIMITH_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH4LIMITH_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH4LIMITH_Clear   (1UL)
 
#define SAADC_INTENCLR_CH3LIMITL_Pos   (13UL)
 
#define SAADC_INTENCLR_CH3LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos)
 
#define SAADC_INTENCLR_CH3LIMITL_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH3LIMITL_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH3LIMITL_Clear   (1UL)
 
#define SAADC_INTENCLR_CH3LIMITH_Pos   (12UL)
 
#define SAADC_INTENCLR_CH3LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos)
 
#define SAADC_INTENCLR_CH3LIMITH_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH3LIMITH_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH3LIMITH_Clear   (1UL)
 
#define SAADC_INTENCLR_CH2LIMITL_Pos   (11UL)
 
#define SAADC_INTENCLR_CH2LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos)
 
#define SAADC_INTENCLR_CH2LIMITL_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH2LIMITL_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH2LIMITL_Clear   (1UL)
 
#define SAADC_INTENCLR_CH2LIMITH_Pos   (10UL)
 
#define SAADC_INTENCLR_CH2LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos)
 
#define SAADC_INTENCLR_CH2LIMITH_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH2LIMITH_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH2LIMITH_Clear   (1UL)
 
#define SAADC_INTENCLR_CH1LIMITL_Pos   (9UL)
 
#define SAADC_INTENCLR_CH1LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos)
 
#define SAADC_INTENCLR_CH1LIMITL_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH1LIMITL_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH1LIMITL_Clear   (1UL)
 
#define SAADC_INTENCLR_CH1LIMITH_Pos   (8UL)
 
#define SAADC_INTENCLR_CH1LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos)
 
#define SAADC_INTENCLR_CH1LIMITH_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH1LIMITH_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH1LIMITH_Clear   (1UL)
 
#define SAADC_INTENCLR_CH0LIMITL_Pos   (7UL)
 
#define SAADC_INTENCLR_CH0LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos)
 
#define SAADC_INTENCLR_CH0LIMITL_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH0LIMITL_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH0LIMITL_Clear   (1UL)
 
#define SAADC_INTENCLR_CH0LIMITH_Pos   (6UL)
 
#define SAADC_INTENCLR_CH0LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos)
 
#define SAADC_INTENCLR_CH0LIMITH_Disabled   (0UL)
 
#define SAADC_INTENCLR_CH0LIMITH_Enabled   (1UL)
 
#define SAADC_INTENCLR_CH0LIMITH_Clear   (1UL)
 
#define SAADC_INTENCLR_STOPPED_Pos   (5UL)
 
#define SAADC_INTENCLR_STOPPED_Msk   (0x1UL << SAADC_INTENCLR_STOPPED_Pos)
 
#define SAADC_INTENCLR_STOPPED_Disabled   (0UL)
 
#define SAADC_INTENCLR_STOPPED_Enabled   (1UL)
 
#define SAADC_INTENCLR_STOPPED_Clear   (1UL)
 
#define SAADC_INTENCLR_CALIBRATEDONE_Pos   (4UL)
 
#define SAADC_INTENCLR_CALIBRATEDONE_Msk   (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos)
 
#define SAADC_INTENCLR_CALIBRATEDONE_Disabled   (0UL)
 
#define SAADC_INTENCLR_CALIBRATEDONE_Enabled   (1UL)
 
#define SAADC_INTENCLR_CALIBRATEDONE_Clear   (1UL)
 
#define SAADC_INTENCLR_RESULTDONE_Pos   (3UL)
 
#define SAADC_INTENCLR_RESULTDONE_Msk   (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos)
 
#define SAADC_INTENCLR_RESULTDONE_Disabled   (0UL)
 
#define SAADC_INTENCLR_RESULTDONE_Enabled   (1UL)
 
#define SAADC_INTENCLR_RESULTDONE_Clear   (1UL)
 
#define SAADC_INTENCLR_DONE_Pos   (2UL)
 
#define SAADC_INTENCLR_DONE_Msk   (0x1UL << SAADC_INTENCLR_DONE_Pos)
 
#define SAADC_INTENCLR_DONE_Disabled   (0UL)
 
#define SAADC_INTENCLR_DONE_Enabled   (1UL)
 
#define SAADC_INTENCLR_DONE_Clear   (1UL)
 
#define SAADC_INTENCLR_END_Pos   (1UL)
 
#define SAADC_INTENCLR_END_Msk   (0x1UL << SAADC_INTENCLR_END_Pos)
 
#define SAADC_INTENCLR_END_Disabled   (0UL)
 
#define SAADC_INTENCLR_END_Enabled   (1UL)
 
#define SAADC_INTENCLR_END_Clear   (1UL)
 
#define SAADC_INTENCLR_STARTED_Pos   (0UL)
 
#define SAADC_INTENCLR_STARTED_Msk   (0x1UL << SAADC_INTENCLR_STARTED_Pos)
 
#define SAADC_INTENCLR_STARTED_Disabled   (0UL)
 
#define SAADC_INTENCLR_STARTED_Enabled   (1UL)
 
#define SAADC_INTENCLR_STARTED_Clear   (1UL)
 
#define SAADC_STATUS_STATUS_Pos   (0UL)
 
#define SAADC_STATUS_STATUS_Msk   (0x1UL << SAADC_STATUS_STATUS_Pos)
 
#define SAADC_STATUS_STATUS_Ready   (0UL)
 
#define SAADC_STATUS_STATUS_Busy   (1UL)
 
#define SAADC_ENABLE_ENABLE_Pos   (0UL)
 
#define SAADC_ENABLE_ENABLE_Msk   (0x1UL << SAADC_ENABLE_ENABLE_Pos)
 
#define SAADC_ENABLE_ENABLE_Disabled   (0UL)
 
#define SAADC_ENABLE_ENABLE_Enabled   (1UL)
 
#define SAADC_CH_PSELP_PSELP_Pos   (0UL)
 
#define SAADC_CH_PSELP_PSELP_Msk   (0x1FUL << SAADC_CH_PSELP_PSELP_Pos)
 
#define SAADC_CH_PSELP_PSELP_NC   (0UL)
 
#define SAADC_CH_PSELP_PSELP_AnalogInput0   (1UL)
 
#define SAADC_CH_PSELP_PSELP_AnalogInput1   (2UL)
 
#define SAADC_CH_PSELP_PSELP_AnalogInput2   (3UL)
 
#define SAADC_CH_PSELP_PSELP_AnalogInput3   (4UL)
 
#define SAADC_CH_PSELP_PSELP_AnalogInput4   (5UL)
 
#define SAADC_CH_PSELP_PSELP_AnalogInput5   (6UL)
 
#define SAADC_CH_PSELP_PSELP_AnalogInput6   (7UL)
 
#define SAADC_CH_PSELP_PSELP_AnalogInput7   (8UL)
 
#define SAADC_CH_PSELP_PSELP_VDD   (9UL)
 
#define SAADC_CH_PSELN_PSELN_Pos   (0UL)
 
#define SAADC_CH_PSELN_PSELN_Msk   (0x1FUL << SAADC_CH_PSELN_PSELN_Pos)
 
#define SAADC_CH_PSELN_PSELN_NC   (0UL)
 
#define SAADC_CH_PSELN_PSELN_AnalogInput0   (1UL)
 
#define SAADC_CH_PSELN_PSELN_AnalogInput1   (2UL)
 
#define SAADC_CH_PSELN_PSELN_AnalogInput2   (3UL)
 
#define SAADC_CH_PSELN_PSELN_AnalogInput3   (4UL)
 
#define SAADC_CH_PSELN_PSELN_AnalogInput4   (5UL)
 
#define SAADC_CH_PSELN_PSELN_AnalogInput5   (6UL)
 
#define SAADC_CH_PSELN_PSELN_AnalogInput6   (7UL)
 
#define SAADC_CH_PSELN_PSELN_AnalogInput7   (8UL)
 
#define SAADC_CH_PSELN_PSELN_VDD   (9UL)
 
#define SAADC_CH_CONFIG_BURST_Pos   (24UL)
 
#define SAADC_CH_CONFIG_BURST_Msk   (0x1UL << SAADC_CH_CONFIG_BURST_Pos)
 
#define SAADC_CH_CONFIG_BURST_Disabled   (0UL)
 
#define SAADC_CH_CONFIG_BURST_Enabled   (1UL)
 
#define SAADC_CH_CONFIG_MODE_Pos   (20UL)
 
#define SAADC_CH_CONFIG_MODE_Msk   (0x1UL << SAADC_CH_CONFIG_MODE_Pos)
 
#define SAADC_CH_CONFIG_MODE_SE   (0UL)
 
#define SAADC_CH_CONFIG_MODE_Diff   (1UL)
 
#define SAADC_CH_CONFIG_TACQ_Pos   (16UL)
 
#define SAADC_CH_CONFIG_TACQ_Msk   (0x7UL << SAADC_CH_CONFIG_TACQ_Pos)
 
#define SAADC_CH_CONFIG_TACQ_3us   (0UL)
 
#define SAADC_CH_CONFIG_TACQ_5us   (1UL)
 
#define SAADC_CH_CONFIG_TACQ_10us   (2UL)
 
#define SAADC_CH_CONFIG_TACQ_15us   (3UL)
 
#define SAADC_CH_CONFIG_TACQ_20us   (4UL)
 
#define SAADC_CH_CONFIG_TACQ_40us   (5UL)
 
#define SAADC_CH_CONFIG_REFSEL_Pos   (12UL)
 
#define SAADC_CH_CONFIG_REFSEL_Msk   (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos)
 
#define SAADC_CH_CONFIG_REFSEL_Internal   (0UL)
 
#define SAADC_CH_CONFIG_REFSEL_VDD1_4   (1UL)
 
#define SAADC_CH_CONFIG_GAIN_Pos   (8UL)
 
#define SAADC_CH_CONFIG_GAIN_Msk   (0x7UL << SAADC_CH_CONFIG_GAIN_Pos)
 
#define SAADC_CH_CONFIG_GAIN_Gain1_6   (0UL)
 
#define SAADC_CH_CONFIG_GAIN_Gain1_5   (1UL)
 
#define SAADC_CH_CONFIG_GAIN_Gain1_4   (2UL)
 
#define SAADC_CH_CONFIG_GAIN_Gain1_3   (3UL)
 
#define SAADC_CH_CONFIG_GAIN_Gain1_2   (4UL)
 
#define SAADC_CH_CONFIG_GAIN_Gain1   (5UL)
 
#define SAADC_CH_CONFIG_GAIN_Gain2   (6UL)
 
#define SAADC_CH_CONFIG_GAIN_Gain4   (7UL)
 
#define SAADC_CH_CONFIG_RESN_Pos   (4UL)
 
#define SAADC_CH_CONFIG_RESN_Msk   (0x3UL << SAADC_CH_CONFIG_RESN_Pos)
 
#define SAADC_CH_CONFIG_RESN_Bypass   (0UL)
 
#define SAADC_CH_CONFIG_RESN_Pulldown   (1UL)
 
#define SAADC_CH_CONFIG_RESN_Pullup   (2UL)
 
#define SAADC_CH_CONFIG_RESN_VDD1_2   (3UL)
 
#define SAADC_CH_CONFIG_RESP_Pos   (0UL)
 
#define SAADC_CH_CONFIG_RESP_Msk   (0x3UL << SAADC_CH_CONFIG_RESP_Pos)
 
#define SAADC_CH_CONFIG_RESP_Bypass   (0UL)
 
#define SAADC_CH_CONFIG_RESP_Pulldown   (1UL)
 
#define SAADC_CH_CONFIG_RESP_Pullup   (2UL)
 
#define SAADC_CH_CONFIG_RESP_VDD1_2   (3UL)
 
#define SAADC_CH_LIMIT_HIGH_Pos   (16UL)
 
#define SAADC_CH_LIMIT_HIGH_Msk   (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos)
 
#define SAADC_CH_LIMIT_LOW_Pos   (0UL)
 
#define SAADC_CH_LIMIT_LOW_Msk   (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos)
 
#define SAADC_RESOLUTION_VAL_Pos   (0UL)
 
#define SAADC_RESOLUTION_VAL_Msk   (0x7UL << SAADC_RESOLUTION_VAL_Pos)
 
#define SAADC_RESOLUTION_VAL_8bit   (0UL)
 
#define SAADC_RESOLUTION_VAL_10bit   (1UL)
 
#define SAADC_RESOLUTION_VAL_12bit   (2UL)
 
#define SAADC_RESOLUTION_VAL_14bit   (3UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos   (0UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk   (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass   (0UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x   (1UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x   (2UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x   (3UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x   (4UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x   (5UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x   (6UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x   (7UL)
 
#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x   (8UL)
 
#define SAADC_SAMPLERATE_MODE_Pos   (12UL)
 
#define SAADC_SAMPLERATE_MODE_Msk   (0x1UL << SAADC_SAMPLERATE_MODE_Pos)
 
#define SAADC_SAMPLERATE_MODE_Task   (0UL)
 
#define SAADC_SAMPLERATE_MODE_Timers   (1UL)
 
#define SAADC_SAMPLERATE_CC_Pos   (0UL)
 
#define SAADC_SAMPLERATE_CC_Msk   (0x7FFUL << SAADC_SAMPLERATE_CC_Pos)
 
#define SAADC_RESULT_PTR_PTR_Pos   (0UL)
 
#define SAADC_RESULT_PTR_PTR_Msk   (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos)
 
#define SAADC_RESULT_MAXCNT_MAXCNT_Pos   (0UL)
 
#define SAADC_RESULT_MAXCNT_MAXCNT_Msk   (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos)
 
#define SAADC_RESULT_AMOUNT_AMOUNT_Pos   (0UL)
 
#define SAADC_RESULT_AMOUNT_AMOUNT_Msk   (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos)
 
#define SPI_INTENSET_READY_Pos   (2UL)
 
#define SPI_INTENSET_READY_Msk   (0x1UL << SPI_INTENSET_READY_Pos)
 
#define SPI_INTENSET_READY_Disabled   (0UL)
 
#define SPI_INTENSET_READY_Enabled   (1UL)
 
#define SPI_INTENSET_READY_Set   (1UL)
 
#define SPI_INTENCLR_READY_Pos   (2UL)
 
#define SPI_INTENCLR_READY_Msk   (0x1UL << SPI_INTENCLR_READY_Pos)
 
#define SPI_INTENCLR_READY_Disabled   (0UL)
 
#define SPI_INTENCLR_READY_Enabled   (1UL)
 
#define SPI_INTENCLR_READY_Clear   (1UL)
 
#define SPI_ENABLE_ENABLE_Pos   (0UL)
 
#define SPI_ENABLE_ENABLE_Msk   (0xFUL << SPI_ENABLE_ENABLE_Pos)
 
#define SPI_ENABLE_ENABLE_Disabled   (0UL)
 
#define SPI_ENABLE_ENABLE_Enabled   (1UL)
 
#define SPI_PSEL_SCK_PSELSCK_Pos   (0UL)
 
#define SPI_PSEL_SCK_PSELSCK_Msk   (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos)
 
#define SPI_PSEL_SCK_PSELSCK_Disconnected   (0xFFFFFFFFUL)
 
#define SPI_PSEL_MOSI_PSELMOSI_Pos   (0UL)
 
#define SPI_PSEL_MOSI_PSELMOSI_Msk   (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos)
 
#define SPI_PSEL_MOSI_PSELMOSI_Disconnected   (0xFFFFFFFFUL)
 
#define SPI_PSEL_MISO_PSELMISO_Pos   (0UL)
 
#define SPI_PSEL_MISO_PSELMISO_Msk   (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos)
 
#define SPI_PSEL_MISO_PSELMISO_Disconnected   (0xFFFFFFFFUL)
 
#define SPI_RXD_RXD_Pos   (0UL)
 
#define SPI_RXD_RXD_Msk   (0xFFUL << SPI_RXD_RXD_Pos)
 
#define SPI_TXD_TXD_Pos   (0UL)
 
#define SPI_TXD_TXD_Msk   (0xFFUL << SPI_TXD_TXD_Pos)
 
#define SPI_FREQUENCY_FREQUENCY_Pos   (0UL)
 
#define SPI_FREQUENCY_FREQUENCY_Msk   (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos)
 
#define SPI_FREQUENCY_FREQUENCY_K125   (0x02000000UL)
 
#define SPI_FREQUENCY_FREQUENCY_K250   (0x04000000UL)
 
#define SPI_FREQUENCY_FREQUENCY_K500   (0x08000000UL)
 
#define SPI_FREQUENCY_FREQUENCY_M1   (0x10000000UL)
 
#define SPI_FREQUENCY_FREQUENCY_M2   (0x20000000UL)
 
#define SPI_FREQUENCY_FREQUENCY_M4   (0x40000000UL)
 
#define SPI_FREQUENCY_FREQUENCY_M8   (0x80000000UL)
 
#define SPI_CONFIG_CPOL_Pos   (2UL)
 
#define SPI_CONFIG_CPOL_Msk   (0x1UL << SPI_CONFIG_CPOL_Pos)
 
#define SPI_CONFIG_CPOL_ActiveHigh   (0UL)
 
#define SPI_CONFIG_CPOL_ActiveLow   (1UL)
 
#define SPI_CONFIG_CPHA_Pos   (1UL)
 
#define SPI_CONFIG_CPHA_Msk   (0x1UL << SPI_CONFIG_CPHA_Pos)
 
#define SPI_CONFIG_CPHA_Leading   (0UL)
 
#define SPI_CONFIG_CPHA_Trailing   (1UL)
 
#define SPI_CONFIG_ORDER_Pos   (0UL)
 
#define SPI_CONFIG_ORDER_Msk   (0x1UL << SPI_CONFIG_ORDER_Pos)
 
#define SPI_CONFIG_ORDER_MsbFirst   (0UL)
 
#define SPI_CONFIG_ORDER_LsbFirst   (1UL)
 
#define SPIM_SHORTS_END_START_Pos   (17UL)
 
#define SPIM_SHORTS_END_START_Msk   (0x1UL << SPIM_SHORTS_END_START_Pos)
 
#define SPIM_SHORTS_END_START_Disabled   (0UL)
 
#define SPIM_SHORTS_END_START_Enabled   (1UL)
 
#define SPIM_INTENSET_STARTED_Pos   (19UL)
 
#define SPIM_INTENSET_STARTED_Msk   (0x1UL << SPIM_INTENSET_STARTED_Pos)
 
#define SPIM_INTENSET_STARTED_Disabled   (0UL)
 
#define SPIM_INTENSET_STARTED_Enabled   (1UL)
 
#define SPIM_INTENSET_STARTED_Set   (1UL)
 
#define SPIM_INTENSET_ENDTX_Pos   (8UL)
 
#define SPIM_INTENSET_ENDTX_Msk   (0x1UL << SPIM_INTENSET_ENDTX_Pos)
 
#define SPIM_INTENSET_ENDTX_Disabled   (0UL)
 
#define SPIM_INTENSET_ENDTX_Enabled   (1UL)
 
#define SPIM_INTENSET_ENDTX_Set   (1UL)
 
#define SPIM_INTENSET_END_Pos   (6UL)
 
#define SPIM_INTENSET_END_Msk   (0x1UL << SPIM_INTENSET_END_Pos)
 
#define SPIM_INTENSET_END_Disabled   (0UL)
 
#define SPIM_INTENSET_END_Enabled   (1UL)
 
#define SPIM_INTENSET_END_Set   (1UL)
 
#define SPIM_INTENSET_ENDRX_Pos   (4UL)
 
#define SPIM_INTENSET_ENDRX_Msk   (0x1UL << SPIM_INTENSET_ENDRX_Pos)
 
#define SPIM_INTENSET_ENDRX_Disabled   (0UL)
 
#define SPIM_INTENSET_ENDRX_Enabled   (1UL)
 
#define SPIM_INTENSET_ENDRX_Set   (1UL)
 
#define SPIM_INTENSET_STOPPED_Pos   (1UL)
 
#define SPIM_INTENSET_STOPPED_Msk   (0x1UL << SPIM_INTENSET_STOPPED_Pos)
 
#define SPIM_INTENSET_STOPPED_Disabled   (0UL)
 
#define SPIM_INTENSET_STOPPED_Enabled   (1UL)
 
#define SPIM_INTENSET_STOPPED_Set   (1UL)
 
#define SPIM_INTENCLR_STARTED_Pos   (19UL)
 
#define SPIM_INTENCLR_STARTED_Msk   (0x1UL << SPIM_INTENCLR_STARTED_Pos)
 
#define SPIM_INTENCLR_STARTED_Disabled   (0UL)
 
#define SPIM_INTENCLR_STARTED_Enabled   (1UL)
 
#define SPIM_INTENCLR_STARTED_Clear   (1UL)
 
#define SPIM_INTENCLR_ENDTX_Pos   (8UL)
 
#define SPIM_INTENCLR_ENDTX_Msk   (0x1UL << SPIM_INTENCLR_ENDTX_Pos)
 
#define SPIM_INTENCLR_ENDTX_Disabled   (0UL)
 
#define SPIM_INTENCLR_ENDTX_Enabled   (1UL)
 
#define SPIM_INTENCLR_ENDTX_Clear   (1UL)
 
#define SPIM_INTENCLR_END_Pos   (6UL)
 
#define SPIM_INTENCLR_END_Msk   (0x1UL << SPIM_INTENCLR_END_Pos)
 
#define SPIM_INTENCLR_END_Disabled   (0UL)
 
#define SPIM_INTENCLR_END_Enabled   (1UL)
 
#define SPIM_INTENCLR_END_Clear   (1UL)
 
#define SPIM_INTENCLR_ENDRX_Pos   (4UL)
 
#define SPIM_INTENCLR_ENDRX_Msk   (0x1UL << SPIM_INTENCLR_ENDRX_Pos)
 
#define SPIM_INTENCLR_ENDRX_Disabled   (0UL)
 
#define SPIM_INTENCLR_ENDRX_Enabled   (1UL)
 
#define SPIM_INTENCLR_ENDRX_Clear   (1UL)
 
#define SPIM_INTENCLR_STOPPED_Pos   (1UL)
 
#define SPIM_INTENCLR_STOPPED_Msk   (0x1UL << SPIM_INTENCLR_STOPPED_Pos)
 
#define SPIM_INTENCLR_STOPPED_Disabled   (0UL)
 
#define SPIM_INTENCLR_STOPPED_Enabled   (1UL)
 
#define SPIM_INTENCLR_STOPPED_Clear   (1UL)
 
#define SPIM_ENABLE_ENABLE_Pos   (0UL)
 
#define SPIM_ENABLE_ENABLE_Msk   (0xFUL << SPIM_ENABLE_ENABLE_Pos)
 
#define SPIM_ENABLE_ENABLE_Disabled   (0UL)
 
#define SPIM_ENABLE_ENABLE_Enabled   (7UL)
 
#define SPIM_PSEL_SCK_CONNECT_Pos   (31UL)
 
#define SPIM_PSEL_SCK_CONNECT_Msk   (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos)
 
#define SPIM_PSEL_SCK_CONNECT_Connected   (0UL)
 
#define SPIM_PSEL_SCK_CONNECT_Disconnected   (1UL)
 
#define SPIM_PSEL_SCK_PIN_Pos   (0UL)
 
#define SPIM_PSEL_SCK_PIN_Msk   (0x1FUL << SPIM_PSEL_SCK_PIN_Pos)
 
#define SPIM_PSEL_MOSI_CONNECT_Pos   (31UL)
 
#define SPIM_PSEL_MOSI_CONNECT_Msk   (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos)
 
#define SPIM_PSEL_MOSI_CONNECT_Connected   (0UL)
 
#define SPIM_PSEL_MOSI_CONNECT_Disconnected   (1UL)
 
#define SPIM_PSEL_MOSI_PIN_Pos   (0UL)
 
#define SPIM_PSEL_MOSI_PIN_Msk   (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos)
 
#define SPIM_PSEL_MISO_CONNECT_Pos   (31UL)
 
#define SPIM_PSEL_MISO_CONNECT_Msk   (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos)
 
#define SPIM_PSEL_MISO_CONNECT_Connected   (0UL)
 
#define SPIM_PSEL_MISO_CONNECT_Disconnected   (1UL)
 
#define SPIM_PSEL_MISO_PIN_Pos   (0UL)
 
#define SPIM_PSEL_MISO_PIN_Msk   (0x1FUL << SPIM_PSEL_MISO_PIN_Pos)
 
#define SPIM_FREQUENCY_FREQUENCY_Pos   (0UL)
 
#define SPIM_FREQUENCY_FREQUENCY_Msk   (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos)
 
#define SPIM_FREQUENCY_FREQUENCY_K125   (0x02000000UL)
 
#define SPIM_FREQUENCY_FREQUENCY_K250   (0x04000000UL)
 
#define SPIM_FREQUENCY_FREQUENCY_K500   (0x08000000UL)
 
#define SPIM_FREQUENCY_FREQUENCY_M1   (0x10000000UL)
 
#define SPIM_FREQUENCY_FREQUENCY_M2   (0x20000000UL)
 
#define SPIM_FREQUENCY_FREQUENCY_M4   (0x40000000UL)
 
#define SPIM_FREQUENCY_FREQUENCY_M8   (0x80000000UL)
 
#define SPIM_RXD_PTR_PTR_Pos   (0UL)
 
#define SPIM_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos)
 
#define SPIM_RXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define SPIM_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos)
 
#define SPIM_RXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define SPIM_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos)
 
#define SPIM_RXD_LIST_LIST_Pos   (0UL)
 
#define SPIM_RXD_LIST_LIST_Msk   (0x7UL << SPIM_RXD_LIST_LIST_Pos)
 
#define SPIM_RXD_LIST_LIST_Disabled   (0UL)
 
#define SPIM_RXD_LIST_LIST_ArrayList   (1UL)
 
#define SPIM_TXD_PTR_PTR_Pos   (0UL)
 
#define SPIM_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos)
 
#define SPIM_TXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define SPIM_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos)
 
#define SPIM_TXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define SPIM_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos)
 
#define SPIM_TXD_LIST_LIST_Pos   (0UL)
 
#define SPIM_TXD_LIST_LIST_Msk   (0x7UL << SPIM_TXD_LIST_LIST_Pos)
 
#define SPIM_TXD_LIST_LIST_Disabled   (0UL)
 
#define SPIM_TXD_LIST_LIST_ArrayList   (1UL)
 
#define SPIM_CONFIG_CPOL_Pos   (2UL)
 
#define SPIM_CONFIG_CPOL_Msk   (0x1UL << SPIM_CONFIG_CPOL_Pos)
 
#define SPIM_CONFIG_CPOL_ActiveHigh   (0UL)
 
#define SPIM_CONFIG_CPOL_ActiveLow   (1UL)
 
#define SPIM_CONFIG_CPHA_Pos   (1UL)
 
#define SPIM_CONFIG_CPHA_Msk   (0x1UL << SPIM_CONFIG_CPHA_Pos)
 
#define SPIM_CONFIG_CPHA_Leading   (0UL)
 
#define SPIM_CONFIG_CPHA_Trailing   (1UL)
 
#define SPIM_CONFIG_ORDER_Pos   (0UL)
 
#define SPIM_CONFIG_ORDER_Msk   (0x1UL << SPIM_CONFIG_ORDER_Pos)
 
#define SPIM_CONFIG_ORDER_MsbFirst   (0UL)
 
#define SPIM_CONFIG_ORDER_LsbFirst   (1UL)
 
#define SPIM_ORC_ORC_Pos   (0UL)
 
#define SPIM_ORC_ORC_Msk   (0xFFUL << SPIM_ORC_ORC_Pos)
 
#define SPIS_SHORTS_END_ACQUIRE_Pos   (2UL)
 
#define SPIS_SHORTS_END_ACQUIRE_Msk   (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos)
 
#define SPIS_SHORTS_END_ACQUIRE_Disabled   (0UL)
 
#define SPIS_SHORTS_END_ACQUIRE_Enabled   (1UL)
 
#define SPIS_INTENSET_ACQUIRED_Pos   (10UL)
 
#define SPIS_INTENSET_ACQUIRED_Msk   (0x1UL << SPIS_INTENSET_ACQUIRED_Pos)
 
#define SPIS_INTENSET_ACQUIRED_Disabled   (0UL)
 
#define SPIS_INTENSET_ACQUIRED_Enabled   (1UL)
 
#define SPIS_INTENSET_ACQUIRED_Set   (1UL)
 
#define SPIS_INTENSET_ENDRX_Pos   (4UL)
 
#define SPIS_INTENSET_ENDRX_Msk   (0x1UL << SPIS_INTENSET_ENDRX_Pos)
 
#define SPIS_INTENSET_ENDRX_Disabled   (0UL)
 
#define SPIS_INTENSET_ENDRX_Enabled   (1UL)
 
#define SPIS_INTENSET_ENDRX_Set   (1UL)
 
#define SPIS_INTENSET_END_Pos   (1UL)
 
#define SPIS_INTENSET_END_Msk   (0x1UL << SPIS_INTENSET_END_Pos)
 
#define SPIS_INTENSET_END_Disabled   (0UL)
 
#define SPIS_INTENSET_END_Enabled   (1UL)
 
#define SPIS_INTENSET_END_Set   (1UL)
 
#define SPIS_INTENCLR_ACQUIRED_Pos   (10UL)
 
#define SPIS_INTENCLR_ACQUIRED_Msk   (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos)
 
#define SPIS_INTENCLR_ACQUIRED_Disabled   (0UL)
 
#define SPIS_INTENCLR_ACQUIRED_Enabled   (1UL)
 
#define SPIS_INTENCLR_ACQUIRED_Clear   (1UL)
 
#define SPIS_INTENCLR_ENDRX_Pos   (4UL)
 
#define SPIS_INTENCLR_ENDRX_Msk   (0x1UL << SPIS_INTENCLR_ENDRX_Pos)
 
#define SPIS_INTENCLR_ENDRX_Disabled   (0UL)
 
#define SPIS_INTENCLR_ENDRX_Enabled   (1UL)
 
#define SPIS_INTENCLR_ENDRX_Clear   (1UL)
 
#define SPIS_INTENCLR_END_Pos   (1UL)
 
#define SPIS_INTENCLR_END_Msk   (0x1UL << SPIS_INTENCLR_END_Pos)
 
#define SPIS_INTENCLR_END_Disabled   (0UL)
 
#define SPIS_INTENCLR_END_Enabled   (1UL)
 
#define SPIS_INTENCLR_END_Clear   (1UL)
 
#define SPIS_SEMSTAT_SEMSTAT_Pos   (0UL)
 
#define SPIS_SEMSTAT_SEMSTAT_Msk   (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos)
 
#define SPIS_SEMSTAT_SEMSTAT_Free   (0UL)
 
#define SPIS_SEMSTAT_SEMSTAT_CPU   (1UL)
 
#define SPIS_SEMSTAT_SEMSTAT_SPIS   (2UL)
 
#define SPIS_SEMSTAT_SEMSTAT_CPUPending   (3UL)
 
#define SPIS_STATUS_OVERFLOW_Pos   (1UL)
 
#define SPIS_STATUS_OVERFLOW_Msk   (0x1UL << SPIS_STATUS_OVERFLOW_Pos)
 
#define SPIS_STATUS_OVERFLOW_NotPresent   (0UL)
 
#define SPIS_STATUS_OVERFLOW_Present   (1UL)
 
#define SPIS_STATUS_OVERFLOW_Clear   (1UL)
 
#define SPIS_STATUS_OVERREAD_Pos   (0UL)
 
#define SPIS_STATUS_OVERREAD_Msk   (0x1UL << SPIS_STATUS_OVERREAD_Pos)
 
#define SPIS_STATUS_OVERREAD_NotPresent   (0UL)
 
#define SPIS_STATUS_OVERREAD_Present   (1UL)
 
#define SPIS_STATUS_OVERREAD_Clear   (1UL)
 
#define SPIS_ENABLE_ENABLE_Pos   (0UL)
 
#define SPIS_ENABLE_ENABLE_Msk   (0xFUL << SPIS_ENABLE_ENABLE_Pos)
 
#define SPIS_ENABLE_ENABLE_Disabled   (0UL)
 
#define SPIS_ENABLE_ENABLE_Enabled   (2UL)
 
#define SPIS_PSEL_SCK_CONNECT_Pos   (31UL)
 
#define SPIS_PSEL_SCK_CONNECT_Msk   (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos)
 
#define SPIS_PSEL_SCK_CONNECT_Connected   (0UL)
 
#define SPIS_PSEL_SCK_CONNECT_Disconnected   (1UL)
 
#define SPIS_PSEL_SCK_PIN_Pos   (0UL)
 
#define SPIS_PSEL_SCK_PIN_Msk   (0x1FUL << SPIS_PSEL_SCK_PIN_Pos)
 
#define SPIS_PSEL_MISO_CONNECT_Pos   (31UL)
 
#define SPIS_PSEL_MISO_CONNECT_Msk   (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos)
 
#define SPIS_PSEL_MISO_CONNECT_Connected   (0UL)
 
#define SPIS_PSEL_MISO_CONNECT_Disconnected   (1UL)
 
#define SPIS_PSEL_MISO_PIN_Pos   (0UL)
 
#define SPIS_PSEL_MISO_PIN_Msk   (0x1FUL << SPIS_PSEL_MISO_PIN_Pos)
 
#define SPIS_PSEL_MOSI_CONNECT_Pos   (31UL)
 
#define SPIS_PSEL_MOSI_CONNECT_Msk   (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos)
 
#define SPIS_PSEL_MOSI_CONNECT_Connected   (0UL)
 
#define SPIS_PSEL_MOSI_CONNECT_Disconnected   (1UL)
 
#define SPIS_PSEL_MOSI_PIN_Pos   (0UL)
 
#define SPIS_PSEL_MOSI_PIN_Msk   (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos)
 
#define SPIS_PSEL_CSN_CONNECT_Pos   (31UL)
 
#define SPIS_PSEL_CSN_CONNECT_Msk   (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos)
 
#define SPIS_PSEL_CSN_CONNECT_Connected   (0UL)
 
#define SPIS_PSEL_CSN_CONNECT_Disconnected   (1UL)
 
#define SPIS_PSEL_CSN_PIN_Pos   (0UL)
 
#define SPIS_PSEL_CSN_PIN_Msk   (0x1FUL << SPIS_PSEL_CSN_PIN_Pos)
 
#define SPIS_RXD_PTR_PTR_Pos   (0UL)
 
#define SPIS_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos)
 
#define SPIS_RXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define SPIS_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos)
 
#define SPIS_RXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define SPIS_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos)
 
#define SPIS_TXD_PTR_PTR_Pos   (0UL)
 
#define SPIS_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos)
 
#define SPIS_TXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define SPIS_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos)
 
#define SPIS_TXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define SPIS_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos)
 
#define SPIS_CONFIG_CPOL_Pos   (2UL)
 
#define SPIS_CONFIG_CPOL_Msk   (0x1UL << SPIS_CONFIG_CPOL_Pos)
 
#define SPIS_CONFIG_CPOL_ActiveHigh   (0UL)
 
#define SPIS_CONFIG_CPOL_ActiveLow   (1UL)
 
#define SPIS_CONFIG_CPHA_Pos   (1UL)
 
#define SPIS_CONFIG_CPHA_Msk   (0x1UL << SPIS_CONFIG_CPHA_Pos)
 
#define SPIS_CONFIG_CPHA_Leading   (0UL)
 
#define SPIS_CONFIG_CPHA_Trailing   (1UL)
 
#define SPIS_CONFIG_ORDER_Pos   (0UL)
 
#define SPIS_CONFIG_ORDER_Msk   (0x1UL << SPIS_CONFIG_ORDER_Pos)
 
#define SPIS_CONFIG_ORDER_MsbFirst   (0UL)
 
#define SPIS_CONFIG_ORDER_LsbFirst   (1UL)
 
#define SPIS_DEF_DEF_Pos   (0UL)
 
#define SPIS_DEF_DEF_Msk   (0xFFUL << SPIS_DEF_DEF_Pos)
 
#define SPIS_ORC_ORC_Pos   (0UL)
 
#define SPIS_ORC_ORC_Msk   (0xFFUL << SPIS_ORC_ORC_Pos)
 
#define TEMP_INTENSET_DATARDY_Pos   (0UL)
 
#define TEMP_INTENSET_DATARDY_Msk   (0x1UL << TEMP_INTENSET_DATARDY_Pos)
 
#define TEMP_INTENSET_DATARDY_Disabled   (0UL)
 
#define TEMP_INTENSET_DATARDY_Enabled   (1UL)
 
#define TEMP_INTENSET_DATARDY_Set   (1UL)
 
#define TEMP_INTENCLR_DATARDY_Pos   (0UL)
 
#define TEMP_INTENCLR_DATARDY_Msk   (0x1UL << TEMP_INTENCLR_DATARDY_Pos)
 
#define TEMP_INTENCLR_DATARDY_Disabled   (0UL)
 
#define TEMP_INTENCLR_DATARDY_Enabled   (1UL)
 
#define TEMP_INTENCLR_DATARDY_Clear   (1UL)
 
#define TEMP_TEMP_TEMP_Pos   (0UL)
 
#define TEMP_TEMP_TEMP_Msk   (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos)
 
#define TEMP_A0_A0_Pos   (0UL)
 
#define TEMP_A0_A0_Msk   (0xFFFUL << TEMP_A0_A0_Pos)
 
#define TEMP_A1_A1_Pos   (0UL)
 
#define TEMP_A1_A1_Msk   (0xFFFUL << TEMP_A1_A1_Pos)
 
#define TEMP_A2_A2_Pos   (0UL)
 
#define TEMP_A2_A2_Msk   (0xFFFUL << TEMP_A2_A2_Pos)
 
#define TEMP_A3_A3_Pos   (0UL)
 
#define TEMP_A3_A3_Msk   (0xFFFUL << TEMP_A3_A3_Pos)
 
#define TEMP_A4_A4_Pos   (0UL)
 
#define TEMP_A4_A4_Msk   (0xFFFUL << TEMP_A4_A4_Pos)
 
#define TEMP_A5_A5_Pos   (0UL)
 
#define TEMP_A5_A5_Msk   (0xFFFUL << TEMP_A5_A5_Pos)
 
#define TEMP_B0_B0_Pos   (0UL)
 
#define TEMP_B0_B0_Msk   (0x3FFFUL << TEMP_B0_B0_Pos)
 
#define TEMP_B1_B1_Pos   (0UL)
 
#define TEMP_B1_B1_Msk   (0x3FFFUL << TEMP_B1_B1_Pos)
 
#define TEMP_B2_B2_Pos   (0UL)
 
#define TEMP_B2_B2_Msk   (0x3FFFUL << TEMP_B2_B2_Pos)
 
#define TEMP_B3_B3_Pos   (0UL)
 
#define TEMP_B3_B3_Msk   (0x3FFFUL << TEMP_B3_B3_Pos)
 
#define TEMP_B4_B4_Pos   (0UL)
 
#define TEMP_B4_B4_Msk   (0x3FFFUL << TEMP_B4_B4_Pos)
 
#define TEMP_B5_B5_Pos   (0UL)
 
#define TEMP_B5_B5_Msk   (0x3FFFUL << TEMP_B5_B5_Pos)
 
#define TEMP_T0_T0_Pos   (0UL)
 
#define TEMP_T0_T0_Msk   (0xFFUL << TEMP_T0_T0_Pos)
 
#define TEMP_T1_T1_Pos   (0UL)
 
#define TEMP_T1_T1_Msk   (0xFFUL << TEMP_T1_T1_Pos)
 
#define TEMP_T2_T2_Pos   (0UL)
 
#define TEMP_T2_T2_Msk   (0xFFUL << TEMP_T2_T2_Pos)
 
#define TEMP_T3_T3_Pos   (0UL)
 
#define TEMP_T3_T3_Msk   (0xFFUL << TEMP_T3_T3_Pos)
 
#define TEMP_T4_T4_Pos   (0UL)
 
#define TEMP_T4_T4_Msk   (0xFFUL << TEMP_T4_T4_Pos)
 
#define TIMER_SHORTS_COMPARE5_STOP_Pos   (13UL)
 
#define TIMER_SHORTS_COMPARE5_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos)
 
#define TIMER_SHORTS_COMPARE5_STOP_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE5_STOP_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE4_STOP_Pos   (12UL)
 
#define TIMER_SHORTS_COMPARE4_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos)
 
#define TIMER_SHORTS_COMPARE4_STOP_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE4_STOP_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE3_STOP_Pos   (11UL)
 
#define TIMER_SHORTS_COMPARE3_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos)
 
#define TIMER_SHORTS_COMPARE3_STOP_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE3_STOP_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE2_STOP_Pos   (10UL)
 
#define TIMER_SHORTS_COMPARE2_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos)
 
#define TIMER_SHORTS_COMPARE2_STOP_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE2_STOP_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE1_STOP_Pos   (9UL)
 
#define TIMER_SHORTS_COMPARE1_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos)
 
#define TIMER_SHORTS_COMPARE1_STOP_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE1_STOP_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE0_STOP_Pos   (8UL)
 
#define TIMER_SHORTS_COMPARE0_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos)
 
#define TIMER_SHORTS_COMPARE0_STOP_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE0_STOP_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE5_CLEAR_Pos   (5UL)
 
#define TIMER_SHORTS_COMPARE5_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos)
 
#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE4_CLEAR_Pos   (4UL)
 
#define TIMER_SHORTS_COMPARE4_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos)
 
#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE3_CLEAR_Pos   (3UL)
 
#define TIMER_SHORTS_COMPARE3_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos)
 
#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE2_CLEAR_Pos   (2UL)
 
#define TIMER_SHORTS_COMPARE2_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos)
 
#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE1_CLEAR_Pos   (1UL)
 
#define TIMER_SHORTS_COMPARE1_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos)
 
#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled   (1UL)
 
#define TIMER_SHORTS_COMPARE0_CLEAR_Pos   (0UL)
 
#define TIMER_SHORTS_COMPARE0_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos)
 
#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled   (0UL)
 
#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled   (1UL)
 
#define TIMER_INTENSET_COMPARE5_Pos   (21UL)
 
#define TIMER_INTENSET_COMPARE5_Msk   (0x1UL << TIMER_INTENSET_COMPARE5_Pos)
 
#define TIMER_INTENSET_COMPARE5_Disabled   (0UL)
 
#define TIMER_INTENSET_COMPARE5_Enabled   (1UL)
 
#define TIMER_INTENSET_COMPARE5_Set   (1UL)
 
#define TIMER_INTENSET_COMPARE4_Pos   (20UL)
 
#define TIMER_INTENSET_COMPARE4_Msk   (0x1UL << TIMER_INTENSET_COMPARE4_Pos)
 
#define TIMER_INTENSET_COMPARE4_Disabled   (0UL)
 
#define TIMER_INTENSET_COMPARE4_Enabled   (1UL)
 
#define TIMER_INTENSET_COMPARE4_Set   (1UL)
 
#define TIMER_INTENSET_COMPARE3_Pos   (19UL)
 
#define TIMER_INTENSET_COMPARE3_Msk   (0x1UL << TIMER_INTENSET_COMPARE3_Pos)
 
#define TIMER_INTENSET_COMPARE3_Disabled   (0UL)
 
#define TIMER_INTENSET_COMPARE3_Enabled   (1UL)
 
#define TIMER_INTENSET_COMPARE3_Set   (1UL)
 
#define TIMER_INTENSET_COMPARE2_Pos   (18UL)
 
#define TIMER_INTENSET_COMPARE2_Msk   (0x1UL << TIMER_INTENSET_COMPARE2_Pos)
 
#define TIMER_INTENSET_COMPARE2_Disabled   (0UL)
 
#define TIMER_INTENSET_COMPARE2_Enabled   (1UL)
 
#define TIMER_INTENSET_COMPARE2_Set   (1UL)
 
#define TIMER_INTENSET_COMPARE1_Pos   (17UL)
 
#define TIMER_INTENSET_COMPARE1_Msk   (0x1UL << TIMER_INTENSET_COMPARE1_Pos)
 
#define TIMER_INTENSET_COMPARE1_Disabled   (0UL)
 
#define TIMER_INTENSET_COMPARE1_Enabled   (1UL)
 
#define TIMER_INTENSET_COMPARE1_Set   (1UL)
 
#define TIMER_INTENSET_COMPARE0_Pos   (16UL)
 
#define TIMER_INTENSET_COMPARE0_Msk   (0x1UL << TIMER_INTENSET_COMPARE0_Pos)
 
#define TIMER_INTENSET_COMPARE0_Disabled   (0UL)
 
#define TIMER_INTENSET_COMPARE0_Enabled   (1UL)
 
#define TIMER_INTENSET_COMPARE0_Set   (1UL)
 
#define TIMER_INTENCLR_COMPARE5_Pos   (21UL)
 
#define TIMER_INTENCLR_COMPARE5_Msk   (0x1UL << TIMER_INTENCLR_COMPARE5_Pos)
 
#define TIMER_INTENCLR_COMPARE5_Disabled   (0UL)
 
#define TIMER_INTENCLR_COMPARE5_Enabled   (1UL)
 
#define TIMER_INTENCLR_COMPARE5_Clear   (1UL)
 
#define TIMER_INTENCLR_COMPARE4_Pos   (20UL)
 
#define TIMER_INTENCLR_COMPARE4_Msk   (0x1UL << TIMER_INTENCLR_COMPARE4_Pos)
 
#define TIMER_INTENCLR_COMPARE4_Disabled   (0UL)
 
#define TIMER_INTENCLR_COMPARE4_Enabled   (1UL)
 
#define TIMER_INTENCLR_COMPARE4_Clear   (1UL)
 
#define TIMER_INTENCLR_COMPARE3_Pos   (19UL)
 
#define TIMER_INTENCLR_COMPARE3_Msk   (0x1UL << TIMER_INTENCLR_COMPARE3_Pos)
 
#define TIMER_INTENCLR_COMPARE3_Disabled   (0UL)
 
#define TIMER_INTENCLR_COMPARE3_Enabled   (1UL)
 
#define TIMER_INTENCLR_COMPARE3_Clear   (1UL)
 
#define TIMER_INTENCLR_COMPARE2_Pos   (18UL)
 
#define TIMER_INTENCLR_COMPARE2_Msk   (0x1UL << TIMER_INTENCLR_COMPARE2_Pos)
 
#define TIMER_INTENCLR_COMPARE2_Disabled   (0UL)
 
#define TIMER_INTENCLR_COMPARE2_Enabled   (1UL)
 
#define TIMER_INTENCLR_COMPARE2_Clear   (1UL)
 
#define TIMER_INTENCLR_COMPARE1_Pos   (17UL)
 
#define TIMER_INTENCLR_COMPARE1_Msk   (0x1UL << TIMER_INTENCLR_COMPARE1_Pos)
 
#define TIMER_INTENCLR_COMPARE1_Disabled   (0UL)
 
#define TIMER_INTENCLR_COMPARE1_Enabled   (1UL)
 
#define TIMER_INTENCLR_COMPARE1_Clear   (1UL)
 
#define TIMER_INTENCLR_COMPARE0_Pos   (16UL)
 
#define TIMER_INTENCLR_COMPARE0_Msk   (0x1UL << TIMER_INTENCLR_COMPARE0_Pos)
 
#define TIMER_INTENCLR_COMPARE0_Disabled   (0UL)
 
#define TIMER_INTENCLR_COMPARE0_Enabled   (1UL)
 
#define TIMER_INTENCLR_COMPARE0_Clear   (1UL)
 
#define TIMER_MODE_MODE_Pos   (0UL)
 
#define TIMER_MODE_MODE_Msk   (0x3UL << TIMER_MODE_MODE_Pos)
 
#define TIMER_MODE_MODE_Timer   (0UL)
 
#define TIMER_MODE_MODE_Counter   (1UL)
 
#define TIMER_MODE_MODE_LowPowerCounter   (2UL)
 
#define TIMER_BITMODE_BITMODE_Pos   (0UL)
 
#define TIMER_BITMODE_BITMODE_Msk   (0x3UL << TIMER_BITMODE_BITMODE_Pos)
 
#define TIMER_BITMODE_BITMODE_16Bit   (0UL)
 
#define TIMER_BITMODE_BITMODE_08Bit   (1UL)
 
#define TIMER_BITMODE_BITMODE_24Bit   (2UL)
 
#define TIMER_BITMODE_BITMODE_32Bit   (3UL)
 
#define TIMER_PRESCALER_PRESCALER_Pos   (0UL)
 
#define TIMER_PRESCALER_PRESCALER_Msk   (0xFUL << TIMER_PRESCALER_PRESCALER_Pos)
 
#define TIMER_CC_CC_Pos   (0UL)
 
#define TIMER_CC_CC_Msk   (0xFFFFFFFFUL << TIMER_CC_CC_Pos)
 
#define TWI_SHORTS_BB_STOP_Pos   (1UL)
 
#define TWI_SHORTS_BB_STOP_Msk   (0x1UL << TWI_SHORTS_BB_STOP_Pos)
 
#define TWI_SHORTS_BB_STOP_Disabled   (0UL)
 
#define TWI_SHORTS_BB_STOP_Enabled   (1UL)
 
#define TWI_SHORTS_BB_SUSPEND_Pos   (0UL)
 
#define TWI_SHORTS_BB_SUSPEND_Msk   (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos)
 
#define TWI_SHORTS_BB_SUSPEND_Disabled   (0UL)
 
#define TWI_SHORTS_BB_SUSPEND_Enabled   (1UL)
 
#define TWI_INTENSET_SUSPENDED_Pos   (18UL)
 
#define TWI_INTENSET_SUSPENDED_Msk   (0x1UL << TWI_INTENSET_SUSPENDED_Pos)
 
#define TWI_INTENSET_SUSPENDED_Disabled   (0UL)
 
#define TWI_INTENSET_SUSPENDED_Enabled   (1UL)
 
#define TWI_INTENSET_SUSPENDED_Set   (1UL)
 
#define TWI_INTENSET_BB_Pos   (14UL)
 
#define TWI_INTENSET_BB_Msk   (0x1UL << TWI_INTENSET_BB_Pos)
 
#define TWI_INTENSET_BB_Disabled   (0UL)
 
#define TWI_INTENSET_BB_Enabled   (1UL)
 
#define TWI_INTENSET_BB_Set   (1UL)
 
#define TWI_INTENSET_ERROR_Pos   (9UL)
 
#define TWI_INTENSET_ERROR_Msk   (0x1UL << TWI_INTENSET_ERROR_Pos)
 
#define TWI_INTENSET_ERROR_Disabled   (0UL)
 
#define TWI_INTENSET_ERROR_Enabled   (1UL)
 
#define TWI_INTENSET_ERROR_Set   (1UL)
 
#define TWI_INTENSET_TXDSENT_Pos   (7UL)
 
#define TWI_INTENSET_TXDSENT_Msk   (0x1UL << TWI_INTENSET_TXDSENT_Pos)
 
#define TWI_INTENSET_TXDSENT_Disabled   (0UL)
 
#define TWI_INTENSET_TXDSENT_Enabled   (1UL)
 
#define TWI_INTENSET_TXDSENT_Set   (1UL)
 
#define TWI_INTENSET_RXDREADY_Pos   (2UL)
 
#define TWI_INTENSET_RXDREADY_Msk   (0x1UL << TWI_INTENSET_RXDREADY_Pos)
 
#define TWI_INTENSET_RXDREADY_Disabled   (0UL)
 
#define TWI_INTENSET_RXDREADY_Enabled   (1UL)
 
#define TWI_INTENSET_RXDREADY_Set   (1UL)
 
#define TWI_INTENSET_STOPPED_Pos   (1UL)
 
#define TWI_INTENSET_STOPPED_Msk   (0x1UL << TWI_INTENSET_STOPPED_Pos)
 
#define TWI_INTENSET_STOPPED_Disabled   (0UL)
 
#define TWI_INTENSET_STOPPED_Enabled   (1UL)
 
#define TWI_INTENSET_STOPPED_Set   (1UL)
 
#define TWI_INTENCLR_SUSPENDED_Pos   (18UL)
 
#define TWI_INTENCLR_SUSPENDED_Msk   (0x1UL << TWI_INTENCLR_SUSPENDED_Pos)
 
#define TWI_INTENCLR_SUSPENDED_Disabled   (0UL)
 
#define TWI_INTENCLR_SUSPENDED_Enabled   (1UL)
 
#define TWI_INTENCLR_SUSPENDED_Clear   (1UL)
 
#define TWI_INTENCLR_BB_Pos   (14UL)
 
#define TWI_INTENCLR_BB_Msk   (0x1UL << TWI_INTENCLR_BB_Pos)
 
#define TWI_INTENCLR_BB_Disabled   (0UL)
 
#define TWI_INTENCLR_BB_Enabled   (1UL)
 
#define TWI_INTENCLR_BB_Clear   (1UL)
 
#define TWI_INTENCLR_ERROR_Pos   (9UL)
 
#define TWI_INTENCLR_ERROR_Msk   (0x1UL << TWI_INTENCLR_ERROR_Pos)
 
#define TWI_INTENCLR_ERROR_Disabled   (0UL)
 
#define TWI_INTENCLR_ERROR_Enabled   (1UL)
 
#define TWI_INTENCLR_ERROR_Clear   (1UL)
 
#define TWI_INTENCLR_TXDSENT_Pos   (7UL)
 
#define TWI_INTENCLR_TXDSENT_Msk   (0x1UL << TWI_INTENCLR_TXDSENT_Pos)
 
#define TWI_INTENCLR_TXDSENT_Disabled   (0UL)
 
#define TWI_INTENCLR_TXDSENT_Enabled   (1UL)
 
#define TWI_INTENCLR_TXDSENT_Clear   (1UL)
 
#define TWI_INTENCLR_RXDREADY_Pos   (2UL)
 
#define TWI_INTENCLR_RXDREADY_Msk   (0x1UL << TWI_INTENCLR_RXDREADY_Pos)
 
#define TWI_INTENCLR_RXDREADY_Disabled   (0UL)
 
#define TWI_INTENCLR_RXDREADY_Enabled   (1UL)
 
#define TWI_INTENCLR_RXDREADY_Clear   (1UL)
 
#define TWI_INTENCLR_STOPPED_Pos   (1UL)
 
#define TWI_INTENCLR_STOPPED_Msk   (0x1UL << TWI_INTENCLR_STOPPED_Pos)
 
#define TWI_INTENCLR_STOPPED_Disabled   (0UL)
 
#define TWI_INTENCLR_STOPPED_Enabled   (1UL)
 
#define TWI_INTENCLR_STOPPED_Clear   (1UL)
 
#define TWI_ERRORSRC_DNACK_Pos   (2UL)
 
#define TWI_ERRORSRC_DNACK_Msk   (0x1UL << TWI_ERRORSRC_DNACK_Pos)
 
#define TWI_ERRORSRC_DNACK_NotPresent   (0UL)
 
#define TWI_ERRORSRC_DNACK_Present   (1UL)
 
#define TWI_ERRORSRC_DNACK_Clear   (1UL)
 
#define TWI_ERRORSRC_ANACK_Pos   (1UL)
 
#define TWI_ERRORSRC_ANACK_Msk   (0x1UL << TWI_ERRORSRC_ANACK_Pos)
 
#define TWI_ERRORSRC_ANACK_NotPresent   (0UL)
 
#define TWI_ERRORSRC_ANACK_Present   (1UL)
 
#define TWI_ERRORSRC_ANACK_Clear   (1UL)
 
#define TWI_ERRORSRC_OVERRUN_Pos   (0UL)
 
#define TWI_ERRORSRC_OVERRUN_Msk   (0x1UL << TWI_ERRORSRC_OVERRUN_Pos)
 
#define TWI_ERRORSRC_OVERRUN_NotPresent   (0UL)
 
#define TWI_ERRORSRC_OVERRUN_Present   (1UL)
 
#define TWI_ERRORSRC_OVERRUN_Clear   (1UL)
 
#define TWI_ENABLE_ENABLE_Pos   (0UL)
 
#define TWI_ENABLE_ENABLE_Msk   (0xFUL << TWI_ENABLE_ENABLE_Pos)
 
#define TWI_ENABLE_ENABLE_Disabled   (0UL)
 
#define TWI_ENABLE_ENABLE_Enabled   (5UL)
 
#define TWI_PSELSCL_PSELSCL_Pos   (0UL)
 
#define TWI_PSELSCL_PSELSCL_Msk   (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos)
 
#define TWI_PSELSCL_PSELSCL_Disconnected   (0xFFFFFFFFUL)
 
#define TWI_PSELSDA_PSELSDA_Pos   (0UL)
 
#define TWI_PSELSDA_PSELSDA_Msk   (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos)
 
#define TWI_PSELSDA_PSELSDA_Disconnected   (0xFFFFFFFFUL)
 
#define TWI_RXD_RXD_Pos   (0UL)
 
#define TWI_RXD_RXD_Msk   (0xFFUL << TWI_RXD_RXD_Pos)
 
#define TWI_TXD_TXD_Pos   (0UL)
 
#define TWI_TXD_TXD_Msk   (0xFFUL << TWI_TXD_TXD_Pos)
 
#define TWI_FREQUENCY_FREQUENCY_Pos   (0UL)
 
#define TWI_FREQUENCY_FREQUENCY_Msk   (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos)
 
#define TWI_FREQUENCY_FREQUENCY_K100   (0x01980000UL)
 
#define TWI_FREQUENCY_FREQUENCY_K250   (0x04000000UL)
 
#define TWI_FREQUENCY_FREQUENCY_K400   (0x06680000UL)
 
#define TWI_ADDRESS_ADDRESS_Pos   (0UL)
 
#define TWI_ADDRESS_ADDRESS_Msk   (0x7FUL << TWI_ADDRESS_ADDRESS_Pos)
 
#define TWIM_SHORTS_LASTRX_STOP_Pos   (12UL)
 
#define TWIM_SHORTS_LASTRX_STOP_Msk   (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos)
 
#define TWIM_SHORTS_LASTRX_STOP_Disabled   (0UL)
 
#define TWIM_SHORTS_LASTRX_STOP_Enabled   (1UL)
 
#define TWIM_SHORTS_LASTRX_STARTTX_Pos   (10UL)
 
#define TWIM_SHORTS_LASTRX_STARTTX_Msk   (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos)
 
#define TWIM_SHORTS_LASTRX_STARTTX_Disabled   (0UL)
 
#define TWIM_SHORTS_LASTRX_STARTTX_Enabled   (1UL)
 
#define TWIM_SHORTS_LASTTX_STOP_Pos   (9UL)
 
#define TWIM_SHORTS_LASTTX_STOP_Msk   (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos)
 
#define TWIM_SHORTS_LASTTX_STOP_Disabled   (0UL)
 
#define TWIM_SHORTS_LASTTX_STOP_Enabled   (1UL)
 
#define TWIM_SHORTS_LASTTX_SUSPEND_Pos   (8UL)
 
#define TWIM_SHORTS_LASTTX_SUSPEND_Msk   (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos)
 
#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled   (0UL)
 
#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled   (1UL)
 
#define TWIM_SHORTS_LASTTX_STARTRX_Pos   (7UL)
 
#define TWIM_SHORTS_LASTTX_STARTRX_Msk   (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos)
 
#define TWIM_SHORTS_LASTTX_STARTRX_Disabled   (0UL)
 
#define TWIM_SHORTS_LASTTX_STARTRX_Enabled   (1UL)
 
#define TWIM_INTEN_LASTTX_Pos   (24UL)
 
#define TWIM_INTEN_LASTTX_Msk   (0x1UL << TWIM_INTEN_LASTTX_Pos)
 
#define TWIM_INTEN_LASTTX_Disabled   (0UL)
 
#define TWIM_INTEN_LASTTX_Enabled   (1UL)
 
#define TWIM_INTEN_LASTRX_Pos   (23UL)
 
#define TWIM_INTEN_LASTRX_Msk   (0x1UL << TWIM_INTEN_LASTRX_Pos)
 
#define TWIM_INTEN_LASTRX_Disabled   (0UL)
 
#define TWIM_INTEN_LASTRX_Enabled   (1UL)
 
#define TWIM_INTEN_TXSTARTED_Pos   (20UL)
 
#define TWIM_INTEN_TXSTARTED_Msk   (0x1UL << TWIM_INTEN_TXSTARTED_Pos)
 
#define TWIM_INTEN_TXSTARTED_Disabled   (0UL)
 
#define TWIM_INTEN_TXSTARTED_Enabled   (1UL)
 
#define TWIM_INTEN_RXSTARTED_Pos   (19UL)
 
#define TWIM_INTEN_RXSTARTED_Msk   (0x1UL << TWIM_INTEN_RXSTARTED_Pos)
 
#define TWIM_INTEN_RXSTARTED_Disabled   (0UL)
 
#define TWIM_INTEN_RXSTARTED_Enabled   (1UL)
 
#define TWIM_INTEN_SUSPENDED_Pos   (18UL)
 
#define TWIM_INTEN_SUSPENDED_Msk   (0x1UL << TWIM_INTEN_SUSPENDED_Pos)
 
#define TWIM_INTEN_SUSPENDED_Disabled   (0UL)
 
#define TWIM_INTEN_SUSPENDED_Enabled   (1UL)
 
#define TWIM_INTEN_ERROR_Pos   (9UL)
 
#define TWIM_INTEN_ERROR_Msk   (0x1UL << TWIM_INTEN_ERROR_Pos)
 
#define TWIM_INTEN_ERROR_Disabled   (0UL)
 
#define TWIM_INTEN_ERROR_Enabled   (1UL)
 
#define TWIM_INTEN_STOPPED_Pos   (1UL)
 
#define TWIM_INTEN_STOPPED_Msk   (0x1UL << TWIM_INTEN_STOPPED_Pos)
 
#define TWIM_INTEN_STOPPED_Disabled   (0UL)
 
#define TWIM_INTEN_STOPPED_Enabled   (1UL)
 
#define TWIM_INTENSET_LASTTX_Pos   (24UL)
 
#define TWIM_INTENSET_LASTTX_Msk   (0x1UL << TWIM_INTENSET_LASTTX_Pos)
 
#define TWIM_INTENSET_LASTTX_Disabled   (0UL)
 
#define TWIM_INTENSET_LASTTX_Enabled   (1UL)
 
#define TWIM_INTENSET_LASTTX_Set   (1UL)
 
#define TWIM_INTENSET_LASTRX_Pos   (23UL)
 
#define TWIM_INTENSET_LASTRX_Msk   (0x1UL << TWIM_INTENSET_LASTRX_Pos)
 
#define TWIM_INTENSET_LASTRX_Disabled   (0UL)
 
#define TWIM_INTENSET_LASTRX_Enabled   (1UL)
 
#define TWIM_INTENSET_LASTRX_Set   (1UL)
 
#define TWIM_INTENSET_TXSTARTED_Pos   (20UL)
 
#define TWIM_INTENSET_TXSTARTED_Msk   (0x1UL << TWIM_INTENSET_TXSTARTED_Pos)
 
#define TWIM_INTENSET_TXSTARTED_Disabled   (0UL)
 
#define TWIM_INTENSET_TXSTARTED_Enabled   (1UL)
 
#define TWIM_INTENSET_TXSTARTED_Set   (1UL)
 
#define TWIM_INTENSET_RXSTARTED_Pos   (19UL)
 
#define TWIM_INTENSET_RXSTARTED_Msk   (0x1UL << TWIM_INTENSET_RXSTARTED_Pos)
 
#define TWIM_INTENSET_RXSTARTED_Disabled   (0UL)
 
#define TWIM_INTENSET_RXSTARTED_Enabled   (1UL)
 
#define TWIM_INTENSET_RXSTARTED_Set   (1UL)
 
#define TWIM_INTENSET_SUSPENDED_Pos   (18UL)
 
#define TWIM_INTENSET_SUSPENDED_Msk   (0x1UL << TWIM_INTENSET_SUSPENDED_Pos)
 
#define TWIM_INTENSET_SUSPENDED_Disabled   (0UL)
 
#define TWIM_INTENSET_SUSPENDED_Enabled   (1UL)
 
#define TWIM_INTENSET_SUSPENDED_Set   (1UL)
 
#define TWIM_INTENSET_ERROR_Pos   (9UL)
 
#define TWIM_INTENSET_ERROR_Msk   (0x1UL << TWIM_INTENSET_ERROR_Pos)
 
#define TWIM_INTENSET_ERROR_Disabled   (0UL)
 
#define TWIM_INTENSET_ERROR_Enabled   (1UL)
 
#define TWIM_INTENSET_ERROR_Set   (1UL)
 
#define TWIM_INTENSET_STOPPED_Pos   (1UL)
 
#define TWIM_INTENSET_STOPPED_Msk   (0x1UL << TWIM_INTENSET_STOPPED_Pos)
 
#define TWIM_INTENSET_STOPPED_Disabled   (0UL)
 
#define TWIM_INTENSET_STOPPED_Enabled   (1UL)
 
#define TWIM_INTENSET_STOPPED_Set   (1UL)
 
#define TWIM_INTENCLR_LASTTX_Pos   (24UL)
 
#define TWIM_INTENCLR_LASTTX_Msk   (0x1UL << TWIM_INTENCLR_LASTTX_Pos)
 
#define TWIM_INTENCLR_LASTTX_Disabled   (0UL)
 
#define TWIM_INTENCLR_LASTTX_Enabled   (1UL)
 
#define TWIM_INTENCLR_LASTTX_Clear   (1UL)
 
#define TWIM_INTENCLR_LASTRX_Pos   (23UL)
 
#define TWIM_INTENCLR_LASTRX_Msk   (0x1UL << TWIM_INTENCLR_LASTRX_Pos)
 
#define TWIM_INTENCLR_LASTRX_Disabled   (0UL)
 
#define TWIM_INTENCLR_LASTRX_Enabled   (1UL)
 
#define TWIM_INTENCLR_LASTRX_Clear   (1UL)
 
#define TWIM_INTENCLR_TXSTARTED_Pos   (20UL)
 
#define TWIM_INTENCLR_TXSTARTED_Msk   (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos)
 
#define TWIM_INTENCLR_TXSTARTED_Disabled   (0UL)
 
#define TWIM_INTENCLR_TXSTARTED_Enabled   (1UL)
 
#define TWIM_INTENCLR_TXSTARTED_Clear   (1UL)
 
#define TWIM_INTENCLR_RXSTARTED_Pos   (19UL)
 
#define TWIM_INTENCLR_RXSTARTED_Msk   (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos)
 
#define TWIM_INTENCLR_RXSTARTED_Disabled   (0UL)
 
#define TWIM_INTENCLR_RXSTARTED_Enabled   (1UL)
 
#define TWIM_INTENCLR_RXSTARTED_Clear   (1UL)
 
#define TWIM_INTENCLR_SUSPENDED_Pos   (18UL)
 
#define TWIM_INTENCLR_SUSPENDED_Msk   (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos)
 
#define TWIM_INTENCLR_SUSPENDED_Disabled   (0UL)
 
#define TWIM_INTENCLR_SUSPENDED_Enabled   (1UL)
 
#define TWIM_INTENCLR_SUSPENDED_Clear   (1UL)
 
#define TWIM_INTENCLR_ERROR_Pos   (9UL)
 
#define TWIM_INTENCLR_ERROR_Msk   (0x1UL << TWIM_INTENCLR_ERROR_Pos)
 
#define TWIM_INTENCLR_ERROR_Disabled   (0UL)
 
#define TWIM_INTENCLR_ERROR_Enabled   (1UL)
 
#define TWIM_INTENCLR_ERROR_Clear   (1UL)
 
#define TWIM_INTENCLR_STOPPED_Pos   (1UL)
 
#define TWIM_INTENCLR_STOPPED_Msk   (0x1UL << TWIM_INTENCLR_STOPPED_Pos)
 
#define TWIM_INTENCLR_STOPPED_Disabled   (0UL)
 
#define TWIM_INTENCLR_STOPPED_Enabled   (1UL)
 
#define TWIM_INTENCLR_STOPPED_Clear   (1UL)
 
#define TWIM_ERRORSRC_DNACK_Pos   (2UL)
 
#define TWIM_ERRORSRC_DNACK_Msk   (0x1UL << TWIM_ERRORSRC_DNACK_Pos)
 
#define TWIM_ERRORSRC_DNACK_NotReceived   (0UL)
 
#define TWIM_ERRORSRC_DNACK_Received   (1UL)
 
#define TWIM_ERRORSRC_ANACK_Pos   (1UL)
 
#define TWIM_ERRORSRC_ANACK_Msk   (0x1UL << TWIM_ERRORSRC_ANACK_Pos)
 
#define TWIM_ERRORSRC_ANACK_NotReceived   (0UL)
 
#define TWIM_ERRORSRC_ANACK_Received   (1UL)
 
#define TWIM_ERRORSRC_OVERRUN_Pos   (0UL)
 
#define TWIM_ERRORSRC_OVERRUN_Msk   (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos)
 
#define TWIM_ERRORSRC_OVERRUN_NotReceived   (0UL)
 
#define TWIM_ERRORSRC_OVERRUN_Received   (1UL)
 
#define TWIM_ENABLE_ENABLE_Pos   (0UL)
 
#define TWIM_ENABLE_ENABLE_Msk   (0xFUL << TWIM_ENABLE_ENABLE_Pos)
 
#define TWIM_ENABLE_ENABLE_Disabled   (0UL)
 
#define TWIM_ENABLE_ENABLE_Enabled   (6UL)
 
#define TWIM_PSEL_SCL_CONNECT_Pos   (31UL)
 
#define TWIM_PSEL_SCL_CONNECT_Msk   (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos)
 
#define TWIM_PSEL_SCL_CONNECT_Connected   (0UL)
 
#define TWIM_PSEL_SCL_CONNECT_Disconnected   (1UL)
 
#define TWIM_PSEL_SCL_PIN_Pos   (0UL)
 
#define TWIM_PSEL_SCL_PIN_Msk   (0x1FUL << TWIM_PSEL_SCL_PIN_Pos)
 
#define TWIM_PSEL_SDA_CONNECT_Pos   (31UL)
 
#define TWIM_PSEL_SDA_CONNECT_Msk   (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos)
 
#define TWIM_PSEL_SDA_CONNECT_Connected   (0UL)
 
#define TWIM_PSEL_SDA_CONNECT_Disconnected   (1UL)
 
#define TWIM_PSEL_SDA_PIN_Pos   (0UL)
 
#define TWIM_PSEL_SDA_PIN_Msk   (0x1FUL << TWIM_PSEL_SDA_PIN_Pos)
 
#define TWIM_FREQUENCY_FREQUENCY_Pos   (0UL)
 
#define TWIM_FREQUENCY_FREQUENCY_Msk   (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos)
 
#define TWIM_FREQUENCY_FREQUENCY_K100   (0x01980000UL)
 
#define TWIM_FREQUENCY_FREQUENCY_K250   (0x04000000UL)
 
#define TWIM_FREQUENCY_FREQUENCY_K400   (0x06400000UL)
 
#define TWIM_RXD_PTR_PTR_Pos   (0UL)
 
#define TWIM_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos)
 
#define TWIM_RXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define TWIM_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos)
 
#define TWIM_RXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define TWIM_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos)
 
#define TWIM_RXD_LIST_LIST_Pos   (0UL)
 
#define TWIM_RXD_LIST_LIST_Msk   (0x7UL << TWIM_RXD_LIST_LIST_Pos)
 
#define TWIM_RXD_LIST_LIST_Disabled   (0UL)
 
#define TWIM_RXD_LIST_LIST_ArrayList   (1UL)
 
#define TWIM_TXD_PTR_PTR_Pos   (0UL)
 
#define TWIM_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos)
 
#define TWIM_TXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define TWIM_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos)
 
#define TWIM_TXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define TWIM_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos)
 
#define TWIM_TXD_LIST_LIST_Pos   (0UL)
 
#define TWIM_TXD_LIST_LIST_Msk   (0x7UL << TWIM_TXD_LIST_LIST_Pos)
 
#define TWIM_TXD_LIST_LIST_Disabled   (0UL)
 
#define TWIM_TXD_LIST_LIST_ArrayList   (1UL)
 
#define TWIM_ADDRESS_ADDRESS_Pos   (0UL)
 
#define TWIM_ADDRESS_ADDRESS_Msk   (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos)
 
#define TWIS_SHORTS_READ_SUSPEND_Pos   (14UL)
 
#define TWIS_SHORTS_READ_SUSPEND_Msk   (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos)
 
#define TWIS_SHORTS_READ_SUSPEND_Disabled   (0UL)
 
#define TWIS_SHORTS_READ_SUSPEND_Enabled   (1UL)
 
#define TWIS_SHORTS_WRITE_SUSPEND_Pos   (13UL)
 
#define TWIS_SHORTS_WRITE_SUSPEND_Msk   (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos)
 
#define TWIS_SHORTS_WRITE_SUSPEND_Disabled   (0UL)
 
#define TWIS_SHORTS_WRITE_SUSPEND_Enabled   (1UL)
 
#define TWIS_INTEN_READ_Pos   (26UL)
 
#define TWIS_INTEN_READ_Msk   (0x1UL << TWIS_INTEN_READ_Pos)
 
#define TWIS_INTEN_READ_Disabled   (0UL)
 
#define TWIS_INTEN_READ_Enabled   (1UL)
 
#define TWIS_INTEN_WRITE_Pos   (25UL)
 
#define TWIS_INTEN_WRITE_Msk   (0x1UL << TWIS_INTEN_WRITE_Pos)
 
#define TWIS_INTEN_WRITE_Disabled   (0UL)
 
#define TWIS_INTEN_WRITE_Enabled   (1UL)
 
#define TWIS_INTEN_TXSTARTED_Pos   (20UL)
 
#define TWIS_INTEN_TXSTARTED_Msk   (0x1UL << TWIS_INTEN_TXSTARTED_Pos)
 
#define TWIS_INTEN_TXSTARTED_Disabled   (0UL)
 
#define TWIS_INTEN_TXSTARTED_Enabled   (1UL)
 
#define TWIS_INTEN_RXSTARTED_Pos   (19UL)
 
#define TWIS_INTEN_RXSTARTED_Msk   (0x1UL << TWIS_INTEN_RXSTARTED_Pos)
 
#define TWIS_INTEN_RXSTARTED_Disabled   (0UL)
 
#define TWIS_INTEN_RXSTARTED_Enabled   (1UL)
 
#define TWIS_INTEN_ERROR_Pos   (9UL)
 
#define TWIS_INTEN_ERROR_Msk   (0x1UL << TWIS_INTEN_ERROR_Pos)
 
#define TWIS_INTEN_ERROR_Disabled   (0UL)
 
#define TWIS_INTEN_ERROR_Enabled   (1UL)
 
#define TWIS_INTEN_STOPPED_Pos   (1UL)
 
#define TWIS_INTEN_STOPPED_Msk   (0x1UL << TWIS_INTEN_STOPPED_Pos)
 
#define TWIS_INTEN_STOPPED_Disabled   (0UL)
 
#define TWIS_INTEN_STOPPED_Enabled   (1UL)
 
#define TWIS_INTENSET_READ_Pos   (26UL)
 
#define TWIS_INTENSET_READ_Msk   (0x1UL << TWIS_INTENSET_READ_Pos)
 
#define TWIS_INTENSET_READ_Disabled   (0UL)
 
#define TWIS_INTENSET_READ_Enabled   (1UL)
 
#define TWIS_INTENSET_READ_Set   (1UL)
 
#define TWIS_INTENSET_WRITE_Pos   (25UL)
 
#define TWIS_INTENSET_WRITE_Msk   (0x1UL << TWIS_INTENSET_WRITE_Pos)
 
#define TWIS_INTENSET_WRITE_Disabled   (0UL)
 
#define TWIS_INTENSET_WRITE_Enabled   (1UL)
 
#define TWIS_INTENSET_WRITE_Set   (1UL)
 
#define TWIS_INTENSET_TXSTARTED_Pos   (20UL)
 
#define TWIS_INTENSET_TXSTARTED_Msk   (0x1UL << TWIS_INTENSET_TXSTARTED_Pos)
 
#define TWIS_INTENSET_TXSTARTED_Disabled   (0UL)
 
#define TWIS_INTENSET_TXSTARTED_Enabled   (1UL)
 
#define TWIS_INTENSET_TXSTARTED_Set   (1UL)
 
#define TWIS_INTENSET_RXSTARTED_Pos   (19UL)
 
#define TWIS_INTENSET_RXSTARTED_Msk   (0x1UL << TWIS_INTENSET_RXSTARTED_Pos)
 
#define TWIS_INTENSET_RXSTARTED_Disabled   (0UL)
 
#define TWIS_INTENSET_RXSTARTED_Enabled   (1UL)
 
#define TWIS_INTENSET_RXSTARTED_Set   (1UL)
 
#define TWIS_INTENSET_ERROR_Pos   (9UL)
 
#define TWIS_INTENSET_ERROR_Msk   (0x1UL << TWIS_INTENSET_ERROR_Pos)
 
#define TWIS_INTENSET_ERROR_Disabled   (0UL)
 
#define TWIS_INTENSET_ERROR_Enabled   (1UL)
 
#define TWIS_INTENSET_ERROR_Set   (1UL)
 
#define TWIS_INTENSET_STOPPED_Pos   (1UL)
 
#define TWIS_INTENSET_STOPPED_Msk   (0x1UL << TWIS_INTENSET_STOPPED_Pos)
 
#define TWIS_INTENSET_STOPPED_Disabled   (0UL)
 
#define TWIS_INTENSET_STOPPED_Enabled   (1UL)
 
#define TWIS_INTENSET_STOPPED_Set   (1UL)
 
#define TWIS_INTENCLR_READ_Pos   (26UL)
 
#define TWIS_INTENCLR_READ_Msk   (0x1UL << TWIS_INTENCLR_READ_Pos)
 
#define TWIS_INTENCLR_READ_Disabled   (0UL)
 
#define TWIS_INTENCLR_READ_Enabled   (1UL)
 
#define TWIS_INTENCLR_READ_Clear   (1UL)
 
#define TWIS_INTENCLR_WRITE_Pos   (25UL)
 
#define TWIS_INTENCLR_WRITE_Msk   (0x1UL << TWIS_INTENCLR_WRITE_Pos)
 
#define TWIS_INTENCLR_WRITE_Disabled   (0UL)
 
#define TWIS_INTENCLR_WRITE_Enabled   (1UL)
 
#define TWIS_INTENCLR_WRITE_Clear   (1UL)
 
#define TWIS_INTENCLR_TXSTARTED_Pos   (20UL)
 
#define TWIS_INTENCLR_TXSTARTED_Msk   (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos)
 
#define TWIS_INTENCLR_TXSTARTED_Disabled   (0UL)
 
#define TWIS_INTENCLR_TXSTARTED_Enabled   (1UL)
 
#define TWIS_INTENCLR_TXSTARTED_Clear   (1UL)
 
#define TWIS_INTENCLR_RXSTARTED_Pos   (19UL)
 
#define TWIS_INTENCLR_RXSTARTED_Msk   (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos)
 
#define TWIS_INTENCLR_RXSTARTED_Disabled   (0UL)
 
#define TWIS_INTENCLR_RXSTARTED_Enabled   (1UL)
 
#define TWIS_INTENCLR_RXSTARTED_Clear   (1UL)
 
#define TWIS_INTENCLR_ERROR_Pos   (9UL)
 
#define TWIS_INTENCLR_ERROR_Msk   (0x1UL << TWIS_INTENCLR_ERROR_Pos)
 
#define TWIS_INTENCLR_ERROR_Disabled   (0UL)
 
#define TWIS_INTENCLR_ERROR_Enabled   (1UL)
 
#define TWIS_INTENCLR_ERROR_Clear   (1UL)
 
#define TWIS_INTENCLR_STOPPED_Pos   (1UL)
 
#define TWIS_INTENCLR_STOPPED_Msk   (0x1UL << TWIS_INTENCLR_STOPPED_Pos)
 
#define TWIS_INTENCLR_STOPPED_Disabled   (0UL)
 
#define TWIS_INTENCLR_STOPPED_Enabled   (1UL)
 
#define TWIS_INTENCLR_STOPPED_Clear   (1UL)
 
#define TWIS_ERRORSRC_OVERREAD_Pos   (3UL)
 
#define TWIS_ERRORSRC_OVERREAD_Msk   (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos)
 
#define TWIS_ERRORSRC_OVERREAD_NotDetected   (0UL)
 
#define TWIS_ERRORSRC_OVERREAD_Detected   (1UL)
 
#define TWIS_ERRORSRC_DNACK_Pos   (2UL)
 
#define TWIS_ERRORSRC_DNACK_Msk   (0x1UL << TWIS_ERRORSRC_DNACK_Pos)
 
#define TWIS_ERRORSRC_DNACK_NotReceived   (0UL)
 
#define TWIS_ERRORSRC_DNACK_Received   (1UL)
 
#define TWIS_ERRORSRC_OVERFLOW_Pos   (0UL)
 
#define TWIS_ERRORSRC_OVERFLOW_Msk   (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos)
 
#define TWIS_ERRORSRC_OVERFLOW_NotDetected   (0UL)
 
#define TWIS_ERRORSRC_OVERFLOW_Detected   (1UL)
 
#define TWIS_MATCH_MATCH_Pos   (0UL)
 
#define TWIS_MATCH_MATCH_Msk   (0x1UL << TWIS_MATCH_MATCH_Pos)
 
#define TWIS_ENABLE_ENABLE_Pos   (0UL)
 
#define TWIS_ENABLE_ENABLE_Msk   (0xFUL << TWIS_ENABLE_ENABLE_Pos)
 
#define TWIS_ENABLE_ENABLE_Disabled   (0UL)
 
#define TWIS_ENABLE_ENABLE_Enabled   (9UL)
 
#define TWIS_PSEL_SCL_CONNECT_Pos   (31UL)
 
#define TWIS_PSEL_SCL_CONNECT_Msk   (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos)
 
#define TWIS_PSEL_SCL_CONNECT_Connected   (0UL)
 
#define TWIS_PSEL_SCL_CONNECT_Disconnected   (1UL)
 
#define TWIS_PSEL_SCL_PIN_Pos   (0UL)
 
#define TWIS_PSEL_SCL_PIN_Msk   (0x1FUL << TWIS_PSEL_SCL_PIN_Pos)
 
#define TWIS_PSEL_SDA_CONNECT_Pos   (31UL)
 
#define TWIS_PSEL_SDA_CONNECT_Msk   (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos)
 
#define TWIS_PSEL_SDA_CONNECT_Connected   (0UL)
 
#define TWIS_PSEL_SDA_CONNECT_Disconnected   (1UL)
 
#define TWIS_PSEL_SDA_PIN_Pos   (0UL)
 
#define TWIS_PSEL_SDA_PIN_Msk   (0x1FUL << TWIS_PSEL_SDA_PIN_Pos)
 
#define TWIS_RXD_PTR_PTR_Pos   (0UL)
 
#define TWIS_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos)
 
#define TWIS_RXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define TWIS_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos)
 
#define TWIS_RXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define TWIS_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos)
 
#define TWIS_TXD_PTR_PTR_Pos   (0UL)
 
#define TWIS_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos)
 
#define TWIS_TXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define TWIS_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos)
 
#define TWIS_TXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define TWIS_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos)
 
#define TWIS_ADDRESS_ADDRESS_Pos   (0UL)
 
#define TWIS_ADDRESS_ADDRESS_Msk   (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos)
 
#define TWIS_CONFIG_ADDRESS1_Pos   (1UL)
 
#define TWIS_CONFIG_ADDRESS1_Msk   (0x1UL << TWIS_CONFIG_ADDRESS1_Pos)
 
#define TWIS_CONFIG_ADDRESS1_Disabled   (0UL)
 
#define TWIS_CONFIG_ADDRESS1_Enabled   (1UL)
 
#define TWIS_CONFIG_ADDRESS0_Pos   (0UL)
 
#define TWIS_CONFIG_ADDRESS0_Msk   (0x1UL << TWIS_CONFIG_ADDRESS0_Pos)
 
#define TWIS_CONFIG_ADDRESS0_Disabled   (0UL)
 
#define TWIS_CONFIG_ADDRESS0_Enabled   (1UL)
 
#define TWIS_ORC_ORC_Pos   (0UL)
 
#define TWIS_ORC_ORC_Msk   (0xFFUL << TWIS_ORC_ORC_Pos)
 
#define UART_SHORTS_NCTS_STOPRX_Pos   (4UL)
 
#define UART_SHORTS_NCTS_STOPRX_Msk   (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos)
 
#define UART_SHORTS_NCTS_STOPRX_Disabled   (0UL)
 
#define UART_SHORTS_NCTS_STOPRX_Enabled   (1UL)
 
#define UART_SHORTS_CTS_STARTRX_Pos   (3UL)
 
#define UART_SHORTS_CTS_STARTRX_Msk   (0x1UL << UART_SHORTS_CTS_STARTRX_Pos)
 
#define UART_SHORTS_CTS_STARTRX_Disabled   (0UL)
 
#define UART_SHORTS_CTS_STARTRX_Enabled   (1UL)
 
#define UART_INTENSET_RXTO_Pos   (17UL)
 
#define UART_INTENSET_RXTO_Msk   (0x1UL << UART_INTENSET_RXTO_Pos)
 
#define UART_INTENSET_RXTO_Disabled   (0UL)
 
#define UART_INTENSET_RXTO_Enabled   (1UL)
 
#define UART_INTENSET_RXTO_Set   (1UL)
 
#define UART_INTENSET_ERROR_Pos   (9UL)
 
#define UART_INTENSET_ERROR_Msk   (0x1UL << UART_INTENSET_ERROR_Pos)
 
#define UART_INTENSET_ERROR_Disabled   (0UL)
 
#define UART_INTENSET_ERROR_Enabled   (1UL)
 
#define UART_INTENSET_ERROR_Set   (1UL)
 
#define UART_INTENSET_TXDRDY_Pos   (7UL)
 
#define UART_INTENSET_TXDRDY_Msk   (0x1UL << UART_INTENSET_TXDRDY_Pos)
 
#define UART_INTENSET_TXDRDY_Disabled   (0UL)
 
#define UART_INTENSET_TXDRDY_Enabled   (1UL)
 
#define UART_INTENSET_TXDRDY_Set   (1UL)
 
#define UART_INTENSET_RXDRDY_Pos   (2UL)
 
#define UART_INTENSET_RXDRDY_Msk   (0x1UL << UART_INTENSET_RXDRDY_Pos)
 
#define UART_INTENSET_RXDRDY_Disabled   (0UL)
 
#define UART_INTENSET_RXDRDY_Enabled   (1UL)
 
#define UART_INTENSET_RXDRDY_Set   (1UL)
 
#define UART_INTENSET_NCTS_Pos   (1UL)
 
#define UART_INTENSET_NCTS_Msk   (0x1UL << UART_INTENSET_NCTS_Pos)
 
#define UART_INTENSET_NCTS_Disabled   (0UL)
 
#define UART_INTENSET_NCTS_Enabled   (1UL)
 
#define UART_INTENSET_NCTS_Set   (1UL)
 
#define UART_INTENSET_CTS_Pos   (0UL)
 
#define UART_INTENSET_CTS_Msk   (0x1UL << UART_INTENSET_CTS_Pos)
 
#define UART_INTENSET_CTS_Disabled   (0UL)
 
#define UART_INTENSET_CTS_Enabled   (1UL)
 
#define UART_INTENSET_CTS_Set   (1UL)
 
#define UART_INTENCLR_RXTO_Pos   (17UL)
 
#define UART_INTENCLR_RXTO_Msk   (0x1UL << UART_INTENCLR_RXTO_Pos)
 
#define UART_INTENCLR_RXTO_Disabled   (0UL)
 
#define UART_INTENCLR_RXTO_Enabled   (1UL)
 
#define UART_INTENCLR_RXTO_Clear   (1UL)
 
#define UART_INTENCLR_ERROR_Pos   (9UL)
 
#define UART_INTENCLR_ERROR_Msk   (0x1UL << UART_INTENCLR_ERROR_Pos)
 
#define UART_INTENCLR_ERROR_Disabled   (0UL)
 
#define UART_INTENCLR_ERROR_Enabled   (1UL)
 
#define UART_INTENCLR_ERROR_Clear   (1UL)
 
#define UART_INTENCLR_TXDRDY_Pos   (7UL)
 
#define UART_INTENCLR_TXDRDY_Msk   (0x1UL << UART_INTENCLR_TXDRDY_Pos)
 
#define UART_INTENCLR_TXDRDY_Disabled   (0UL)
 
#define UART_INTENCLR_TXDRDY_Enabled   (1UL)
 
#define UART_INTENCLR_TXDRDY_Clear   (1UL)
 
#define UART_INTENCLR_RXDRDY_Pos   (2UL)
 
#define UART_INTENCLR_RXDRDY_Msk   (0x1UL << UART_INTENCLR_RXDRDY_Pos)
 
#define UART_INTENCLR_RXDRDY_Disabled   (0UL)
 
#define UART_INTENCLR_RXDRDY_Enabled   (1UL)
 
#define UART_INTENCLR_RXDRDY_Clear   (1UL)
 
#define UART_INTENCLR_NCTS_Pos   (1UL)
 
#define UART_INTENCLR_NCTS_Msk   (0x1UL << UART_INTENCLR_NCTS_Pos)
 
#define UART_INTENCLR_NCTS_Disabled   (0UL)
 
#define UART_INTENCLR_NCTS_Enabled   (1UL)
 
#define UART_INTENCLR_NCTS_Clear   (1UL)
 
#define UART_INTENCLR_CTS_Pos   (0UL)
 
#define UART_INTENCLR_CTS_Msk   (0x1UL << UART_INTENCLR_CTS_Pos)
 
#define UART_INTENCLR_CTS_Disabled   (0UL)
 
#define UART_INTENCLR_CTS_Enabled   (1UL)
 
#define UART_INTENCLR_CTS_Clear   (1UL)
 
#define UART_ERRORSRC_BREAK_Pos   (3UL)
 
#define UART_ERRORSRC_BREAK_Msk   (0x1UL << UART_ERRORSRC_BREAK_Pos)
 
#define UART_ERRORSRC_BREAK_NotPresent   (0UL)
 
#define UART_ERRORSRC_BREAK_Present   (1UL)
 
#define UART_ERRORSRC_FRAMING_Pos   (2UL)
 
#define UART_ERRORSRC_FRAMING_Msk   (0x1UL << UART_ERRORSRC_FRAMING_Pos)
 
#define UART_ERRORSRC_FRAMING_NotPresent   (0UL)
 
#define UART_ERRORSRC_FRAMING_Present   (1UL)
 
#define UART_ERRORSRC_PARITY_Pos   (1UL)
 
#define UART_ERRORSRC_PARITY_Msk   (0x1UL << UART_ERRORSRC_PARITY_Pos)
 
#define UART_ERRORSRC_PARITY_NotPresent   (0UL)
 
#define UART_ERRORSRC_PARITY_Present   (1UL)
 
#define UART_ERRORSRC_OVERRUN_Pos   (0UL)
 
#define UART_ERRORSRC_OVERRUN_Msk   (0x1UL << UART_ERRORSRC_OVERRUN_Pos)
 
#define UART_ERRORSRC_OVERRUN_NotPresent   (0UL)
 
#define UART_ERRORSRC_OVERRUN_Present   (1UL)
 
#define UART_ENABLE_ENABLE_Pos   (0UL)
 
#define UART_ENABLE_ENABLE_Msk   (0xFUL << UART_ENABLE_ENABLE_Pos)
 
#define UART_ENABLE_ENABLE_Disabled   (0UL)
 
#define UART_ENABLE_ENABLE_Enabled   (4UL)
 
#define UART_PSELRTS_PSELRTS_Pos   (0UL)
 
#define UART_PSELRTS_PSELRTS_Msk   (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos)
 
#define UART_PSELRTS_PSELRTS_Disconnected   (0xFFFFFFFFUL)
 
#define UART_PSELTXD_PSELTXD_Pos   (0UL)
 
#define UART_PSELTXD_PSELTXD_Msk   (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos)
 
#define UART_PSELTXD_PSELTXD_Disconnected   (0xFFFFFFFFUL)
 
#define UART_PSELCTS_PSELCTS_Pos   (0UL)
 
#define UART_PSELCTS_PSELCTS_Msk   (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos)
 
#define UART_PSELCTS_PSELCTS_Disconnected   (0xFFFFFFFFUL)
 
#define UART_PSELRXD_PSELRXD_Pos   (0UL)
 
#define UART_PSELRXD_PSELRXD_Msk   (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos)
 
#define UART_PSELRXD_PSELRXD_Disconnected   (0xFFFFFFFFUL)
 
#define UART_RXD_RXD_Pos   (0UL)
 
#define UART_RXD_RXD_Msk   (0xFFUL << UART_RXD_RXD_Pos)
 
#define UART_TXD_TXD_Pos   (0UL)
 
#define UART_TXD_TXD_Msk   (0xFFUL << UART_TXD_TXD_Pos)
 
#define UART_BAUDRATE_BAUDRATE_Pos   (0UL)
 
#define UART_BAUDRATE_BAUDRATE_Msk   (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos)
 
#define UART_BAUDRATE_BAUDRATE_Baud1200   (0x0004F000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud2400   (0x0009D000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud4800   (0x0013B000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud9600   (0x00275000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud14400   (0x003B0000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud19200   (0x004EA000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud28800   (0x0075F000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud31250   (0x00800000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud38400   (0x009D5000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud56000   (0x00E50000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud57600   (0x00EBF000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud76800   (0x013A9000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud115200   (0x01D7E000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud230400   (0x03AFB000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud250000   (0x04000000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud460800   (0x075F7000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud921600   (0x0EBED000UL)
 
#define UART_BAUDRATE_BAUDRATE_Baud1M   (0x10000000UL)
 
#define UART_CONFIG_PARITY_Pos   (1UL)
 
#define UART_CONFIG_PARITY_Msk   (0x7UL << UART_CONFIG_PARITY_Pos)
 
#define UART_CONFIG_PARITY_Excluded   (0x0UL)
 
#define UART_CONFIG_PARITY_Included   (0x7UL)
 
#define UART_CONFIG_HWFC_Pos   (0UL)
 
#define UART_CONFIG_HWFC_Msk   (0x1UL << UART_CONFIG_HWFC_Pos)
 
#define UART_CONFIG_HWFC_Disabled   (0UL)
 
#define UART_CONFIG_HWFC_Enabled   (1UL)
 
#define UARTE_SHORTS_ENDRX_STOPRX_Pos   (6UL)
 
#define UARTE_SHORTS_ENDRX_STOPRX_Msk   (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos)
 
#define UARTE_SHORTS_ENDRX_STOPRX_Disabled   (0UL)
 
#define UARTE_SHORTS_ENDRX_STOPRX_Enabled   (1UL)
 
#define UARTE_SHORTS_ENDRX_STARTRX_Pos   (5UL)
 
#define UARTE_SHORTS_ENDRX_STARTRX_Msk   (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos)
 
#define UARTE_SHORTS_ENDRX_STARTRX_Disabled   (0UL)
 
#define UARTE_SHORTS_ENDRX_STARTRX_Enabled   (1UL)
 
#define UARTE_INTEN_TXSTOPPED_Pos   (22UL)
 
#define UARTE_INTEN_TXSTOPPED_Msk   (0x1UL << UARTE_INTEN_TXSTOPPED_Pos)
 
#define UARTE_INTEN_TXSTOPPED_Disabled   (0UL)
 
#define UARTE_INTEN_TXSTOPPED_Enabled   (1UL)
 
#define UARTE_INTEN_TXSTARTED_Pos   (20UL)
 
#define UARTE_INTEN_TXSTARTED_Msk   (0x1UL << UARTE_INTEN_TXSTARTED_Pos)
 
#define UARTE_INTEN_TXSTARTED_Disabled   (0UL)
 
#define UARTE_INTEN_TXSTARTED_Enabled   (1UL)
 
#define UARTE_INTEN_RXSTARTED_Pos   (19UL)
 
#define UARTE_INTEN_RXSTARTED_Msk   (0x1UL << UARTE_INTEN_RXSTARTED_Pos)
 
#define UARTE_INTEN_RXSTARTED_Disabled   (0UL)
 
#define UARTE_INTEN_RXSTARTED_Enabled   (1UL)
 
#define UARTE_INTEN_RXTO_Pos   (17UL)
 
#define UARTE_INTEN_RXTO_Msk   (0x1UL << UARTE_INTEN_RXTO_Pos)
 
#define UARTE_INTEN_RXTO_Disabled   (0UL)
 
#define UARTE_INTEN_RXTO_Enabled   (1UL)
 
#define UARTE_INTEN_ERROR_Pos   (9UL)
 
#define UARTE_INTEN_ERROR_Msk   (0x1UL << UARTE_INTEN_ERROR_Pos)
 
#define UARTE_INTEN_ERROR_Disabled   (0UL)
 
#define UARTE_INTEN_ERROR_Enabled   (1UL)
 
#define UARTE_INTEN_ENDTX_Pos   (8UL)
 
#define UARTE_INTEN_ENDTX_Msk   (0x1UL << UARTE_INTEN_ENDTX_Pos)
 
#define UARTE_INTEN_ENDTX_Disabled   (0UL)
 
#define UARTE_INTEN_ENDTX_Enabled   (1UL)
 
#define UARTE_INTEN_TXDRDY_Pos   (7UL)
 
#define UARTE_INTEN_TXDRDY_Msk   (0x1UL << UARTE_INTEN_TXDRDY_Pos)
 
#define UARTE_INTEN_TXDRDY_Disabled   (0UL)
 
#define UARTE_INTEN_TXDRDY_Enabled   (1UL)
 
#define UARTE_INTEN_ENDRX_Pos   (4UL)
 
#define UARTE_INTEN_ENDRX_Msk   (0x1UL << UARTE_INTEN_ENDRX_Pos)
 
#define UARTE_INTEN_ENDRX_Disabled   (0UL)
 
#define UARTE_INTEN_ENDRX_Enabled   (1UL)
 
#define UARTE_INTEN_RXDRDY_Pos   (2UL)
 
#define UARTE_INTEN_RXDRDY_Msk   (0x1UL << UARTE_INTEN_RXDRDY_Pos)
 
#define UARTE_INTEN_RXDRDY_Disabled   (0UL)
 
#define UARTE_INTEN_RXDRDY_Enabled   (1UL)
 
#define UARTE_INTEN_NCTS_Pos   (1UL)
 
#define UARTE_INTEN_NCTS_Msk   (0x1UL << UARTE_INTEN_NCTS_Pos)
 
#define UARTE_INTEN_NCTS_Disabled   (0UL)
 
#define UARTE_INTEN_NCTS_Enabled   (1UL)
 
#define UARTE_INTEN_CTS_Pos   (0UL)
 
#define UARTE_INTEN_CTS_Msk   (0x1UL << UARTE_INTEN_CTS_Pos)
 
#define UARTE_INTEN_CTS_Disabled   (0UL)
 
#define UARTE_INTEN_CTS_Enabled   (1UL)
 
#define UARTE_INTENSET_TXSTOPPED_Pos   (22UL)
 
#define UARTE_INTENSET_TXSTOPPED_Msk   (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos)
 
#define UARTE_INTENSET_TXSTOPPED_Disabled   (0UL)
 
#define UARTE_INTENSET_TXSTOPPED_Enabled   (1UL)
 
#define UARTE_INTENSET_TXSTOPPED_Set   (1UL)
 
#define UARTE_INTENSET_TXSTARTED_Pos   (20UL)
 
#define UARTE_INTENSET_TXSTARTED_Msk   (0x1UL << UARTE_INTENSET_TXSTARTED_Pos)
 
#define UARTE_INTENSET_TXSTARTED_Disabled   (0UL)
 
#define UARTE_INTENSET_TXSTARTED_Enabled   (1UL)
 
#define UARTE_INTENSET_TXSTARTED_Set   (1UL)
 
#define UARTE_INTENSET_RXSTARTED_Pos   (19UL)
 
#define UARTE_INTENSET_RXSTARTED_Msk   (0x1UL << UARTE_INTENSET_RXSTARTED_Pos)
 
#define UARTE_INTENSET_RXSTARTED_Disabled   (0UL)
 
#define UARTE_INTENSET_RXSTARTED_Enabled   (1UL)
 
#define UARTE_INTENSET_RXSTARTED_Set   (1UL)
 
#define UARTE_INTENSET_RXTO_Pos   (17UL)
 
#define UARTE_INTENSET_RXTO_Msk   (0x1UL << UARTE_INTENSET_RXTO_Pos)
 
#define UARTE_INTENSET_RXTO_Disabled   (0UL)
 
#define UARTE_INTENSET_RXTO_Enabled   (1UL)
 
#define UARTE_INTENSET_RXTO_Set   (1UL)
 
#define UARTE_INTENSET_ERROR_Pos   (9UL)
 
#define UARTE_INTENSET_ERROR_Msk   (0x1UL << UARTE_INTENSET_ERROR_Pos)
 
#define UARTE_INTENSET_ERROR_Disabled   (0UL)
 
#define UARTE_INTENSET_ERROR_Enabled   (1UL)
 
#define UARTE_INTENSET_ERROR_Set   (1UL)
 
#define UARTE_INTENSET_ENDTX_Pos   (8UL)
 
#define UARTE_INTENSET_ENDTX_Msk   (0x1UL << UARTE_INTENSET_ENDTX_Pos)
 
#define UARTE_INTENSET_ENDTX_Disabled   (0UL)
 
#define UARTE_INTENSET_ENDTX_Enabled   (1UL)
 
#define UARTE_INTENSET_ENDTX_Set   (1UL)
 
#define UARTE_INTENSET_TXDRDY_Pos   (7UL)
 
#define UARTE_INTENSET_TXDRDY_Msk   (0x1UL << UARTE_INTENSET_TXDRDY_Pos)
 
#define UARTE_INTENSET_TXDRDY_Disabled   (0UL)
 
#define UARTE_INTENSET_TXDRDY_Enabled   (1UL)
 
#define UARTE_INTENSET_TXDRDY_Set   (1UL)
 
#define UARTE_INTENSET_ENDRX_Pos   (4UL)
 
#define UARTE_INTENSET_ENDRX_Msk   (0x1UL << UARTE_INTENSET_ENDRX_Pos)
 
#define UARTE_INTENSET_ENDRX_Disabled   (0UL)
 
#define UARTE_INTENSET_ENDRX_Enabled   (1UL)
 
#define UARTE_INTENSET_ENDRX_Set   (1UL)
 
#define UARTE_INTENSET_RXDRDY_Pos   (2UL)
 
#define UARTE_INTENSET_RXDRDY_Msk   (0x1UL << UARTE_INTENSET_RXDRDY_Pos)
 
#define UARTE_INTENSET_RXDRDY_Disabled   (0UL)
 
#define UARTE_INTENSET_RXDRDY_Enabled   (1UL)
 
#define UARTE_INTENSET_RXDRDY_Set   (1UL)
 
#define UARTE_INTENSET_NCTS_Pos   (1UL)
 
#define UARTE_INTENSET_NCTS_Msk   (0x1UL << UARTE_INTENSET_NCTS_Pos)
 
#define UARTE_INTENSET_NCTS_Disabled   (0UL)
 
#define UARTE_INTENSET_NCTS_Enabled   (1UL)
 
#define UARTE_INTENSET_NCTS_Set   (1UL)
 
#define UARTE_INTENSET_CTS_Pos   (0UL)
 
#define UARTE_INTENSET_CTS_Msk   (0x1UL << UARTE_INTENSET_CTS_Pos)
 
#define UARTE_INTENSET_CTS_Disabled   (0UL)
 
#define UARTE_INTENSET_CTS_Enabled   (1UL)
 
#define UARTE_INTENSET_CTS_Set   (1UL)
 
#define UARTE_INTENCLR_TXSTOPPED_Pos   (22UL)
 
#define UARTE_INTENCLR_TXSTOPPED_Msk   (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos)
 
#define UARTE_INTENCLR_TXSTOPPED_Disabled   (0UL)
 
#define UARTE_INTENCLR_TXSTOPPED_Enabled   (1UL)
 
#define UARTE_INTENCLR_TXSTOPPED_Clear   (1UL)
 
#define UARTE_INTENCLR_TXSTARTED_Pos   (20UL)
 
#define UARTE_INTENCLR_TXSTARTED_Msk   (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos)
 
#define UARTE_INTENCLR_TXSTARTED_Disabled   (0UL)
 
#define UARTE_INTENCLR_TXSTARTED_Enabled   (1UL)
 
#define UARTE_INTENCLR_TXSTARTED_Clear   (1UL)
 
#define UARTE_INTENCLR_RXSTARTED_Pos   (19UL)
 
#define UARTE_INTENCLR_RXSTARTED_Msk   (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos)
 
#define UARTE_INTENCLR_RXSTARTED_Disabled   (0UL)
 
#define UARTE_INTENCLR_RXSTARTED_Enabled   (1UL)
 
#define UARTE_INTENCLR_RXSTARTED_Clear   (1UL)
 
#define UARTE_INTENCLR_RXTO_Pos   (17UL)
 
#define UARTE_INTENCLR_RXTO_Msk   (0x1UL << UARTE_INTENCLR_RXTO_Pos)
 
#define UARTE_INTENCLR_RXTO_Disabled   (0UL)
 
#define UARTE_INTENCLR_RXTO_Enabled   (1UL)
 
#define UARTE_INTENCLR_RXTO_Clear   (1UL)
 
#define UARTE_INTENCLR_ERROR_Pos   (9UL)
 
#define UARTE_INTENCLR_ERROR_Msk   (0x1UL << UARTE_INTENCLR_ERROR_Pos)
 
#define UARTE_INTENCLR_ERROR_Disabled   (0UL)
 
#define UARTE_INTENCLR_ERROR_Enabled   (1UL)
 
#define UARTE_INTENCLR_ERROR_Clear   (1UL)
 
#define UARTE_INTENCLR_ENDTX_Pos   (8UL)
 
#define UARTE_INTENCLR_ENDTX_Msk   (0x1UL << UARTE_INTENCLR_ENDTX_Pos)
 
#define UARTE_INTENCLR_ENDTX_Disabled   (0UL)
 
#define UARTE_INTENCLR_ENDTX_Enabled   (1UL)
 
#define UARTE_INTENCLR_ENDTX_Clear   (1UL)
 
#define UARTE_INTENCLR_TXDRDY_Pos   (7UL)
 
#define UARTE_INTENCLR_TXDRDY_Msk   (0x1UL << UARTE_INTENCLR_TXDRDY_Pos)
 
#define UARTE_INTENCLR_TXDRDY_Disabled   (0UL)
 
#define UARTE_INTENCLR_TXDRDY_Enabled   (1UL)
 
#define UARTE_INTENCLR_TXDRDY_Clear   (1UL)
 
#define UARTE_INTENCLR_ENDRX_Pos   (4UL)
 
#define UARTE_INTENCLR_ENDRX_Msk   (0x1UL << UARTE_INTENCLR_ENDRX_Pos)
 
#define UARTE_INTENCLR_ENDRX_Disabled   (0UL)
 
#define UARTE_INTENCLR_ENDRX_Enabled   (1UL)
 
#define UARTE_INTENCLR_ENDRX_Clear   (1UL)
 
#define UARTE_INTENCLR_RXDRDY_Pos   (2UL)
 
#define UARTE_INTENCLR_RXDRDY_Msk   (0x1UL << UARTE_INTENCLR_RXDRDY_Pos)
 
#define UARTE_INTENCLR_RXDRDY_Disabled   (0UL)
 
#define UARTE_INTENCLR_RXDRDY_Enabled   (1UL)
 
#define UARTE_INTENCLR_RXDRDY_Clear   (1UL)
 
#define UARTE_INTENCLR_NCTS_Pos   (1UL)
 
#define UARTE_INTENCLR_NCTS_Msk   (0x1UL << UARTE_INTENCLR_NCTS_Pos)
 
#define UARTE_INTENCLR_NCTS_Disabled   (0UL)
 
#define UARTE_INTENCLR_NCTS_Enabled   (1UL)
 
#define UARTE_INTENCLR_NCTS_Clear   (1UL)
 
#define UARTE_INTENCLR_CTS_Pos   (0UL)
 
#define UARTE_INTENCLR_CTS_Msk   (0x1UL << UARTE_INTENCLR_CTS_Pos)
 
#define UARTE_INTENCLR_CTS_Disabled   (0UL)
 
#define UARTE_INTENCLR_CTS_Enabled   (1UL)
 
#define UARTE_INTENCLR_CTS_Clear   (1UL)
 
#define UARTE_ERRORSRC_BREAK_Pos   (3UL)
 
#define UARTE_ERRORSRC_BREAK_Msk   (0x1UL << UARTE_ERRORSRC_BREAK_Pos)
 
#define UARTE_ERRORSRC_BREAK_NotPresent   (0UL)
 
#define UARTE_ERRORSRC_BREAK_Present   (1UL)
 
#define UARTE_ERRORSRC_FRAMING_Pos   (2UL)
 
#define UARTE_ERRORSRC_FRAMING_Msk   (0x1UL << UARTE_ERRORSRC_FRAMING_Pos)
 
#define UARTE_ERRORSRC_FRAMING_NotPresent   (0UL)
 
#define UARTE_ERRORSRC_FRAMING_Present   (1UL)
 
#define UARTE_ERRORSRC_PARITY_Pos   (1UL)
 
#define UARTE_ERRORSRC_PARITY_Msk   (0x1UL << UARTE_ERRORSRC_PARITY_Pos)
 
#define UARTE_ERRORSRC_PARITY_NotPresent   (0UL)
 
#define UARTE_ERRORSRC_PARITY_Present   (1UL)
 
#define UARTE_ERRORSRC_OVERRUN_Pos   (0UL)
 
#define UARTE_ERRORSRC_OVERRUN_Msk   (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos)
 
#define UARTE_ERRORSRC_OVERRUN_NotPresent   (0UL)
 
#define UARTE_ERRORSRC_OVERRUN_Present   (1UL)
 
#define UARTE_ENABLE_ENABLE_Pos   (0UL)
 
#define UARTE_ENABLE_ENABLE_Msk   (0xFUL << UARTE_ENABLE_ENABLE_Pos)
 
#define UARTE_ENABLE_ENABLE_Disabled   (0UL)
 
#define UARTE_ENABLE_ENABLE_Enabled   (8UL)
 
#define UARTE_PSEL_RTS_CONNECT_Pos   (31UL)
 
#define UARTE_PSEL_RTS_CONNECT_Msk   (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos)
 
#define UARTE_PSEL_RTS_CONNECT_Connected   (0UL)
 
#define UARTE_PSEL_RTS_CONNECT_Disconnected   (1UL)
 
#define UARTE_PSEL_RTS_PIN_Pos   (0UL)
 
#define UARTE_PSEL_RTS_PIN_Msk   (0x1FUL << UARTE_PSEL_RTS_PIN_Pos)
 
#define UARTE_PSEL_TXD_CONNECT_Pos   (31UL)
 
#define UARTE_PSEL_TXD_CONNECT_Msk   (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos)
 
#define UARTE_PSEL_TXD_CONNECT_Connected   (0UL)
 
#define UARTE_PSEL_TXD_CONNECT_Disconnected   (1UL)
 
#define UARTE_PSEL_TXD_PIN_Pos   (0UL)
 
#define UARTE_PSEL_TXD_PIN_Msk   (0x1FUL << UARTE_PSEL_TXD_PIN_Pos)
 
#define UARTE_PSEL_CTS_CONNECT_Pos   (31UL)
 
#define UARTE_PSEL_CTS_CONNECT_Msk   (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos)
 
#define UARTE_PSEL_CTS_CONNECT_Connected   (0UL)
 
#define UARTE_PSEL_CTS_CONNECT_Disconnected   (1UL)
 
#define UARTE_PSEL_CTS_PIN_Pos   (0UL)
 
#define UARTE_PSEL_CTS_PIN_Msk   (0x1FUL << UARTE_PSEL_CTS_PIN_Pos)
 
#define UARTE_PSEL_RXD_CONNECT_Pos   (31UL)
 
#define UARTE_PSEL_RXD_CONNECT_Msk   (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos)
 
#define UARTE_PSEL_RXD_CONNECT_Connected   (0UL)
 
#define UARTE_PSEL_RXD_CONNECT_Disconnected   (1UL)
 
#define UARTE_PSEL_RXD_PIN_Pos   (0UL)
 
#define UARTE_PSEL_RXD_PIN_Msk   (0x1FUL << UARTE_PSEL_RXD_PIN_Pos)
 
#define UARTE_BAUDRATE_BAUDRATE_Pos   (0UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Msk   (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud1200   (0x0004F000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud2400   (0x0009D000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud4800   (0x0013B000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud9600   (0x00275000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud14400   (0x003AF000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud19200   (0x004EA000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud28800   (0x0075C000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud31250   (0x00800000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud38400   (0x009D0000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud56000   (0x00E50000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud57600   (0x00EB0000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud76800   (0x013A9000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud115200   (0x01D60000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud230400   (0x03B00000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud250000   (0x04000000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud460800   (0x07400000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud921600   (0x0F000000UL)
 
#define UARTE_BAUDRATE_BAUDRATE_Baud1M   (0x10000000UL)
 
#define UARTE_RXD_PTR_PTR_Pos   (0UL)
 
#define UARTE_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos)
 
#define UARTE_RXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define UARTE_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos)
 
#define UARTE_RXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define UARTE_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos)
 
#define UARTE_TXD_PTR_PTR_Pos   (0UL)
 
#define UARTE_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos)
 
#define UARTE_TXD_MAXCNT_MAXCNT_Pos   (0UL)
 
#define UARTE_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos)
 
#define UARTE_TXD_AMOUNT_AMOUNT_Pos   (0UL)
 
#define UARTE_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos)
 
#define UARTE_CONFIG_PARITY_Pos   (1UL)
 
#define UARTE_CONFIG_PARITY_Msk   (0x7UL << UARTE_CONFIG_PARITY_Pos)
 
#define UARTE_CONFIG_PARITY_Excluded   (0x0UL)
 
#define UARTE_CONFIG_PARITY_Included   (0x7UL)
 
#define UARTE_CONFIG_HWFC_Pos   (0UL)
 
#define UARTE_CONFIG_HWFC_Msk   (0x1UL << UARTE_CONFIG_HWFC_Pos)
 
#define UARTE_CONFIG_HWFC_Disabled   (0UL)
 
#define UARTE_CONFIG_HWFC_Enabled   (1UL)
 
#define UICR_NRFFW_NRFFW_Pos   (0UL)
 
#define UICR_NRFFW_NRFFW_Msk   (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos)
 
#define UICR_NRFHW_NRFHW_Pos   (0UL)
 
#define UICR_NRFHW_NRFHW_Msk   (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos)
 
#define UICR_CUSTOMER_CUSTOMER_Pos   (0UL)
 
#define UICR_CUSTOMER_CUSTOMER_Msk   (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos)
 
#define UICR_PSELRESET_CONNECT_Pos   (31UL)
 
#define UICR_PSELRESET_CONNECT_Msk   (0x1UL << UICR_PSELRESET_CONNECT_Pos)
 
#define UICR_PSELRESET_CONNECT_Connected   (0UL)
 
#define UICR_PSELRESET_CONNECT_Disconnected   (1UL)
 
#define UICR_PSELRESET_PIN_Pos   (0UL)
 
#define UICR_PSELRESET_PIN_Msk   (0x3FUL << UICR_PSELRESET_PIN_Pos)
 
#define UICR_APPROTECT_PALL_Pos   (0UL)
 
#define UICR_APPROTECT_PALL_Msk   (0xFFUL << UICR_APPROTECT_PALL_Pos)
 
#define UICR_APPROTECT_PALL_Enabled   (0x00UL)
 
#define UICR_APPROTECT_PALL_Disabled   (0xFFUL)
 
#define UICR_NFCPINS_PROTECT_Pos   (0UL)
 
#define UICR_NFCPINS_PROTECT_Msk   (0x1UL << UICR_NFCPINS_PROTECT_Pos)
 
#define UICR_NFCPINS_PROTECT_Disabled   (0UL)
 
#define UICR_NFCPINS_PROTECT_NFC   (1UL)
 
#define WDT_INTENSET_TIMEOUT_Pos   (0UL)
 
#define WDT_INTENSET_TIMEOUT_Msk   (0x1UL << WDT_INTENSET_TIMEOUT_Pos)
 
#define WDT_INTENSET_TIMEOUT_Disabled   (0UL)
 
#define WDT_INTENSET_TIMEOUT_Enabled   (1UL)
 
#define WDT_INTENSET_TIMEOUT_Set   (1UL)
 
#define WDT_INTENCLR_TIMEOUT_Pos   (0UL)
 
#define WDT_INTENCLR_TIMEOUT_Msk   (0x1UL << WDT_INTENCLR_TIMEOUT_Pos)
 
#define WDT_INTENCLR_TIMEOUT_Disabled   (0UL)
 
#define WDT_INTENCLR_TIMEOUT_Enabled   (1UL)
 
#define WDT_INTENCLR_TIMEOUT_Clear   (1UL)
 
#define WDT_RUNSTATUS_RUNSTATUS_Pos   (0UL)
 
#define WDT_RUNSTATUS_RUNSTATUS_Msk   (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos)
 
#define WDT_RUNSTATUS_RUNSTATUS_NotRunning   (0UL)
 
#define WDT_RUNSTATUS_RUNSTATUS_Running   (1UL)
 
#define WDT_REQSTATUS_RR7_Pos   (7UL)
 
#define WDT_REQSTATUS_RR7_Msk   (0x1UL << WDT_REQSTATUS_RR7_Pos)
 
#define WDT_REQSTATUS_RR7_DisabledOrRequested   (0UL)
 
#define WDT_REQSTATUS_RR7_EnabledAndUnrequested   (1UL)
 
#define WDT_REQSTATUS_RR6_Pos   (6UL)
 
#define WDT_REQSTATUS_RR6_Msk   (0x1UL << WDT_REQSTATUS_RR6_Pos)
 
#define WDT_REQSTATUS_RR6_DisabledOrRequested   (0UL)
 
#define WDT_REQSTATUS_RR6_EnabledAndUnrequested   (1UL)
 
#define WDT_REQSTATUS_RR5_Pos   (5UL)
 
#define WDT_REQSTATUS_RR5_Msk   (0x1UL << WDT_REQSTATUS_RR5_Pos)
 
#define WDT_REQSTATUS_RR5_DisabledOrRequested   (0UL)
 
#define WDT_REQSTATUS_RR5_EnabledAndUnrequested   (1UL)
 
#define WDT_REQSTATUS_RR4_Pos   (4UL)
 
#define WDT_REQSTATUS_RR4_Msk   (0x1UL << WDT_REQSTATUS_RR4_Pos)
 
#define WDT_REQSTATUS_RR4_DisabledOrRequested   (0UL)
 
#define WDT_REQSTATUS_RR4_EnabledAndUnrequested   (1UL)
 
#define WDT_REQSTATUS_RR3_Pos   (3UL)
 
#define WDT_REQSTATUS_RR3_Msk   (0x1UL << WDT_REQSTATUS_RR3_Pos)
 
#define WDT_REQSTATUS_RR3_DisabledOrRequested   (0UL)
 
#define WDT_REQSTATUS_RR3_EnabledAndUnrequested   (1UL)
 
#define WDT_REQSTATUS_RR2_Pos   (2UL)
 
#define WDT_REQSTATUS_RR2_Msk   (0x1UL << WDT_REQSTATUS_RR2_Pos)
 
#define WDT_REQSTATUS_RR2_DisabledOrRequested   (0UL)
 
#define WDT_REQSTATUS_RR2_EnabledAndUnrequested   (1UL)
 
#define WDT_REQSTATUS_RR1_Pos   (1UL)
 
#define WDT_REQSTATUS_RR1_Msk   (0x1UL << WDT_REQSTATUS_RR1_Pos)
 
#define WDT_REQSTATUS_RR1_DisabledOrRequested   (0UL)
 
#define WDT_REQSTATUS_RR1_EnabledAndUnrequested   (1UL)
 
#define WDT_REQSTATUS_RR0_Pos   (0UL)
 
#define WDT_REQSTATUS_RR0_Msk   (0x1UL << WDT_REQSTATUS_RR0_Pos)
 
#define WDT_REQSTATUS_RR0_DisabledOrRequested   (0UL)
 
#define WDT_REQSTATUS_RR0_EnabledAndUnrequested   (1UL)
 
#define WDT_CRV_CRV_Pos   (0UL)
 
#define WDT_CRV_CRV_Msk   (0xFFFFFFFFUL << WDT_CRV_CRV_Pos)
 
#define WDT_RREN_RR7_Pos   (7UL)
 
#define WDT_RREN_RR7_Msk   (0x1UL << WDT_RREN_RR7_Pos)
 
#define WDT_RREN_RR7_Disabled   (0UL)
 
#define WDT_RREN_RR7_Enabled   (1UL)
 
#define WDT_RREN_RR6_Pos   (6UL)
 
#define WDT_RREN_RR6_Msk   (0x1UL << WDT_RREN_RR6_Pos)
 
#define WDT_RREN_RR6_Disabled   (0UL)
 
#define WDT_RREN_RR6_Enabled   (1UL)
 
#define WDT_RREN_RR5_Pos   (5UL)
 
#define WDT_RREN_RR5_Msk   (0x1UL << WDT_RREN_RR5_Pos)
 
#define WDT_RREN_RR5_Disabled   (0UL)
 
#define WDT_RREN_RR5_Enabled   (1UL)
 
#define WDT_RREN_RR4_Pos   (4UL)
 
#define WDT_RREN_RR4_Msk   (0x1UL << WDT_RREN_RR4_Pos)
 
#define WDT_RREN_RR4_Disabled   (0UL)
 
#define WDT_RREN_RR4_Enabled   (1UL)
 
#define WDT_RREN_RR3_Pos   (3UL)
 
#define WDT_RREN_RR3_Msk   (0x1UL << WDT_RREN_RR3_Pos)
 
#define WDT_RREN_RR3_Disabled   (0UL)
 
#define WDT_RREN_RR3_Enabled   (1UL)
 
#define WDT_RREN_RR2_Pos   (2UL)
 
#define WDT_RREN_RR2_Msk   (0x1UL << WDT_RREN_RR2_Pos)
 
#define WDT_RREN_RR2_Disabled   (0UL)
 
#define WDT_RREN_RR2_Enabled   (1UL)
 
#define WDT_RREN_RR1_Pos   (1UL)
 
#define WDT_RREN_RR1_Msk   (0x1UL << WDT_RREN_RR1_Pos)
 
#define WDT_RREN_RR1_Disabled   (0UL)
 
#define WDT_RREN_RR1_Enabled   (1UL)
 
#define WDT_RREN_RR0_Pos   (0UL)
 
#define WDT_RREN_RR0_Msk   (0x1UL << WDT_RREN_RR0_Pos)
 
#define WDT_RREN_RR0_Disabled   (0UL)
 
#define WDT_RREN_RR0_Enabled   (1UL)
 
#define WDT_CONFIG_HALT_Pos   (3UL)
 
#define WDT_CONFIG_HALT_Msk   (0x1UL << WDT_CONFIG_HALT_Pos)
 
#define WDT_CONFIG_HALT_Pause   (0UL)
 
#define WDT_CONFIG_HALT_Run   (1UL)
 
#define WDT_CONFIG_SLEEP_Pos   (0UL)
 
#define WDT_CONFIG_SLEEP_Msk   (0x1UL << WDT_CONFIG_SLEEP_Pos)
 
#define WDT_CONFIG_SLEEP_Pause   (0UL)
 
#define WDT_CONFIG_SLEEP_Run   (1UL)
 
#define WDT_RR_RR_Pos   (0UL)
 
#define WDT_RR_RR_Msk   (0xFFFFFFFFUL << WDT_RR_RR_Pos)
 
#define WDT_RR_RR_Reload   (0x6E524635UL)
 

Macro Definition Documentation

◆ AAR_ADDRPTR_ADDRPTR_Msk

#define AAR_ADDRPTR_ADDRPTR_Msk   (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos)

Bit mask of ADDRPTR field.

◆ AAR_ADDRPTR_ADDRPTR_Pos

#define AAR_ADDRPTR_ADDRPTR_Pos   (0UL)

Position of ADDRPTR field.

◆ AAR_ENABLE_ENABLE_Disabled

#define AAR_ENABLE_ENABLE_Disabled   (0UL)

Disable

◆ AAR_ENABLE_ENABLE_Enabled

#define AAR_ENABLE_ENABLE_Enabled   (3UL)

Enable

◆ AAR_ENABLE_ENABLE_Msk

#define AAR_ENABLE_ENABLE_Msk   (0x3UL << AAR_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ AAR_ENABLE_ENABLE_Pos

#define AAR_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ AAR_INTENCLR_END_Clear

#define AAR_INTENCLR_END_Clear   (1UL)

Disable

◆ AAR_INTENCLR_END_Disabled

#define AAR_INTENCLR_END_Disabled   (0UL)

Read: Disabled

◆ AAR_INTENCLR_END_Enabled

#define AAR_INTENCLR_END_Enabled   (1UL)

Read: Enabled

◆ AAR_INTENCLR_END_Msk

#define AAR_INTENCLR_END_Msk   (0x1UL << AAR_INTENCLR_END_Pos)

Bit mask of END field.

◆ AAR_INTENCLR_END_Pos

#define AAR_INTENCLR_END_Pos   (0UL)

Position of END field.

◆ AAR_INTENCLR_NOTRESOLVED_Clear

#define AAR_INTENCLR_NOTRESOLVED_Clear   (1UL)

Disable

◆ AAR_INTENCLR_NOTRESOLVED_Disabled

#define AAR_INTENCLR_NOTRESOLVED_Disabled   (0UL)

Read: Disabled

◆ AAR_INTENCLR_NOTRESOLVED_Enabled

#define AAR_INTENCLR_NOTRESOLVED_Enabled   (1UL)

Read: Enabled

◆ AAR_INTENCLR_NOTRESOLVED_Msk

#define AAR_INTENCLR_NOTRESOLVED_Msk   (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos)

Bit mask of NOTRESOLVED field.

◆ AAR_INTENCLR_NOTRESOLVED_Pos

#define AAR_INTENCLR_NOTRESOLVED_Pos   (2UL)

Position of NOTRESOLVED field.

◆ AAR_INTENCLR_RESOLVED_Clear

#define AAR_INTENCLR_RESOLVED_Clear   (1UL)

Disable

◆ AAR_INTENCLR_RESOLVED_Disabled

#define AAR_INTENCLR_RESOLVED_Disabled   (0UL)

Read: Disabled

◆ AAR_INTENCLR_RESOLVED_Enabled

#define AAR_INTENCLR_RESOLVED_Enabled   (1UL)

Read: Enabled

◆ AAR_INTENCLR_RESOLVED_Msk

#define AAR_INTENCLR_RESOLVED_Msk   (0x1UL << AAR_INTENCLR_RESOLVED_Pos)

Bit mask of RESOLVED field.

◆ AAR_INTENCLR_RESOLVED_Pos

#define AAR_INTENCLR_RESOLVED_Pos   (1UL)

Position of RESOLVED field.

◆ AAR_INTENSET_END_Disabled

#define AAR_INTENSET_END_Disabled   (0UL)

Read: Disabled

◆ AAR_INTENSET_END_Enabled

#define AAR_INTENSET_END_Enabled   (1UL)

Read: Enabled

◆ AAR_INTENSET_END_Msk

#define AAR_INTENSET_END_Msk   (0x1UL << AAR_INTENSET_END_Pos)

Bit mask of END field.

◆ AAR_INTENSET_END_Pos

#define AAR_INTENSET_END_Pos   (0UL)

Position of END field.

◆ AAR_INTENSET_END_Set

#define AAR_INTENSET_END_Set   (1UL)

Enable

◆ AAR_INTENSET_NOTRESOLVED_Disabled

#define AAR_INTENSET_NOTRESOLVED_Disabled   (0UL)

Read: Disabled

◆ AAR_INTENSET_NOTRESOLVED_Enabled

#define AAR_INTENSET_NOTRESOLVED_Enabled   (1UL)

Read: Enabled

◆ AAR_INTENSET_NOTRESOLVED_Msk

#define AAR_INTENSET_NOTRESOLVED_Msk   (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos)

Bit mask of NOTRESOLVED field.

◆ AAR_INTENSET_NOTRESOLVED_Pos

#define AAR_INTENSET_NOTRESOLVED_Pos   (2UL)

Position of NOTRESOLVED field.

◆ AAR_INTENSET_NOTRESOLVED_Set

#define AAR_INTENSET_NOTRESOLVED_Set   (1UL)

Enable

◆ AAR_INTENSET_RESOLVED_Disabled

#define AAR_INTENSET_RESOLVED_Disabled   (0UL)

Read: Disabled

◆ AAR_INTENSET_RESOLVED_Enabled

#define AAR_INTENSET_RESOLVED_Enabled   (1UL)

Read: Enabled

◆ AAR_INTENSET_RESOLVED_Msk

#define AAR_INTENSET_RESOLVED_Msk   (0x1UL << AAR_INTENSET_RESOLVED_Pos)

Bit mask of RESOLVED field.

◆ AAR_INTENSET_RESOLVED_Pos

#define AAR_INTENSET_RESOLVED_Pos   (1UL)

Position of RESOLVED field.

◆ AAR_INTENSET_RESOLVED_Set

#define AAR_INTENSET_RESOLVED_Set   (1UL)

Enable

◆ AAR_IRKPTR_IRKPTR_Msk

#define AAR_IRKPTR_IRKPTR_Msk   (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos)

Bit mask of IRKPTR field.

◆ AAR_IRKPTR_IRKPTR_Pos

#define AAR_IRKPTR_IRKPTR_Pos   (0UL)

Position of IRKPTR field.

◆ AAR_NIRK_NIRK_Msk

#define AAR_NIRK_NIRK_Msk   (0x1FUL << AAR_NIRK_NIRK_Pos)

Bit mask of NIRK field.

◆ AAR_NIRK_NIRK_Pos

#define AAR_NIRK_NIRK_Pos   (0UL)

Position of NIRK field.

◆ AAR_SCRATCHPTR_SCRATCHPTR_Msk

#define AAR_SCRATCHPTR_SCRATCHPTR_Msk   (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos)

Bit mask of SCRATCHPTR field.

◆ AAR_SCRATCHPTR_SCRATCHPTR_Pos

#define AAR_SCRATCHPTR_SCRATCHPTR_Pos   (0UL)

Position of SCRATCHPTR field.

◆ AAR_STATUS_STATUS_Msk

#define AAR_STATUS_STATUS_Msk   (0xFUL << AAR_STATUS_STATUS_Pos)

Bit mask of STATUS field.

◆ AAR_STATUS_STATUS_Pos

#define AAR_STATUS_STATUS_Pos   (0UL)

Position of STATUS field.

◆ BPROT_CONFIG0_REGION0_Disabled

#define BPROT_CONFIG0_REGION0_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION0_Enabled

#define BPROT_CONFIG0_REGION0_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION0_Msk

#define BPROT_CONFIG0_REGION0_Msk   (0x1UL << BPROT_CONFIG0_REGION0_Pos)

Bit mask of REGION0 field.

◆ BPROT_CONFIG0_REGION0_Pos

#define BPROT_CONFIG0_REGION0_Pos   (0UL)

Position of REGION0 field.

◆ BPROT_CONFIG0_REGION10_Disabled

#define BPROT_CONFIG0_REGION10_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION10_Enabled

#define BPROT_CONFIG0_REGION10_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION10_Msk

#define BPROT_CONFIG0_REGION10_Msk   (0x1UL << BPROT_CONFIG0_REGION10_Pos)

Bit mask of REGION10 field.

◆ BPROT_CONFIG0_REGION10_Pos

#define BPROT_CONFIG0_REGION10_Pos   (10UL)

Position of REGION10 field.

◆ BPROT_CONFIG0_REGION11_Disabled

#define BPROT_CONFIG0_REGION11_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION11_Enabled

#define BPROT_CONFIG0_REGION11_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION11_Msk

#define BPROT_CONFIG0_REGION11_Msk   (0x1UL << BPROT_CONFIG0_REGION11_Pos)

Bit mask of REGION11 field.

◆ BPROT_CONFIG0_REGION11_Pos

#define BPROT_CONFIG0_REGION11_Pos   (11UL)

Position of REGION11 field.

◆ BPROT_CONFIG0_REGION12_Disabled

#define BPROT_CONFIG0_REGION12_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION12_Enabled

#define BPROT_CONFIG0_REGION12_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION12_Msk

#define BPROT_CONFIG0_REGION12_Msk   (0x1UL << BPROT_CONFIG0_REGION12_Pos)

Bit mask of REGION12 field.

◆ BPROT_CONFIG0_REGION12_Pos

#define BPROT_CONFIG0_REGION12_Pos   (12UL)

Position of REGION12 field.

◆ BPROT_CONFIG0_REGION13_Disabled

#define BPROT_CONFIG0_REGION13_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION13_Enabled

#define BPROT_CONFIG0_REGION13_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION13_Msk

#define BPROT_CONFIG0_REGION13_Msk   (0x1UL << BPROT_CONFIG0_REGION13_Pos)

Bit mask of REGION13 field.

◆ BPROT_CONFIG0_REGION13_Pos

#define BPROT_CONFIG0_REGION13_Pos   (13UL)

Position of REGION13 field.

◆ BPROT_CONFIG0_REGION14_Disabled

#define BPROT_CONFIG0_REGION14_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION14_Enabled

#define BPROT_CONFIG0_REGION14_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION14_Msk

#define BPROT_CONFIG0_REGION14_Msk   (0x1UL << BPROT_CONFIG0_REGION14_Pos)

Bit mask of REGION14 field.

◆ BPROT_CONFIG0_REGION14_Pos

#define BPROT_CONFIG0_REGION14_Pos   (14UL)

Position of REGION14 field.

◆ BPROT_CONFIG0_REGION15_Disabled

#define BPROT_CONFIG0_REGION15_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION15_Enabled

#define BPROT_CONFIG0_REGION15_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION15_Msk

#define BPROT_CONFIG0_REGION15_Msk   (0x1UL << BPROT_CONFIG0_REGION15_Pos)

Bit mask of REGION15 field.

◆ BPROT_CONFIG0_REGION15_Pos

#define BPROT_CONFIG0_REGION15_Pos   (15UL)

Position of REGION15 field.

◆ BPROT_CONFIG0_REGION16_Disabled

#define BPROT_CONFIG0_REGION16_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION16_Enabled

#define BPROT_CONFIG0_REGION16_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION16_Msk

#define BPROT_CONFIG0_REGION16_Msk   (0x1UL << BPROT_CONFIG0_REGION16_Pos)

Bit mask of REGION16 field.

◆ BPROT_CONFIG0_REGION16_Pos

#define BPROT_CONFIG0_REGION16_Pos   (16UL)

Position of REGION16 field.

◆ BPROT_CONFIG0_REGION17_Disabled

#define BPROT_CONFIG0_REGION17_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION17_Enabled

#define BPROT_CONFIG0_REGION17_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION17_Msk

#define BPROT_CONFIG0_REGION17_Msk   (0x1UL << BPROT_CONFIG0_REGION17_Pos)

Bit mask of REGION17 field.

◆ BPROT_CONFIG0_REGION17_Pos

#define BPROT_CONFIG0_REGION17_Pos   (17UL)

Position of REGION17 field.

◆ BPROT_CONFIG0_REGION18_Disabled

#define BPROT_CONFIG0_REGION18_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION18_Enabled

#define BPROT_CONFIG0_REGION18_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION18_Msk

#define BPROT_CONFIG0_REGION18_Msk   (0x1UL << BPROT_CONFIG0_REGION18_Pos)

Bit mask of REGION18 field.

◆ BPROT_CONFIG0_REGION18_Pos

#define BPROT_CONFIG0_REGION18_Pos   (18UL)

Position of REGION18 field.

◆ BPROT_CONFIG0_REGION19_Disabled

#define BPROT_CONFIG0_REGION19_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION19_Enabled

#define BPROT_CONFIG0_REGION19_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION19_Msk

#define BPROT_CONFIG0_REGION19_Msk   (0x1UL << BPROT_CONFIG0_REGION19_Pos)

Bit mask of REGION19 field.

◆ BPROT_CONFIG0_REGION19_Pos

#define BPROT_CONFIG0_REGION19_Pos   (19UL)

Position of REGION19 field.

◆ BPROT_CONFIG0_REGION1_Disabled

#define BPROT_CONFIG0_REGION1_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION1_Enabled

#define BPROT_CONFIG0_REGION1_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION1_Msk

#define BPROT_CONFIG0_REGION1_Msk   (0x1UL << BPROT_CONFIG0_REGION1_Pos)

Bit mask of REGION1 field.

◆ BPROT_CONFIG0_REGION1_Pos

#define BPROT_CONFIG0_REGION1_Pos   (1UL)

Position of REGION1 field.

◆ BPROT_CONFIG0_REGION20_Disabled

#define BPROT_CONFIG0_REGION20_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION20_Enabled

#define BPROT_CONFIG0_REGION20_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION20_Msk

#define BPROT_CONFIG0_REGION20_Msk   (0x1UL << BPROT_CONFIG0_REGION20_Pos)

Bit mask of REGION20 field.

◆ BPROT_CONFIG0_REGION20_Pos

#define BPROT_CONFIG0_REGION20_Pos   (20UL)

Position of REGION20 field.

◆ BPROT_CONFIG0_REGION21_Disabled

#define BPROT_CONFIG0_REGION21_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION21_Enabled

#define BPROT_CONFIG0_REGION21_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION21_Msk

#define BPROT_CONFIG0_REGION21_Msk   (0x1UL << BPROT_CONFIG0_REGION21_Pos)

Bit mask of REGION21 field.

◆ BPROT_CONFIG0_REGION21_Pos

#define BPROT_CONFIG0_REGION21_Pos   (21UL)

Position of REGION21 field.

◆ BPROT_CONFIG0_REGION22_Disabled

#define BPROT_CONFIG0_REGION22_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION22_Enabled

#define BPROT_CONFIG0_REGION22_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION22_Msk

#define BPROT_CONFIG0_REGION22_Msk   (0x1UL << BPROT_CONFIG0_REGION22_Pos)

Bit mask of REGION22 field.

◆ BPROT_CONFIG0_REGION22_Pos

#define BPROT_CONFIG0_REGION22_Pos   (22UL)

Position of REGION22 field.

◆ BPROT_CONFIG0_REGION23_Disabled

#define BPROT_CONFIG0_REGION23_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION23_Enabled

#define BPROT_CONFIG0_REGION23_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION23_Msk

#define BPROT_CONFIG0_REGION23_Msk   (0x1UL << BPROT_CONFIG0_REGION23_Pos)

Bit mask of REGION23 field.

◆ BPROT_CONFIG0_REGION23_Pos

#define BPROT_CONFIG0_REGION23_Pos   (23UL)

Position of REGION23 field.

◆ BPROT_CONFIG0_REGION24_Disabled

#define BPROT_CONFIG0_REGION24_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION24_Enabled

#define BPROT_CONFIG0_REGION24_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION24_Msk

#define BPROT_CONFIG0_REGION24_Msk   (0x1UL << BPROT_CONFIG0_REGION24_Pos)

Bit mask of REGION24 field.

◆ BPROT_CONFIG0_REGION24_Pos

#define BPROT_CONFIG0_REGION24_Pos   (24UL)

Position of REGION24 field.

◆ BPROT_CONFIG0_REGION25_Disabled

#define BPROT_CONFIG0_REGION25_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION25_Enabled

#define BPROT_CONFIG0_REGION25_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION25_Msk

#define BPROT_CONFIG0_REGION25_Msk   (0x1UL << BPROT_CONFIG0_REGION25_Pos)

Bit mask of REGION25 field.

◆ BPROT_CONFIG0_REGION25_Pos

#define BPROT_CONFIG0_REGION25_Pos   (25UL)

Position of REGION25 field.

◆ BPROT_CONFIG0_REGION26_Disabled

#define BPROT_CONFIG0_REGION26_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION26_Enabled

#define BPROT_CONFIG0_REGION26_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION26_Msk

#define BPROT_CONFIG0_REGION26_Msk   (0x1UL << BPROT_CONFIG0_REGION26_Pos)

Bit mask of REGION26 field.

◆ BPROT_CONFIG0_REGION26_Pos

#define BPROT_CONFIG0_REGION26_Pos   (26UL)

Position of REGION26 field.

◆ BPROT_CONFIG0_REGION27_Disabled

#define BPROT_CONFIG0_REGION27_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION27_Enabled

#define BPROT_CONFIG0_REGION27_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION27_Msk

#define BPROT_CONFIG0_REGION27_Msk   (0x1UL << BPROT_CONFIG0_REGION27_Pos)

Bit mask of REGION27 field.

◆ BPROT_CONFIG0_REGION27_Pos

#define BPROT_CONFIG0_REGION27_Pos   (27UL)

Position of REGION27 field.

◆ BPROT_CONFIG0_REGION28_Disabled

#define BPROT_CONFIG0_REGION28_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION28_Enabled

#define BPROT_CONFIG0_REGION28_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION28_Msk

#define BPROT_CONFIG0_REGION28_Msk   (0x1UL << BPROT_CONFIG0_REGION28_Pos)

Bit mask of REGION28 field.

◆ BPROT_CONFIG0_REGION28_Pos

#define BPROT_CONFIG0_REGION28_Pos   (28UL)

Position of REGION28 field.

◆ BPROT_CONFIG0_REGION29_Disabled

#define BPROT_CONFIG0_REGION29_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION29_Enabled

#define BPROT_CONFIG0_REGION29_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION29_Msk

#define BPROT_CONFIG0_REGION29_Msk   (0x1UL << BPROT_CONFIG0_REGION29_Pos)

Bit mask of REGION29 field.

◆ BPROT_CONFIG0_REGION29_Pos

#define BPROT_CONFIG0_REGION29_Pos   (29UL)

Position of REGION29 field.

◆ BPROT_CONFIG0_REGION2_Disabled

#define BPROT_CONFIG0_REGION2_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION2_Enabled

#define BPROT_CONFIG0_REGION2_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION2_Msk

#define BPROT_CONFIG0_REGION2_Msk   (0x1UL << BPROT_CONFIG0_REGION2_Pos)

Bit mask of REGION2 field.

◆ BPROT_CONFIG0_REGION2_Pos

#define BPROT_CONFIG0_REGION2_Pos   (2UL)

Position of REGION2 field.

◆ BPROT_CONFIG0_REGION30_Disabled

#define BPROT_CONFIG0_REGION30_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION30_Enabled

#define BPROT_CONFIG0_REGION30_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION30_Msk

#define BPROT_CONFIG0_REGION30_Msk   (0x1UL << BPROT_CONFIG0_REGION30_Pos)

Bit mask of REGION30 field.

◆ BPROT_CONFIG0_REGION30_Pos

#define BPROT_CONFIG0_REGION30_Pos   (30UL)

Position of REGION30 field.

◆ BPROT_CONFIG0_REGION31_Disabled

#define BPROT_CONFIG0_REGION31_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION31_Enabled

#define BPROT_CONFIG0_REGION31_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION31_Msk

#define BPROT_CONFIG0_REGION31_Msk   (0x1UL << BPROT_CONFIG0_REGION31_Pos)

Bit mask of REGION31 field.

◆ BPROT_CONFIG0_REGION31_Pos

#define BPROT_CONFIG0_REGION31_Pos   (31UL)

Position of REGION31 field.

◆ BPROT_CONFIG0_REGION3_Disabled

#define BPROT_CONFIG0_REGION3_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION3_Enabled

#define BPROT_CONFIG0_REGION3_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION3_Msk

#define BPROT_CONFIG0_REGION3_Msk   (0x1UL << BPROT_CONFIG0_REGION3_Pos)

Bit mask of REGION3 field.

◆ BPROT_CONFIG0_REGION3_Pos

#define BPROT_CONFIG0_REGION3_Pos   (3UL)

Position of REGION3 field.

◆ BPROT_CONFIG0_REGION4_Disabled

#define BPROT_CONFIG0_REGION4_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION4_Enabled

#define BPROT_CONFIG0_REGION4_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION4_Msk

#define BPROT_CONFIG0_REGION4_Msk   (0x1UL << BPROT_CONFIG0_REGION4_Pos)

Bit mask of REGION4 field.

◆ BPROT_CONFIG0_REGION4_Pos

#define BPROT_CONFIG0_REGION4_Pos   (4UL)

Position of REGION4 field.

◆ BPROT_CONFIG0_REGION5_Disabled

#define BPROT_CONFIG0_REGION5_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION5_Enabled

#define BPROT_CONFIG0_REGION5_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION5_Msk

#define BPROT_CONFIG0_REGION5_Msk   (0x1UL << BPROT_CONFIG0_REGION5_Pos)

Bit mask of REGION5 field.

◆ BPROT_CONFIG0_REGION5_Pos

#define BPROT_CONFIG0_REGION5_Pos   (5UL)

Position of REGION5 field.

◆ BPROT_CONFIG0_REGION6_Disabled

#define BPROT_CONFIG0_REGION6_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION6_Enabled

#define BPROT_CONFIG0_REGION6_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION6_Msk

#define BPROT_CONFIG0_REGION6_Msk   (0x1UL << BPROT_CONFIG0_REGION6_Pos)

Bit mask of REGION6 field.

◆ BPROT_CONFIG0_REGION6_Pos

#define BPROT_CONFIG0_REGION6_Pos   (6UL)

Position of REGION6 field.

◆ BPROT_CONFIG0_REGION7_Disabled

#define BPROT_CONFIG0_REGION7_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION7_Enabled

#define BPROT_CONFIG0_REGION7_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION7_Msk

#define BPROT_CONFIG0_REGION7_Msk   (0x1UL << BPROT_CONFIG0_REGION7_Pos)

Bit mask of REGION7 field.

◆ BPROT_CONFIG0_REGION7_Pos

#define BPROT_CONFIG0_REGION7_Pos   (7UL)

Position of REGION7 field.

◆ BPROT_CONFIG0_REGION8_Disabled

#define BPROT_CONFIG0_REGION8_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION8_Enabled

#define BPROT_CONFIG0_REGION8_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION8_Msk

#define BPROT_CONFIG0_REGION8_Msk   (0x1UL << BPROT_CONFIG0_REGION8_Pos)

Bit mask of REGION8 field.

◆ BPROT_CONFIG0_REGION8_Pos

#define BPROT_CONFIG0_REGION8_Pos   (8UL)

Position of REGION8 field.

◆ BPROT_CONFIG0_REGION9_Disabled

#define BPROT_CONFIG0_REGION9_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG0_REGION9_Enabled

#define BPROT_CONFIG0_REGION9_Enabled   (1UL)

Protection enable

◆ BPROT_CONFIG0_REGION9_Msk

#define BPROT_CONFIG0_REGION9_Msk   (0x1UL << BPROT_CONFIG0_REGION9_Pos)

Bit mask of REGION9 field.

◆ BPROT_CONFIG0_REGION9_Pos

#define BPROT_CONFIG0_REGION9_Pos   (9UL)

Position of REGION9 field.

◆ BPROT_CONFIG1_REGION32_Disabled

#define BPROT_CONFIG1_REGION32_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION32_Enabled

#define BPROT_CONFIG1_REGION32_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION32_Msk

#define BPROT_CONFIG1_REGION32_Msk   (0x1UL << BPROT_CONFIG1_REGION32_Pos)

Bit mask of REGION32 field.

◆ BPROT_CONFIG1_REGION32_Pos

#define BPROT_CONFIG1_REGION32_Pos   (0UL)

Position of REGION32 field.

◆ BPROT_CONFIG1_REGION33_Disabled

#define BPROT_CONFIG1_REGION33_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION33_Enabled

#define BPROT_CONFIG1_REGION33_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION33_Msk

#define BPROT_CONFIG1_REGION33_Msk   (0x1UL << BPROT_CONFIG1_REGION33_Pos)

Bit mask of REGION33 field.

◆ BPROT_CONFIG1_REGION33_Pos

#define BPROT_CONFIG1_REGION33_Pos   (1UL)

Position of REGION33 field.

◆ BPROT_CONFIG1_REGION34_Disabled

#define BPROT_CONFIG1_REGION34_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION34_Enabled

#define BPROT_CONFIG1_REGION34_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION34_Msk

#define BPROT_CONFIG1_REGION34_Msk   (0x1UL << BPROT_CONFIG1_REGION34_Pos)

Bit mask of REGION34 field.

◆ BPROT_CONFIG1_REGION34_Pos

#define BPROT_CONFIG1_REGION34_Pos   (2UL)

Position of REGION34 field.

◆ BPROT_CONFIG1_REGION35_Disabled

#define BPROT_CONFIG1_REGION35_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION35_Enabled

#define BPROT_CONFIG1_REGION35_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION35_Msk

#define BPROT_CONFIG1_REGION35_Msk   (0x1UL << BPROT_CONFIG1_REGION35_Pos)

Bit mask of REGION35 field.

◆ BPROT_CONFIG1_REGION35_Pos

#define BPROT_CONFIG1_REGION35_Pos   (3UL)

Position of REGION35 field.

◆ BPROT_CONFIG1_REGION36_Disabled

#define BPROT_CONFIG1_REGION36_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION36_Enabled

#define BPROT_CONFIG1_REGION36_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION36_Msk

#define BPROT_CONFIG1_REGION36_Msk   (0x1UL << BPROT_CONFIG1_REGION36_Pos)

Bit mask of REGION36 field.

◆ BPROT_CONFIG1_REGION36_Pos

#define BPROT_CONFIG1_REGION36_Pos   (4UL)

Position of REGION36 field.

◆ BPROT_CONFIG1_REGION37_Disabled

#define BPROT_CONFIG1_REGION37_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION37_Enabled

#define BPROT_CONFIG1_REGION37_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION37_Msk

#define BPROT_CONFIG1_REGION37_Msk   (0x1UL << BPROT_CONFIG1_REGION37_Pos)

Bit mask of REGION37 field.

◆ BPROT_CONFIG1_REGION37_Pos

#define BPROT_CONFIG1_REGION37_Pos   (5UL)

Position of REGION37 field.

◆ BPROT_CONFIG1_REGION38_Disabled

#define BPROT_CONFIG1_REGION38_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION38_Enabled

#define BPROT_CONFIG1_REGION38_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION38_Msk

#define BPROT_CONFIG1_REGION38_Msk   (0x1UL << BPROT_CONFIG1_REGION38_Pos)

Bit mask of REGION38 field.

◆ BPROT_CONFIG1_REGION38_Pos

#define BPROT_CONFIG1_REGION38_Pos   (6UL)

Position of REGION38 field.

◆ BPROT_CONFIG1_REGION39_Disabled

#define BPROT_CONFIG1_REGION39_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION39_Enabled

#define BPROT_CONFIG1_REGION39_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION39_Msk

#define BPROT_CONFIG1_REGION39_Msk   (0x1UL << BPROT_CONFIG1_REGION39_Pos)

Bit mask of REGION39 field.

◆ BPROT_CONFIG1_REGION39_Pos

#define BPROT_CONFIG1_REGION39_Pos   (7UL)

Position of REGION39 field.

◆ BPROT_CONFIG1_REGION40_Disabled

#define BPROT_CONFIG1_REGION40_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION40_Enabled

#define BPROT_CONFIG1_REGION40_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION40_Msk

#define BPROT_CONFIG1_REGION40_Msk   (0x1UL << BPROT_CONFIG1_REGION40_Pos)

Bit mask of REGION40 field.

◆ BPROT_CONFIG1_REGION40_Pos

#define BPROT_CONFIG1_REGION40_Pos   (8UL)

Position of REGION40 field.

◆ BPROT_CONFIG1_REGION41_Disabled

#define BPROT_CONFIG1_REGION41_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION41_Enabled

#define BPROT_CONFIG1_REGION41_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION41_Msk

#define BPROT_CONFIG1_REGION41_Msk   (0x1UL << BPROT_CONFIG1_REGION41_Pos)

Bit mask of REGION41 field.

◆ BPROT_CONFIG1_REGION41_Pos

#define BPROT_CONFIG1_REGION41_Pos   (9UL)

Position of REGION41 field.

◆ BPROT_CONFIG1_REGION42_Disabled

#define BPROT_CONFIG1_REGION42_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION42_Enabled

#define BPROT_CONFIG1_REGION42_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION42_Msk

#define BPROT_CONFIG1_REGION42_Msk   (0x1UL << BPROT_CONFIG1_REGION42_Pos)

Bit mask of REGION42 field.

◆ BPROT_CONFIG1_REGION42_Pos

#define BPROT_CONFIG1_REGION42_Pos   (10UL)

Position of REGION42 field.

◆ BPROT_CONFIG1_REGION43_Disabled

#define BPROT_CONFIG1_REGION43_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION43_Enabled

#define BPROT_CONFIG1_REGION43_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION43_Msk

#define BPROT_CONFIG1_REGION43_Msk   (0x1UL << BPROT_CONFIG1_REGION43_Pos)

Bit mask of REGION43 field.

◆ BPROT_CONFIG1_REGION43_Pos

#define BPROT_CONFIG1_REGION43_Pos   (11UL)

Position of REGION43 field.

◆ BPROT_CONFIG1_REGION44_Disabled

#define BPROT_CONFIG1_REGION44_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION44_Enabled

#define BPROT_CONFIG1_REGION44_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION44_Msk

#define BPROT_CONFIG1_REGION44_Msk   (0x1UL << BPROT_CONFIG1_REGION44_Pos)

Bit mask of REGION44 field.

◆ BPROT_CONFIG1_REGION44_Pos

#define BPROT_CONFIG1_REGION44_Pos   (12UL)

Position of REGION44 field.

◆ BPROT_CONFIG1_REGION45_Disabled

#define BPROT_CONFIG1_REGION45_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION45_Enabled

#define BPROT_CONFIG1_REGION45_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION45_Msk

#define BPROT_CONFIG1_REGION45_Msk   (0x1UL << BPROT_CONFIG1_REGION45_Pos)

Bit mask of REGION45 field.

◆ BPROT_CONFIG1_REGION45_Pos

#define BPROT_CONFIG1_REGION45_Pos   (13UL)

Position of REGION45 field.

◆ BPROT_CONFIG1_REGION46_Disabled

#define BPROT_CONFIG1_REGION46_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION46_Enabled

#define BPROT_CONFIG1_REGION46_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION46_Msk

#define BPROT_CONFIG1_REGION46_Msk   (0x1UL << BPROT_CONFIG1_REGION46_Pos)

Bit mask of REGION46 field.

◆ BPROT_CONFIG1_REGION46_Pos

#define BPROT_CONFIG1_REGION46_Pos   (14UL)

Position of REGION46 field.

◆ BPROT_CONFIG1_REGION47_Disabled

#define BPROT_CONFIG1_REGION47_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION47_Enabled

#define BPROT_CONFIG1_REGION47_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION47_Msk

#define BPROT_CONFIG1_REGION47_Msk   (0x1UL << BPROT_CONFIG1_REGION47_Pos)

Bit mask of REGION47 field.

◆ BPROT_CONFIG1_REGION47_Pos

#define BPROT_CONFIG1_REGION47_Pos   (15UL)

Position of REGION47 field.

◆ BPROT_CONFIG1_REGION48_Disabled

#define BPROT_CONFIG1_REGION48_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION48_Enabled

#define BPROT_CONFIG1_REGION48_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION48_Msk

#define BPROT_CONFIG1_REGION48_Msk   (0x1UL << BPROT_CONFIG1_REGION48_Pos)

Bit mask of REGION48 field.

◆ BPROT_CONFIG1_REGION48_Pos

#define BPROT_CONFIG1_REGION48_Pos   (16UL)

Position of REGION48 field.

◆ BPROT_CONFIG1_REGION49_Disabled

#define BPROT_CONFIG1_REGION49_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION49_Enabled

#define BPROT_CONFIG1_REGION49_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION49_Msk

#define BPROT_CONFIG1_REGION49_Msk   (0x1UL << BPROT_CONFIG1_REGION49_Pos)

Bit mask of REGION49 field.

◆ BPROT_CONFIG1_REGION49_Pos

#define BPROT_CONFIG1_REGION49_Pos   (17UL)

Position of REGION49 field.

◆ BPROT_CONFIG1_REGION50_Disabled

#define BPROT_CONFIG1_REGION50_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION50_Enabled

#define BPROT_CONFIG1_REGION50_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION50_Msk

#define BPROT_CONFIG1_REGION50_Msk   (0x1UL << BPROT_CONFIG1_REGION50_Pos)

Bit mask of REGION50 field.

◆ BPROT_CONFIG1_REGION50_Pos

#define BPROT_CONFIG1_REGION50_Pos   (18UL)

Position of REGION50 field.

◆ BPROT_CONFIG1_REGION51_Disabled

#define BPROT_CONFIG1_REGION51_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION51_Enabled

#define BPROT_CONFIG1_REGION51_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION51_Msk

#define BPROT_CONFIG1_REGION51_Msk   (0x1UL << BPROT_CONFIG1_REGION51_Pos)

Bit mask of REGION51 field.

◆ BPROT_CONFIG1_REGION51_Pos

#define BPROT_CONFIG1_REGION51_Pos   (19UL)

Position of REGION51 field.

◆ BPROT_CONFIG1_REGION52_Disabled

#define BPROT_CONFIG1_REGION52_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION52_Enabled

#define BPROT_CONFIG1_REGION52_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION52_Msk

#define BPROT_CONFIG1_REGION52_Msk   (0x1UL << BPROT_CONFIG1_REGION52_Pos)

Bit mask of REGION52 field.

◆ BPROT_CONFIG1_REGION52_Pos

#define BPROT_CONFIG1_REGION52_Pos   (20UL)

Position of REGION52 field.

◆ BPROT_CONFIG1_REGION53_Disabled

#define BPROT_CONFIG1_REGION53_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION53_Enabled

#define BPROT_CONFIG1_REGION53_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION53_Msk

#define BPROT_CONFIG1_REGION53_Msk   (0x1UL << BPROT_CONFIG1_REGION53_Pos)

Bit mask of REGION53 field.

◆ BPROT_CONFIG1_REGION53_Pos

#define BPROT_CONFIG1_REGION53_Pos   (21UL)

Position of REGION53 field.

◆ BPROT_CONFIG1_REGION54_Disabled

#define BPROT_CONFIG1_REGION54_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION54_Enabled

#define BPROT_CONFIG1_REGION54_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION54_Msk

#define BPROT_CONFIG1_REGION54_Msk   (0x1UL << BPROT_CONFIG1_REGION54_Pos)

Bit mask of REGION54 field.

◆ BPROT_CONFIG1_REGION54_Pos

#define BPROT_CONFIG1_REGION54_Pos   (22UL)

Position of REGION54 field.

◆ BPROT_CONFIG1_REGION55_Disabled

#define BPROT_CONFIG1_REGION55_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION55_Enabled

#define BPROT_CONFIG1_REGION55_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION55_Msk

#define BPROT_CONFIG1_REGION55_Msk   (0x1UL << BPROT_CONFIG1_REGION55_Pos)

Bit mask of REGION55 field.

◆ BPROT_CONFIG1_REGION55_Pos

#define BPROT_CONFIG1_REGION55_Pos   (23UL)

Position of REGION55 field.

◆ BPROT_CONFIG1_REGION56_Disabled

#define BPROT_CONFIG1_REGION56_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION56_Enabled

#define BPROT_CONFIG1_REGION56_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION56_Msk

#define BPROT_CONFIG1_REGION56_Msk   (0x1UL << BPROT_CONFIG1_REGION56_Pos)

Bit mask of REGION56 field.

◆ BPROT_CONFIG1_REGION56_Pos

#define BPROT_CONFIG1_REGION56_Pos   (24UL)

Position of REGION56 field.

◆ BPROT_CONFIG1_REGION57_Disabled

#define BPROT_CONFIG1_REGION57_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION57_Enabled

#define BPROT_CONFIG1_REGION57_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION57_Msk

#define BPROT_CONFIG1_REGION57_Msk   (0x1UL << BPROT_CONFIG1_REGION57_Pos)

Bit mask of REGION57 field.

◆ BPROT_CONFIG1_REGION57_Pos

#define BPROT_CONFIG1_REGION57_Pos   (25UL)

Position of REGION57 field.

◆ BPROT_CONFIG1_REGION58_Disabled

#define BPROT_CONFIG1_REGION58_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION58_Enabled

#define BPROT_CONFIG1_REGION58_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION58_Msk

#define BPROT_CONFIG1_REGION58_Msk   (0x1UL << BPROT_CONFIG1_REGION58_Pos)

Bit mask of REGION58 field.

◆ BPROT_CONFIG1_REGION58_Pos

#define BPROT_CONFIG1_REGION58_Pos   (26UL)

Position of REGION58 field.

◆ BPROT_CONFIG1_REGION59_Disabled

#define BPROT_CONFIG1_REGION59_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION59_Enabled

#define BPROT_CONFIG1_REGION59_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION59_Msk

#define BPROT_CONFIG1_REGION59_Msk   (0x1UL << BPROT_CONFIG1_REGION59_Pos)

Bit mask of REGION59 field.

◆ BPROT_CONFIG1_REGION59_Pos

#define BPROT_CONFIG1_REGION59_Pos   (27UL)

Position of REGION59 field.

◆ BPROT_CONFIG1_REGION60_Disabled

#define BPROT_CONFIG1_REGION60_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION60_Enabled

#define BPROT_CONFIG1_REGION60_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION60_Msk

#define BPROT_CONFIG1_REGION60_Msk   (0x1UL << BPROT_CONFIG1_REGION60_Pos)

Bit mask of REGION60 field.

◆ BPROT_CONFIG1_REGION60_Pos

#define BPROT_CONFIG1_REGION60_Pos   (28UL)

Position of REGION60 field.

◆ BPROT_CONFIG1_REGION61_Disabled

#define BPROT_CONFIG1_REGION61_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION61_Enabled

#define BPROT_CONFIG1_REGION61_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION61_Msk

#define BPROT_CONFIG1_REGION61_Msk   (0x1UL << BPROT_CONFIG1_REGION61_Pos)

Bit mask of REGION61 field.

◆ BPROT_CONFIG1_REGION61_Pos

#define BPROT_CONFIG1_REGION61_Pos   (29UL)

Position of REGION61 field.

◆ BPROT_CONFIG1_REGION62_Disabled

#define BPROT_CONFIG1_REGION62_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION62_Enabled

#define BPROT_CONFIG1_REGION62_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION62_Msk

#define BPROT_CONFIG1_REGION62_Msk   (0x1UL << BPROT_CONFIG1_REGION62_Pos)

Bit mask of REGION62 field.

◆ BPROT_CONFIG1_REGION62_Pos

#define BPROT_CONFIG1_REGION62_Pos   (30UL)

Position of REGION62 field.

◆ BPROT_CONFIG1_REGION63_Disabled

#define BPROT_CONFIG1_REGION63_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG1_REGION63_Enabled

#define BPROT_CONFIG1_REGION63_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG1_REGION63_Msk

#define BPROT_CONFIG1_REGION63_Msk   (0x1UL << BPROT_CONFIG1_REGION63_Pos)

Bit mask of REGION63 field.

◆ BPROT_CONFIG1_REGION63_Pos

#define BPROT_CONFIG1_REGION63_Pos   (31UL)

Position of REGION63 field.

◆ BPROT_CONFIG2_REGION64_Disabled

#define BPROT_CONFIG2_REGION64_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION64_Enabled

#define BPROT_CONFIG2_REGION64_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION64_Msk

#define BPROT_CONFIG2_REGION64_Msk   (0x1UL << BPROT_CONFIG2_REGION64_Pos)

Bit mask of REGION64 field.

◆ BPROT_CONFIG2_REGION64_Pos

#define BPROT_CONFIG2_REGION64_Pos   (0UL)

Position of REGION64 field.

◆ BPROT_CONFIG2_REGION65_Disabled

#define BPROT_CONFIG2_REGION65_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION65_Enabled

#define BPROT_CONFIG2_REGION65_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION65_Msk

#define BPROT_CONFIG2_REGION65_Msk   (0x1UL << BPROT_CONFIG2_REGION65_Pos)

Bit mask of REGION65 field.

◆ BPROT_CONFIG2_REGION65_Pos

#define BPROT_CONFIG2_REGION65_Pos   (1UL)

Position of REGION65 field.

◆ BPROT_CONFIG2_REGION66_Disabled

#define BPROT_CONFIG2_REGION66_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION66_Enabled

#define BPROT_CONFIG2_REGION66_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION66_Msk

#define BPROT_CONFIG2_REGION66_Msk   (0x1UL << BPROT_CONFIG2_REGION66_Pos)

Bit mask of REGION66 field.

◆ BPROT_CONFIG2_REGION66_Pos

#define BPROT_CONFIG2_REGION66_Pos   (2UL)

Position of REGION66 field.

◆ BPROT_CONFIG2_REGION67_Disabled

#define BPROT_CONFIG2_REGION67_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION67_Enabled

#define BPROT_CONFIG2_REGION67_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION67_Msk

#define BPROT_CONFIG2_REGION67_Msk   (0x1UL << BPROT_CONFIG2_REGION67_Pos)

Bit mask of REGION67 field.

◆ BPROT_CONFIG2_REGION67_Pos

#define BPROT_CONFIG2_REGION67_Pos   (3UL)

Position of REGION67 field.

◆ BPROT_CONFIG2_REGION68_Disabled

#define BPROT_CONFIG2_REGION68_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION68_Enabled

#define BPROT_CONFIG2_REGION68_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION68_Msk

#define BPROT_CONFIG2_REGION68_Msk   (0x1UL << BPROT_CONFIG2_REGION68_Pos)

Bit mask of REGION68 field.

◆ BPROT_CONFIG2_REGION68_Pos

#define BPROT_CONFIG2_REGION68_Pos   (4UL)

Position of REGION68 field.

◆ BPROT_CONFIG2_REGION69_Disabled

#define BPROT_CONFIG2_REGION69_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION69_Enabled

#define BPROT_CONFIG2_REGION69_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION69_Msk

#define BPROT_CONFIG2_REGION69_Msk   (0x1UL << BPROT_CONFIG2_REGION69_Pos)

Bit mask of REGION69 field.

◆ BPROT_CONFIG2_REGION69_Pos

#define BPROT_CONFIG2_REGION69_Pos   (5UL)

Position of REGION69 field.

◆ BPROT_CONFIG2_REGION70_Disabled

#define BPROT_CONFIG2_REGION70_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION70_Enabled

#define BPROT_CONFIG2_REGION70_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION70_Msk

#define BPROT_CONFIG2_REGION70_Msk   (0x1UL << BPROT_CONFIG2_REGION70_Pos)

Bit mask of REGION70 field.

◆ BPROT_CONFIG2_REGION70_Pos

#define BPROT_CONFIG2_REGION70_Pos   (6UL)

Position of REGION70 field.

◆ BPROT_CONFIG2_REGION71_Disabled

#define BPROT_CONFIG2_REGION71_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION71_Enabled

#define BPROT_CONFIG2_REGION71_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION71_Msk

#define BPROT_CONFIG2_REGION71_Msk   (0x1UL << BPROT_CONFIG2_REGION71_Pos)

Bit mask of REGION71 field.

◆ BPROT_CONFIG2_REGION71_Pos

#define BPROT_CONFIG2_REGION71_Pos   (7UL)

Position of REGION71 field.

◆ BPROT_CONFIG2_REGION72_Disabled

#define BPROT_CONFIG2_REGION72_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION72_Enabled

#define BPROT_CONFIG2_REGION72_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION72_Msk

#define BPROT_CONFIG2_REGION72_Msk   (0x1UL << BPROT_CONFIG2_REGION72_Pos)

Bit mask of REGION72 field.

◆ BPROT_CONFIG2_REGION72_Pos

#define BPROT_CONFIG2_REGION72_Pos   (8UL)

Position of REGION72 field.

◆ BPROT_CONFIG2_REGION73_Disabled

#define BPROT_CONFIG2_REGION73_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION73_Enabled

#define BPROT_CONFIG2_REGION73_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION73_Msk

#define BPROT_CONFIG2_REGION73_Msk   (0x1UL << BPROT_CONFIG2_REGION73_Pos)

Bit mask of REGION73 field.

◆ BPROT_CONFIG2_REGION73_Pos

#define BPROT_CONFIG2_REGION73_Pos   (9UL)

Position of REGION73 field.

◆ BPROT_CONFIG2_REGION74_Disabled

#define BPROT_CONFIG2_REGION74_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION74_Enabled

#define BPROT_CONFIG2_REGION74_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION74_Msk

#define BPROT_CONFIG2_REGION74_Msk   (0x1UL << BPROT_CONFIG2_REGION74_Pos)

Bit mask of REGION74 field.

◆ BPROT_CONFIG2_REGION74_Pos

#define BPROT_CONFIG2_REGION74_Pos   (10UL)

Position of REGION74 field.

◆ BPROT_CONFIG2_REGION75_Disabled

#define BPROT_CONFIG2_REGION75_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION75_Enabled

#define BPROT_CONFIG2_REGION75_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION75_Msk

#define BPROT_CONFIG2_REGION75_Msk   (0x1UL << BPROT_CONFIG2_REGION75_Pos)

Bit mask of REGION75 field.

◆ BPROT_CONFIG2_REGION75_Pos

#define BPROT_CONFIG2_REGION75_Pos   (11UL)

Position of REGION75 field.

◆ BPROT_CONFIG2_REGION76_Disabled

#define BPROT_CONFIG2_REGION76_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION76_Enabled

#define BPROT_CONFIG2_REGION76_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION76_Msk

#define BPROT_CONFIG2_REGION76_Msk   (0x1UL << BPROT_CONFIG2_REGION76_Pos)

Bit mask of REGION76 field.

◆ BPROT_CONFIG2_REGION76_Pos

#define BPROT_CONFIG2_REGION76_Pos   (12UL)

Position of REGION76 field.

◆ BPROT_CONFIG2_REGION77_Disabled

#define BPROT_CONFIG2_REGION77_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION77_Enabled

#define BPROT_CONFIG2_REGION77_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION77_Msk

#define BPROT_CONFIG2_REGION77_Msk   (0x1UL << BPROT_CONFIG2_REGION77_Pos)

Bit mask of REGION77 field.

◆ BPROT_CONFIG2_REGION77_Pos

#define BPROT_CONFIG2_REGION77_Pos   (13UL)

Position of REGION77 field.

◆ BPROT_CONFIG2_REGION78_Disabled

#define BPROT_CONFIG2_REGION78_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION78_Enabled

#define BPROT_CONFIG2_REGION78_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION78_Msk

#define BPROT_CONFIG2_REGION78_Msk   (0x1UL << BPROT_CONFIG2_REGION78_Pos)

Bit mask of REGION78 field.

◆ BPROT_CONFIG2_REGION78_Pos

#define BPROT_CONFIG2_REGION78_Pos   (14UL)

Position of REGION78 field.

◆ BPROT_CONFIG2_REGION79_Disabled

#define BPROT_CONFIG2_REGION79_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION79_Enabled

#define BPROT_CONFIG2_REGION79_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION79_Msk

#define BPROT_CONFIG2_REGION79_Msk   (0x1UL << BPROT_CONFIG2_REGION79_Pos)

Bit mask of REGION79 field.

◆ BPROT_CONFIG2_REGION79_Pos

#define BPROT_CONFIG2_REGION79_Pos   (15UL)

Position of REGION79 field.

◆ BPROT_CONFIG2_REGION80_Disabled

#define BPROT_CONFIG2_REGION80_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION80_Enabled

#define BPROT_CONFIG2_REGION80_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION80_Msk

#define BPROT_CONFIG2_REGION80_Msk   (0x1UL << BPROT_CONFIG2_REGION80_Pos)

Bit mask of REGION80 field.

◆ BPROT_CONFIG2_REGION80_Pos

#define BPROT_CONFIG2_REGION80_Pos   (16UL)

Position of REGION80 field.

◆ BPROT_CONFIG2_REGION81_Disabled

#define BPROT_CONFIG2_REGION81_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION81_Enabled

#define BPROT_CONFIG2_REGION81_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION81_Msk

#define BPROT_CONFIG2_REGION81_Msk   (0x1UL << BPROT_CONFIG2_REGION81_Pos)

Bit mask of REGION81 field.

◆ BPROT_CONFIG2_REGION81_Pos

#define BPROT_CONFIG2_REGION81_Pos   (17UL)

Position of REGION81 field.

◆ BPROT_CONFIG2_REGION82_Disabled

#define BPROT_CONFIG2_REGION82_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION82_Enabled

#define BPROT_CONFIG2_REGION82_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION82_Msk

#define BPROT_CONFIG2_REGION82_Msk   (0x1UL << BPROT_CONFIG2_REGION82_Pos)

Bit mask of REGION82 field.

◆ BPROT_CONFIG2_REGION82_Pos

#define BPROT_CONFIG2_REGION82_Pos   (18UL)

Position of REGION82 field.

◆ BPROT_CONFIG2_REGION83_Disabled

#define BPROT_CONFIG2_REGION83_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION83_Enabled

#define BPROT_CONFIG2_REGION83_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION83_Msk

#define BPROT_CONFIG2_REGION83_Msk   (0x1UL << BPROT_CONFIG2_REGION83_Pos)

Bit mask of REGION83 field.

◆ BPROT_CONFIG2_REGION83_Pos

#define BPROT_CONFIG2_REGION83_Pos   (19UL)

Position of REGION83 field.

◆ BPROT_CONFIG2_REGION84_Disabled

#define BPROT_CONFIG2_REGION84_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION84_Enabled

#define BPROT_CONFIG2_REGION84_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION84_Msk

#define BPROT_CONFIG2_REGION84_Msk   (0x1UL << BPROT_CONFIG2_REGION84_Pos)

Bit mask of REGION84 field.

◆ BPROT_CONFIG2_REGION84_Pos

#define BPROT_CONFIG2_REGION84_Pos   (20UL)

Position of REGION84 field.

◆ BPROT_CONFIG2_REGION85_Disabled

#define BPROT_CONFIG2_REGION85_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION85_Enabled

#define BPROT_CONFIG2_REGION85_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION85_Msk

#define BPROT_CONFIG2_REGION85_Msk   (0x1UL << BPROT_CONFIG2_REGION85_Pos)

Bit mask of REGION85 field.

◆ BPROT_CONFIG2_REGION85_Pos

#define BPROT_CONFIG2_REGION85_Pos   (21UL)

Position of REGION85 field.

◆ BPROT_CONFIG2_REGION86_Disabled

#define BPROT_CONFIG2_REGION86_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION86_Enabled

#define BPROT_CONFIG2_REGION86_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION86_Msk

#define BPROT_CONFIG2_REGION86_Msk   (0x1UL << BPROT_CONFIG2_REGION86_Pos)

Bit mask of REGION86 field.

◆ BPROT_CONFIG2_REGION86_Pos

#define BPROT_CONFIG2_REGION86_Pos   (22UL)

Position of REGION86 field.

◆ BPROT_CONFIG2_REGION87_Disabled

#define BPROT_CONFIG2_REGION87_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION87_Enabled

#define BPROT_CONFIG2_REGION87_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION87_Msk

#define BPROT_CONFIG2_REGION87_Msk   (0x1UL << BPROT_CONFIG2_REGION87_Pos)

Bit mask of REGION87 field.

◆ BPROT_CONFIG2_REGION87_Pos

#define BPROT_CONFIG2_REGION87_Pos   (23UL)

Position of REGION87 field.

◆ BPROT_CONFIG2_REGION88_Disabled

#define BPROT_CONFIG2_REGION88_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION88_Enabled

#define BPROT_CONFIG2_REGION88_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION88_Msk

#define BPROT_CONFIG2_REGION88_Msk   (0x1UL << BPROT_CONFIG2_REGION88_Pos)

Bit mask of REGION88 field.

◆ BPROT_CONFIG2_REGION88_Pos

#define BPROT_CONFIG2_REGION88_Pos   (24UL)

Position of REGION88 field.

◆ BPROT_CONFIG2_REGION89_Disabled

#define BPROT_CONFIG2_REGION89_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION89_Enabled

#define BPROT_CONFIG2_REGION89_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION89_Msk

#define BPROT_CONFIG2_REGION89_Msk   (0x1UL << BPROT_CONFIG2_REGION89_Pos)

Bit mask of REGION89 field.

◆ BPROT_CONFIG2_REGION89_Pos

#define BPROT_CONFIG2_REGION89_Pos   (25UL)

Position of REGION89 field.

◆ BPROT_CONFIG2_REGION90_Disabled

#define BPROT_CONFIG2_REGION90_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION90_Enabled

#define BPROT_CONFIG2_REGION90_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION90_Msk

#define BPROT_CONFIG2_REGION90_Msk   (0x1UL << BPROT_CONFIG2_REGION90_Pos)

Bit mask of REGION90 field.

◆ BPROT_CONFIG2_REGION90_Pos

#define BPROT_CONFIG2_REGION90_Pos   (26UL)

Position of REGION90 field.

◆ BPROT_CONFIG2_REGION91_Disabled

#define BPROT_CONFIG2_REGION91_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION91_Enabled

#define BPROT_CONFIG2_REGION91_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION91_Msk

#define BPROT_CONFIG2_REGION91_Msk   (0x1UL << BPROT_CONFIG2_REGION91_Pos)

Bit mask of REGION91 field.

◆ BPROT_CONFIG2_REGION91_Pos

#define BPROT_CONFIG2_REGION91_Pos   (27UL)

Position of REGION91 field.

◆ BPROT_CONFIG2_REGION92_Disabled

#define BPROT_CONFIG2_REGION92_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION92_Enabled

#define BPROT_CONFIG2_REGION92_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION92_Msk

#define BPROT_CONFIG2_REGION92_Msk   (0x1UL << BPROT_CONFIG2_REGION92_Pos)

Bit mask of REGION92 field.

◆ BPROT_CONFIG2_REGION92_Pos

#define BPROT_CONFIG2_REGION92_Pos   (28UL)

Position of REGION92 field.

◆ BPROT_CONFIG2_REGION93_Disabled

#define BPROT_CONFIG2_REGION93_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION93_Enabled

#define BPROT_CONFIG2_REGION93_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION93_Msk

#define BPROT_CONFIG2_REGION93_Msk   (0x1UL << BPROT_CONFIG2_REGION93_Pos)

Bit mask of REGION93 field.

◆ BPROT_CONFIG2_REGION93_Pos

#define BPROT_CONFIG2_REGION93_Pos   (29UL)

Position of REGION93 field.

◆ BPROT_CONFIG2_REGION94_Disabled

#define BPROT_CONFIG2_REGION94_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION94_Enabled

#define BPROT_CONFIG2_REGION94_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION94_Msk

#define BPROT_CONFIG2_REGION94_Msk   (0x1UL << BPROT_CONFIG2_REGION94_Pos)

Bit mask of REGION94 field.

◆ BPROT_CONFIG2_REGION94_Pos

#define BPROT_CONFIG2_REGION94_Pos   (30UL)

Position of REGION94 field.

◆ BPROT_CONFIG2_REGION95_Disabled

#define BPROT_CONFIG2_REGION95_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG2_REGION95_Enabled

#define BPROT_CONFIG2_REGION95_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG2_REGION95_Msk

#define BPROT_CONFIG2_REGION95_Msk   (0x1UL << BPROT_CONFIG2_REGION95_Pos)

Bit mask of REGION95 field.

◆ BPROT_CONFIG2_REGION95_Pos

#define BPROT_CONFIG2_REGION95_Pos   (31UL)

Position of REGION95 field.

◆ BPROT_CONFIG3_REGION100_Disabled

#define BPROT_CONFIG3_REGION100_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION100_Enabled

#define BPROT_CONFIG3_REGION100_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION100_Msk

#define BPROT_CONFIG3_REGION100_Msk   (0x1UL << BPROT_CONFIG3_REGION100_Pos)

Bit mask of REGION100 field.

◆ BPROT_CONFIG3_REGION100_Pos

#define BPROT_CONFIG3_REGION100_Pos   (4UL)

Position of REGION100 field.

◆ BPROT_CONFIG3_REGION101_Disabled

#define BPROT_CONFIG3_REGION101_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION101_Enabled

#define BPROT_CONFIG3_REGION101_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION101_Msk

#define BPROT_CONFIG3_REGION101_Msk   (0x1UL << BPROT_CONFIG3_REGION101_Pos)

Bit mask of REGION101 field.

◆ BPROT_CONFIG3_REGION101_Pos

#define BPROT_CONFIG3_REGION101_Pos   (5UL)

Position of REGION101 field.

◆ BPROT_CONFIG3_REGION102_Disabled

#define BPROT_CONFIG3_REGION102_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION102_Enabled

#define BPROT_CONFIG3_REGION102_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION102_Msk

#define BPROT_CONFIG3_REGION102_Msk   (0x1UL << BPROT_CONFIG3_REGION102_Pos)

Bit mask of REGION102 field.

◆ BPROT_CONFIG3_REGION102_Pos

#define BPROT_CONFIG3_REGION102_Pos   (6UL)

Position of REGION102 field.

◆ BPROT_CONFIG3_REGION103_Disabled

#define BPROT_CONFIG3_REGION103_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION103_Enabled

#define BPROT_CONFIG3_REGION103_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION103_Msk

#define BPROT_CONFIG3_REGION103_Msk   (0x1UL << BPROT_CONFIG3_REGION103_Pos)

Bit mask of REGION103 field.

◆ BPROT_CONFIG3_REGION103_Pos

#define BPROT_CONFIG3_REGION103_Pos   (7UL)

Position of REGION103 field.

◆ BPROT_CONFIG3_REGION104_Disabled

#define BPROT_CONFIG3_REGION104_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION104_Enabled

#define BPROT_CONFIG3_REGION104_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION104_Msk

#define BPROT_CONFIG3_REGION104_Msk   (0x1UL << BPROT_CONFIG3_REGION104_Pos)

Bit mask of REGION104 field.

◆ BPROT_CONFIG3_REGION104_Pos

#define BPROT_CONFIG3_REGION104_Pos   (8UL)

Position of REGION104 field.

◆ BPROT_CONFIG3_REGION105_Disabled

#define BPROT_CONFIG3_REGION105_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION105_Enabled

#define BPROT_CONFIG3_REGION105_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION105_Msk

#define BPROT_CONFIG3_REGION105_Msk   (0x1UL << BPROT_CONFIG3_REGION105_Pos)

Bit mask of REGION105 field.

◆ BPROT_CONFIG3_REGION105_Pos

#define BPROT_CONFIG3_REGION105_Pos   (9UL)

Position of REGION105 field.

◆ BPROT_CONFIG3_REGION106_Disabled

#define BPROT_CONFIG3_REGION106_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION106_Enabled

#define BPROT_CONFIG3_REGION106_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION106_Msk

#define BPROT_CONFIG3_REGION106_Msk   (0x1UL << BPROT_CONFIG3_REGION106_Pos)

Bit mask of REGION106 field.

◆ BPROT_CONFIG3_REGION106_Pos

#define BPROT_CONFIG3_REGION106_Pos   (10UL)

Position of REGION106 field.

◆ BPROT_CONFIG3_REGION107_Disabled

#define BPROT_CONFIG3_REGION107_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION107_Enabled

#define BPROT_CONFIG3_REGION107_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION107_Msk

#define BPROT_CONFIG3_REGION107_Msk   (0x1UL << BPROT_CONFIG3_REGION107_Pos)

Bit mask of REGION107 field.

◆ BPROT_CONFIG3_REGION107_Pos

#define BPROT_CONFIG3_REGION107_Pos   (11UL)

Position of REGION107 field.

◆ BPROT_CONFIG3_REGION108_Disabled

#define BPROT_CONFIG3_REGION108_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION108_Enabled

#define BPROT_CONFIG3_REGION108_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION108_Msk

#define BPROT_CONFIG3_REGION108_Msk   (0x1UL << BPROT_CONFIG3_REGION108_Pos)

Bit mask of REGION108 field.

◆ BPROT_CONFIG3_REGION108_Pos

#define BPROT_CONFIG3_REGION108_Pos   (12UL)

Position of REGION108 field.

◆ BPROT_CONFIG3_REGION109_Disabled

#define BPROT_CONFIG3_REGION109_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION109_Enabled

#define BPROT_CONFIG3_REGION109_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION109_Msk

#define BPROT_CONFIG3_REGION109_Msk   (0x1UL << BPROT_CONFIG3_REGION109_Pos)

Bit mask of REGION109 field.

◆ BPROT_CONFIG3_REGION109_Pos

#define BPROT_CONFIG3_REGION109_Pos   (13UL)

Position of REGION109 field.

◆ BPROT_CONFIG3_REGION110_Disabled

#define BPROT_CONFIG3_REGION110_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION110_Enabled

#define BPROT_CONFIG3_REGION110_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION110_Msk

#define BPROT_CONFIG3_REGION110_Msk   (0x1UL << BPROT_CONFIG3_REGION110_Pos)

Bit mask of REGION110 field.

◆ BPROT_CONFIG3_REGION110_Pos

#define BPROT_CONFIG3_REGION110_Pos   (14UL)

Position of REGION110 field.

◆ BPROT_CONFIG3_REGION111_Disabled

#define BPROT_CONFIG3_REGION111_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION111_Enabled

#define BPROT_CONFIG3_REGION111_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION111_Msk

#define BPROT_CONFIG3_REGION111_Msk   (0x1UL << BPROT_CONFIG3_REGION111_Pos)

Bit mask of REGION111 field.

◆ BPROT_CONFIG3_REGION111_Pos

#define BPROT_CONFIG3_REGION111_Pos   (15UL)

Position of REGION111 field.

◆ BPROT_CONFIG3_REGION112_Disabled

#define BPROT_CONFIG3_REGION112_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION112_Enabled

#define BPROT_CONFIG3_REGION112_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION112_Msk

#define BPROT_CONFIG3_REGION112_Msk   (0x1UL << BPROT_CONFIG3_REGION112_Pos)

Bit mask of REGION112 field.

◆ BPROT_CONFIG3_REGION112_Pos

#define BPROT_CONFIG3_REGION112_Pos   (16UL)

Position of REGION112 field.

◆ BPROT_CONFIG3_REGION113_Disabled

#define BPROT_CONFIG3_REGION113_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION113_Enabled

#define BPROT_CONFIG3_REGION113_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION113_Msk

#define BPROT_CONFIG3_REGION113_Msk   (0x1UL << BPROT_CONFIG3_REGION113_Pos)

Bit mask of REGION113 field.

◆ BPROT_CONFIG3_REGION113_Pos

#define BPROT_CONFIG3_REGION113_Pos   (17UL)

Position of REGION113 field.

◆ BPROT_CONFIG3_REGION114_Disabled

#define BPROT_CONFIG3_REGION114_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION114_Enabled

#define BPROT_CONFIG3_REGION114_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION114_Msk

#define BPROT_CONFIG3_REGION114_Msk   (0x1UL << BPROT_CONFIG3_REGION114_Pos)

Bit mask of REGION114 field.

◆ BPROT_CONFIG3_REGION114_Pos

#define BPROT_CONFIG3_REGION114_Pos   (18UL)

Position of REGION114 field.

◆ BPROT_CONFIG3_REGION115_Disabled

#define BPROT_CONFIG3_REGION115_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION115_Enabled

#define BPROT_CONFIG3_REGION115_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION115_Msk

#define BPROT_CONFIG3_REGION115_Msk   (0x1UL << BPROT_CONFIG3_REGION115_Pos)

Bit mask of REGION115 field.

◆ BPROT_CONFIG3_REGION115_Pos

#define BPROT_CONFIG3_REGION115_Pos   (19UL)

Position of REGION115 field.

◆ BPROT_CONFIG3_REGION116_Disabled

#define BPROT_CONFIG3_REGION116_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION116_Enabled

#define BPROT_CONFIG3_REGION116_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION116_Msk

#define BPROT_CONFIG3_REGION116_Msk   (0x1UL << BPROT_CONFIG3_REGION116_Pos)

Bit mask of REGION116 field.

◆ BPROT_CONFIG3_REGION116_Pos

#define BPROT_CONFIG3_REGION116_Pos   (20UL)

Position of REGION116 field.

◆ BPROT_CONFIG3_REGION117_Disabled

#define BPROT_CONFIG3_REGION117_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION117_Enabled

#define BPROT_CONFIG3_REGION117_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION117_Msk

#define BPROT_CONFIG3_REGION117_Msk   (0x1UL << BPROT_CONFIG3_REGION117_Pos)

Bit mask of REGION117 field.

◆ BPROT_CONFIG3_REGION117_Pos

#define BPROT_CONFIG3_REGION117_Pos   (21UL)

Position of REGION117 field.

◆ BPROT_CONFIG3_REGION118_Disabled

#define BPROT_CONFIG3_REGION118_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION118_Enabled

#define BPROT_CONFIG3_REGION118_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION118_Msk

#define BPROT_CONFIG3_REGION118_Msk   (0x1UL << BPROT_CONFIG3_REGION118_Pos)

Bit mask of REGION118 field.

◆ BPROT_CONFIG3_REGION118_Pos

#define BPROT_CONFIG3_REGION118_Pos   (22UL)

Position of REGION118 field.

◆ BPROT_CONFIG3_REGION119_Disabled

#define BPROT_CONFIG3_REGION119_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION119_Enabled

#define BPROT_CONFIG3_REGION119_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION119_Msk

#define BPROT_CONFIG3_REGION119_Msk   (0x1UL << BPROT_CONFIG3_REGION119_Pos)

Bit mask of REGION119 field.

◆ BPROT_CONFIG3_REGION119_Pos

#define BPROT_CONFIG3_REGION119_Pos   (23UL)

Position of REGION119 field.

◆ BPROT_CONFIG3_REGION120_Disabled

#define BPROT_CONFIG3_REGION120_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION120_Enabled

#define BPROT_CONFIG3_REGION120_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION120_Msk

#define BPROT_CONFIG3_REGION120_Msk   (0x1UL << BPROT_CONFIG3_REGION120_Pos)

Bit mask of REGION120 field.

◆ BPROT_CONFIG3_REGION120_Pos

#define BPROT_CONFIG3_REGION120_Pos   (24UL)

Position of REGION120 field.

◆ BPROT_CONFIG3_REGION121_Disabled

#define BPROT_CONFIG3_REGION121_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION121_Enabled

#define BPROT_CONFIG3_REGION121_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION121_Msk

#define BPROT_CONFIG3_REGION121_Msk   (0x1UL << BPROT_CONFIG3_REGION121_Pos)

Bit mask of REGION121 field.

◆ BPROT_CONFIG3_REGION121_Pos

#define BPROT_CONFIG3_REGION121_Pos   (25UL)

Position of REGION121 field.

◆ BPROT_CONFIG3_REGION122_Disabled

#define BPROT_CONFIG3_REGION122_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION122_Enabled

#define BPROT_CONFIG3_REGION122_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION122_Msk

#define BPROT_CONFIG3_REGION122_Msk   (0x1UL << BPROT_CONFIG3_REGION122_Pos)

Bit mask of REGION122 field.

◆ BPROT_CONFIG3_REGION122_Pos

#define BPROT_CONFIG3_REGION122_Pos   (26UL)

Position of REGION122 field.

◆ BPROT_CONFIG3_REGION123_Disabled

#define BPROT_CONFIG3_REGION123_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION123_Enabled

#define BPROT_CONFIG3_REGION123_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION123_Msk

#define BPROT_CONFIG3_REGION123_Msk   (0x1UL << BPROT_CONFIG3_REGION123_Pos)

Bit mask of REGION123 field.

◆ BPROT_CONFIG3_REGION123_Pos

#define BPROT_CONFIG3_REGION123_Pos   (27UL)

Position of REGION123 field.

◆ BPROT_CONFIG3_REGION124_Disabled

#define BPROT_CONFIG3_REGION124_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION124_Enabled

#define BPROT_CONFIG3_REGION124_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION124_Msk

#define BPROT_CONFIG3_REGION124_Msk   (0x1UL << BPROT_CONFIG3_REGION124_Pos)

Bit mask of REGION124 field.

◆ BPROT_CONFIG3_REGION124_Pos

#define BPROT_CONFIG3_REGION124_Pos   (28UL)

Position of REGION124 field.

◆ BPROT_CONFIG3_REGION125_Disabled

#define BPROT_CONFIG3_REGION125_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION125_Enabled

#define BPROT_CONFIG3_REGION125_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION125_Msk

#define BPROT_CONFIG3_REGION125_Msk   (0x1UL << BPROT_CONFIG3_REGION125_Pos)

Bit mask of REGION125 field.

◆ BPROT_CONFIG3_REGION125_Pos

#define BPROT_CONFIG3_REGION125_Pos   (29UL)

Position of REGION125 field.

◆ BPROT_CONFIG3_REGION126_Disabled

#define BPROT_CONFIG3_REGION126_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION126_Enabled

#define BPROT_CONFIG3_REGION126_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION126_Msk

#define BPROT_CONFIG3_REGION126_Msk   (0x1UL << BPROT_CONFIG3_REGION126_Pos)

Bit mask of REGION126 field.

◆ BPROT_CONFIG3_REGION126_Pos

#define BPROT_CONFIG3_REGION126_Pos   (30UL)

Position of REGION126 field.

◆ BPROT_CONFIG3_REGION127_Disabled

#define BPROT_CONFIG3_REGION127_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION127_Enabled

#define BPROT_CONFIG3_REGION127_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION127_Msk

#define BPROT_CONFIG3_REGION127_Msk   (0x1UL << BPROT_CONFIG3_REGION127_Pos)

Bit mask of REGION127 field.

◆ BPROT_CONFIG3_REGION127_Pos

#define BPROT_CONFIG3_REGION127_Pos   (31UL)

Position of REGION127 field.

◆ BPROT_CONFIG3_REGION96_Disabled

#define BPROT_CONFIG3_REGION96_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION96_Enabled

#define BPROT_CONFIG3_REGION96_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION96_Msk

#define BPROT_CONFIG3_REGION96_Msk   (0x1UL << BPROT_CONFIG3_REGION96_Pos)

Bit mask of REGION96 field.

◆ BPROT_CONFIG3_REGION96_Pos

#define BPROT_CONFIG3_REGION96_Pos   (0UL)

Position of REGION96 field.

◆ BPROT_CONFIG3_REGION97_Disabled

#define BPROT_CONFIG3_REGION97_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION97_Enabled

#define BPROT_CONFIG3_REGION97_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION97_Msk

#define BPROT_CONFIG3_REGION97_Msk   (0x1UL << BPROT_CONFIG3_REGION97_Pos)

Bit mask of REGION97 field.

◆ BPROT_CONFIG3_REGION97_Pos

#define BPROT_CONFIG3_REGION97_Pos   (1UL)

Position of REGION97 field.

◆ BPROT_CONFIG3_REGION98_Disabled

#define BPROT_CONFIG3_REGION98_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION98_Enabled

#define BPROT_CONFIG3_REGION98_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION98_Msk

#define BPROT_CONFIG3_REGION98_Msk   (0x1UL << BPROT_CONFIG3_REGION98_Pos)

Bit mask of REGION98 field.

◆ BPROT_CONFIG3_REGION98_Pos

#define BPROT_CONFIG3_REGION98_Pos   (2UL)

Position of REGION98 field.

◆ BPROT_CONFIG3_REGION99_Disabled

#define BPROT_CONFIG3_REGION99_Disabled   (0UL)

Protection disabled

◆ BPROT_CONFIG3_REGION99_Enabled

#define BPROT_CONFIG3_REGION99_Enabled   (1UL)

Protection enabled

◆ BPROT_CONFIG3_REGION99_Msk

#define BPROT_CONFIG3_REGION99_Msk   (0x1UL << BPROT_CONFIG3_REGION99_Pos)

Bit mask of REGION99 field.

◆ BPROT_CONFIG3_REGION99_Pos

#define BPROT_CONFIG3_REGION99_Pos   (3UL)

Position of REGION99 field.

◆ BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled

#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled   (1UL)

Disable in debug

◆ BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled

#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled   (0UL)

Enable in debug

◆ BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk

#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk   (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos)

Bit mask of DISABLEINDEBUG field.

◆ BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos

#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos   (0UL)

Position of DISABLEINDEBUG field.

◆ CCM_CNFPTR_CNFPTR_Msk

#define CCM_CNFPTR_CNFPTR_Msk   (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos)

Bit mask of CNFPTR field.

◆ CCM_CNFPTR_CNFPTR_Pos

#define CCM_CNFPTR_CNFPTR_Pos   (0UL)

Position of CNFPTR field.

◆ CCM_ENABLE_ENABLE_Disabled

#define CCM_ENABLE_ENABLE_Disabled   (0UL)

Disable

◆ CCM_ENABLE_ENABLE_Enabled

#define CCM_ENABLE_ENABLE_Enabled   (2UL)

Enable

◆ CCM_ENABLE_ENABLE_Msk

#define CCM_ENABLE_ENABLE_Msk   (0x3UL << CCM_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ CCM_ENABLE_ENABLE_Pos

#define CCM_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ CCM_INPTR_INPTR_Msk

#define CCM_INPTR_INPTR_Msk   (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos)

Bit mask of INPTR field.

◆ CCM_INPTR_INPTR_Pos

#define CCM_INPTR_INPTR_Pos   (0UL)

Position of INPTR field.

◆ CCM_INTENCLR_ENDCRYPT_Clear

#define CCM_INTENCLR_ENDCRYPT_Clear   (1UL)

Disable

◆ CCM_INTENCLR_ENDCRYPT_Disabled

#define CCM_INTENCLR_ENDCRYPT_Disabled   (0UL)

Read: Disabled

◆ CCM_INTENCLR_ENDCRYPT_Enabled

#define CCM_INTENCLR_ENDCRYPT_Enabled   (1UL)

Read: Enabled

◆ CCM_INTENCLR_ENDCRYPT_Msk

#define CCM_INTENCLR_ENDCRYPT_Msk   (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos)

Bit mask of ENDCRYPT field.

◆ CCM_INTENCLR_ENDCRYPT_Pos

#define CCM_INTENCLR_ENDCRYPT_Pos   (1UL)

Position of ENDCRYPT field.

◆ CCM_INTENCLR_ENDKSGEN_Clear

#define CCM_INTENCLR_ENDKSGEN_Clear   (1UL)

Disable

◆ CCM_INTENCLR_ENDKSGEN_Disabled

#define CCM_INTENCLR_ENDKSGEN_Disabled   (0UL)

Read: Disabled

◆ CCM_INTENCLR_ENDKSGEN_Enabled

#define CCM_INTENCLR_ENDKSGEN_Enabled   (1UL)

Read: Enabled

◆ CCM_INTENCLR_ENDKSGEN_Msk

#define CCM_INTENCLR_ENDKSGEN_Msk   (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos)

Bit mask of ENDKSGEN field.

◆ CCM_INTENCLR_ENDKSGEN_Pos

#define CCM_INTENCLR_ENDKSGEN_Pos   (0UL)

Position of ENDKSGEN field.

◆ CCM_INTENCLR_ERROR_Clear

#define CCM_INTENCLR_ERROR_Clear   (1UL)

Disable

◆ CCM_INTENCLR_ERROR_Disabled

#define CCM_INTENCLR_ERROR_Disabled   (0UL)

Read: Disabled

◆ CCM_INTENCLR_ERROR_Enabled

#define CCM_INTENCLR_ERROR_Enabled   (1UL)

Read: Enabled

◆ CCM_INTENCLR_ERROR_Msk

#define CCM_INTENCLR_ERROR_Msk   (0x1UL << CCM_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

◆ CCM_INTENCLR_ERROR_Pos

#define CCM_INTENCLR_ERROR_Pos   (2UL)

Position of ERROR field.

◆ CCM_INTENSET_ENDCRYPT_Disabled

#define CCM_INTENSET_ENDCRYPT_Disabled   (0UL)

Read: Disabled

◆ CCM_INTENSET_ENDCRYPT_Enabled

#define CCM_INTENSET_ENDCRYPT_Enabled   (1UL)

Read: Enabled

◆ CCM_INTENSET_ENDCRYPT_Msk

#define CCM_INTENSET_ENDCRYPT_Msk   (0x1UL << CCM_INTENSET_ENDCRYPT_Pos)

Bit mask of ENDCRYPT field.

◆ CCM_INTENSET_ENDCRYPT_Pos

#define CCM_INTENSET_ENDCRYPT_Pos   (1UL)

Position of ENDCRYPT field.

◆ CCM_INTENSET_ENDCRYPT_Set

#define CCM_INTENSET_ENDCRYPT_Set   (1UL)

Enable

◆ CCM_INTENSET_ENDKSGEN_Disabled

#define CCM_INTENSET_ENDKSGEN_Disabled   (0UL)

Read: Disabled

◆ CCM_INTENSET_ENDKSGEN_Enabled

#define CCM_INTENSET_ENDKSGEN_Enabled   (1UL)

Read: Enabled

◆ CCM_INTENSET_ENDKSGEN_Msk

#define CCM_INTENSET_ENDKSGEN_Msk   (0x1UL << CCM_INTENSET_ENDKSGEN_Pos)

Bit mask of ENDKSGEN field.

◆ CCM_INTENSET_ENDKSGEN_Pos

#define CCM_INTENSET_ENDKSGEN_Pos   (0UL)

Position of ENDKSGEN field.

◆ CCM_INTENSET_ENDKSGEN_Set

#define CCM_INTENSET_ENDKSGEN_Set   (1UL)

Enable

◆ CCM_INTENSET_ERROR_Disabled

#define CCM_INTENSET_ERROR_Disabled   (0UL)

Read: Disabled

◆ CCM_INTENSET_ERROR_Enabled

#define CCM_INTENSET_ERROR_Enabled   (1UL)

Read: Enabled

◆ CCM_INTENSET_ERROR_Msk

#define CCM_INTENSET_ERROR_Msk   (0x1UL << CCM_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

◆ CCM_INTENSET_ERROR_Pos

#define CCM_INTENSET_ERROR_Pos   (2UL)

Position of ERROR field.

◆ CCM_INTENSET_ERROR_Set

#define CCM_INTENSET_ERROR_Set   (1UL)

Enable

◆ CCM_MICSTATUS_MICSTATUS_CheckFailed

#define CCM_MICSTATUS_MICSTATUS_CheckFailed   (0UL)

MIC check failed

◆ CCM_MICSTATUS_MICSTATUS_CheckPassed

#define CCM_MICSTATUS_MICSTATUS_CheckPassed   (1UL)

MIC check passed

◆ CCM_MICSTATUS_MICSTATUS_Msk

#define CCM_MICSTATUS_MICSTATUS_Msk   (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos)

Bit mask of MICSTATUS field.

◆ CCM_MICSTATUS_MICSTATUS_Pos

#define CCM_MICSTATUS_MICSTATUS_Pos   (0UL)

Position of MICSTATUS field.

◆ CCM_MODE_DATARATE_1Mbit

#define CCM_MODE_DATARATE_1Mbit   (0UL)

In synch with 1 Mbit data rate

◆ CCM_MODE_DATARATE_2Mbit

#define CCM_MODE_DATARATE_2Mbit   (1UL)

In synch with 2 Mbit data rate

◆ CCM_MODE_DATARATE_Msk

#define CCM_MODE_DATARATE_Msk   (0x1UL << CCM_MODE_DATARATE_Pos)

Bit mask of DATARATE field.

◆ CCM_MODE_DATARATE_Pos

#define CCM_MODE_DATARATE_Pos   (16UL)

Position of DATARATE field.

◆ CCM_MODE_LENGTH_Default

#define CCM_MODE_LENGTH_Default   (0UL)

Default length. Effective length of LENGTH field is 5-bit

◆ CCM_MODE_LENGTH_Extended

#define CCM_MODE_LENGTH_Extended   (1UL)

Extended length. Effective length of LENGTH field is 8-bit

◆ CCM_MODE_LENGTH_Msk

#define CCM_MODE_LENGTH_Msk   (0x1UL << CCM_MODE_LENGTH_Pos)

Bit mask of LENGTH field.

◆ CCM_MODE_LENGTH_Pos

#define CCM_MODE_LENGTH_Pos   (24UL)

Position of LENGTH field.

◆ CCM_MODE_MODE_Decryption

#define CCM_MODE_MODE_Decryption   (1UL)

AES CCM packet decryption mode

◆ CCM_MODE_MODE_Encryption

#define CCM_MODE_MODE_Encryption   (0UL)

AES CCM packet encryption mode

◆ CCM_MODE_MODE_Msk

#define CCM_MODE_MODE_Msk   (0x1UL << CCM_MODE_MODE_Pos)

Bit mask of MODE field.

◆ CCM_MODE_MODE_Pos

#define CCM_MODE_MODE_Pos   (0UL)

Position of MODE field.

◆ CCM_OUTPTR_OUTPTR_Msk

#define CCM_OUTPTR_OUTPTR_Msk   (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos)

Bit mask of OUTPTR field.

◆ CCM_OUTPTR_OUTPTR_Pos

#define CCM_OUTPTR_OUTPTR_Pos   (0UL)

Position of OUTPTR field.

◆ CCM_SCRATCHPTR_SCRATCHPTR_Msk

#define CCM_SCRATCHPTR_SCRATCHPTR_Msk   (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos)

Bit mask of SCRATCHPTR field.

◆ CCM_SCRATCHPTR_SCRATCHPTR_Pos

#define CCM_SCRATCHPTR_SCRATCHPTR_Pos   (0UL)

Position of SCRATCHPTR field.

◆ CCM_SHORTS_ENDKSGEN_CRYPT_Disabled

#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled   (0UL)

Disable shortcut

◆ CCM_SHORTS_ENDKSGEN_CRYPT_Enabled

#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled   (1UL)

Enable shortcut

◆ CCM_SHORTS_ENDKSGEN_CRYPT_Msk

#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk   (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos)

Bit mask of ENDKSGEN_CRYPT field.

◆ CCM_SHORTS_ENDKSGEN_CRYPT_Pos

#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos   (0UL)

Position of ENDKSGEN_CRYPT field.

◆ CLOCK_CTIV_CTIV_Msk

#define CLOCK_CTIV_CTIV_Msk   (0x7FUL << CLOCK_CTIV_CTIV_Pos)

Bit mask of CTIV field.

◆ CLOCK_CTIV_CTIV_Pos

#define CLOCK_CTIV_CTIV_Pos   (0UL)

Position of CTIV field.

◆ CLOCK_HFCLKRUN_STATUS_Msk

#define CLOCK_HFCLKRUN_STATUS_Msk   (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos)

Bit mask of STATUS field.

◆ CLOCK_HFCLKRUN_STATUS_NotTriggered

#define CLOCK_HFCLKRUN_STATUS_NotTriggered   (0UL)

Task not triggered

◆ CLOCK_HFCLKRUN_STATUS_Pos

#define CLOCK_HFCLKRUN_STATUS_Pos   (0UL)

Position of STATUS field.

◆ CLOCK_HFCLKRUN_STATUS_Triggered

#define CLOCK_HFCLKRUN_STATUS_Triggered   (1UL)

Task triggered

◆ CLOCK_HFCLKSTAT_SRC_Msk

#define CLOCK_HFCLKSTAT_SRC_Msk   (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos)

Bit mask of SRC field.

◆ CLOCK_HFCLKSTAT_SRC_Pos

#define CLOCK_HFCLKSTAT_SRC_Pos   (0UL)

Position of SRC field.

◆ CLOCK_HFCLKSTAT_SRC_RC

#define CLOCK_HFCLKSTAT_SRC_RC   (0UL)

64 MHz internal oscillator (HFINT)

◆ CLOCK_HFCLKSTAT_SRC_Xtal

#define CLOCK_HFCLKSTAT_SRC_Xtal   (1UL)

64 MHz crystal oscillator (HFXO)

◆ CLOCK_HFCLKSTAT_STATE_Msk

#define CLOCK_HFCLKSTAT_STATE_Msk   (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos)

Bit mask of STATE field.

◆ CLOCK_HFCLKSTAT_STATE_NotRunning

#define CLOCK_HFCLKSTAT_STATE_NotRunning   (0UL)

HFCLK not running

◆ CLOCK_HFCLKSTAT_STATE_Pos

#define CLOCK_HFCLKSTAT_STATE_Pos   (16UL)

Position of STATE field.

◆ CLOCK_HFCLKSTAT_STATE_Running

#define CLOCK_HFCLKSTAT_STATE_Running   (1UL)

HFCLK running

◆ CLOCK_INTENCLR_CTTO_Clear

#define CLOCK_INTENCLR_CTTO_Clear   (1UL)

Disable

◆ CLOCK_INTENCLR_CTTO_Disabled

#define CLOCK_INTENCLR_CTTO_Disabled   (0UL)

Read: Disabled

◆ CLOCK_INTENCLR_CTTO_Enabled

#define CLOCK_INTENCLR_CTTO_Enabled   (1UL)

Read: Enabled

◆ CLOCK_INTENCLR_CTTO_Msk

#define CLOCK_INTENCLR_CTTO_Msk   (0x1UL << CLOCK_INTENCLR_CTTO_Pos)

Bit mask of CTTO field.

◆ CLOCK_INTENCLR_CTTO_Pos

#define CLOCK_INTENCLR_CTTO_Pos   (4UL)

Position of CTTO field.

◆ CLOCK_INTENCLR_DONE_Clear

#define CLOCK_INTENCLR_DONE_Clear   (1UL)

Disable

◆ CLOCK_INTENCLR_DONE_Disabled

#define CLOCK_INTENCLR_DONE_Disabled   (0UL)

Read: Disabled

◆ CLOCK_INTENCLR_DONE_Enabled

#define CLOCK_INTENCLR_DONE_Enabled   (1UL)

Read: Enabled

◆ CLOCK_INTENCLR_DONE_Msk

#define CLOCK_INTENCLR_DONE_Msk   (0x1UL << CLOCK_INTENCLR_DONE_Pos)

Bit mask of DONE field.

◆ CLOCK_INTENCLR_DONE_Pos

#define CLOCK_INTENCLR_DONE_Pos   (3UL)

Position of DONE field.

◆ CLOCK_INTENCLR_HFCLKSTARTED_Clear

#define CLOCK_INTENCLR_HFCLKSTARTED_Clear   (1UL)

Disable

◆ CLOCK_INTENCLR_HFCLKSTARTED_Disabled

#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled   (0UL)

Read: Disabled

◆ CLOCK_INTENCLR_HFCLKSTARTED_Enabled

#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled   (1UL)

Read: Enabled

◆ CLOCK_INTENCLR_HFCLKSTARTED_Msk

#define CLOCK_INTENCLR_HFCLKSTARTED_Msk   (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos)

Bit mask of HFCLKSTARTED field.

◆ CLOCK_INTENCLR_HFCLKSTARTED_Pos

#define CLOCK_INTENCLR_HFCLKSTARTED_Pos   (0UL)

Position of HFCLKSTARTED field.

◆ CLOCK_INTENCLR_LFCLKSTARTED_Clear

#define CLOCK_INTENCLR_LFCLKSTARTED_Clear   (1UL)

Disable

◆ CLOCK_INTENCLR_LFCLKSTARTED_Disabled

#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled   (0UL)

Read: Disabled

◆ CLOCK_INTENCLR_LFCLKSTARTED_Enabled

#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled   (1UL)

Read: Enabled

◆ CLOCK_INTENCLR_LFCLKSTARTED_Msk

#define CLOCK_INTENCLR_LFCLKSTARTED_Msk   (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos)

Bit mask of LFCLKSTARTED field.

◆ CLOCK_INTENCLR_LFCLKSTARTED_Pos

#define CLOCK_INTENCLR_LFCLKSTARTED_Pos   (1UL)

Position of LFCLKSTARTED field.

◆ CLOCK_INTENSET_CTTO_Disabled

#define CLOCK_INTENSET_CTTO_Disabled   (0UL)

Read: Disabled

◆ CLOCK_INTENSET_CTTO_Enabled

#define CLOCK_INTENSET_CTTO_Enabled   (1UL)

Read: Enabled

◆ CLOCK_INTENSET_CTTO_Msk

#define CLOCK_INTENSET_CTTO_Msk   (0x1UL << CLOCK_INTENSET_CTTO_Pos)

Bit mask of CTTO field.

◆ CLOCK_INTENSET_CTTO_Pos

#define CLOCK_INTENSET_CTTO_Pos   (4UL)

Position of CTTO field.

◆ CLOCK_INTENSET_CTTO_Set

#define CLOCK_INTENSET_CTTO_Set   (1UL)

Enable

◆ CLOCK_INTENSET_DONE_Disabled

#define CLOCK_INTENSET_DONE_Disabled   (0UL)

Read: Disabled

◆ CLOCK_INTENSET_DONE_Enabled

#define CLOCK_INTENSET_DONE_Enabled   (1UL)

Read: Enabled

◆ CLOCK_INTENSET_DONE_Msk

#define CLOCK_INTENSET_DONE_Msk   (0x1UL << CLOCK_INTENSET_DONE_Pos)

Bit mask of DONE field.

◆ CLOCK_INTENSET_DONE_Pos

#define CLOCK_INTENSET_DONE_Pos   (3UL)

Position of DONE field.

◆ CLOCK_INTENSET_DONE_Set

#define CLOCK_INTENSET_DONE_Set   (1UL)

Enable

◆ CLOCK_INTENSET_HFCLKSTARTED_Disabled

#define CLOCK_INTENSET_HFCLKSTARTED_Disabled   (0UL)

Read: Disabled

◆ CLOCK_INTENSET_HFCLKSTARTED_Enabled

#define CLOCK_INTENSET_HFCLKSTARTED_Enabled   (1UL)

Read: Enabled

◆ CLOCK_INTENSET_HFCLKSTARTED_Msk

#define CLOCK_INTENSET_HFCLKSTARTED_Msk   (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos)

Bit mask of HFCLKSTARTED field.

◆ CLOCK_INTENSET_HFCLKSTARTED_Pos

#define CLOCK_INTENSET_HFCLKSTARTED_Pos   (0UL)

Position of HFCLKSTARTED field.

◆ CLOCK_INTENSET_HFCLKSTARTED_Set

#define CLOCK_INTENSET_HFCLKSTARTED_Set   (1UL)

Enable

◆ CLOCK_INTENSET_LFCLKSTARTED_Disabled

#define CLOCK_INTENSET_LFCLKSTARTED_Disabled   (0UL)

Read: Disabled

◆ CLOCK_INTENSET_LFCLKSTARTED_Enabled

#define CLOCK_INTENSET_LFCLKSTARTED_Enabled   (1UL)

Read: Enabled

◆ CLOCK_INTENSET_LFCLKSTARTED_Msk

#define CLOCK_INTENSET_LFCLKSTARTED_Msk   (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos)

Bit mask of LFCLKSTARTED field.

◆ CLOCK_INTENSET_LFCLKSTARTED_Pos

#define CLOCK_INTENSET_LFCLKSTARTED_Pos   (1UL)

Position of LFCLKSTARTED field.

◆ CLOCK_INTENSET_LFCLKSTARTED_Set

#define CLOCK_INTENSET_LFCLKSTARTED_Set   (1UL)

Enable

◆ CLOCK_LFCLKRUN_STATUS_Msk

#define CLOCK_LFCLKRUN_STATUS_Msk   (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos)

Bit mask of STATUS field.

◆ CLOCK_LFCLKRUN_STATUS_NotTriggered

#define CLOCK_LFCLKRUN_STATUS_NotTriggered   (0UL)

Task not triggered

◆ CLOCK_LFCLKRUN_STATUS_Pos

#define CLOCK_LFCLKRUN_STATUS_Pos   (0UL)

Position of STATUS field.

◆ CLOCK_LFCLKRUN_STATUS_Triggered

#define CLOCK_LFCLKRUN_STATUS_Triggered   (1UL)

Task triggered

◆ CLOCK_LFCLKSRC_BYPASS_Disabled

#define CLOCK_LFCLKSRC_BYPASS_Disabled   (0UL)

Disable (use with Xtal or low-swing external source)

◆ CLOCK_LFCLKSRC_BYPASS_Enabled

#define CLOCK_LFCLKSRC_BYPASS_Enabled   (1UL)

Enable (use with rail-to-rail external source)

◆ CLOCK_LFCLKSRC_BYPASS_Msk

#define CLOCK_LFCLKSRC_BYPASS_Msk   (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos)

Bit mask of BYPASS field.

◆ CLOCK_LFCLKSRC_BYPASS_Pos

#define CLOCK_LFCLKSRC_BYPASS_Pos   (16UL)

Position of BYPASS field.

◆ CLOCK_LFCLKSRC_EXTERNAL_Disabled

#define CLOCK_LFCLKSRC_EXTERNAL_Disabled   (0UL)

Disable external source (use with Xtal)

◆ CLOCK_LFCLKSRC_EXTERNAL_Enabled

#define CLOCK_LFCLKSRC_EXTERNAL_Enabled   (1UL)

Enable use of external source instead of Xtal (SRC needs to be set to Xtal)

◆ CLOCK_LFCLKSRC_EXTERNAL_Msk

#define CLOCK_LFCLKSRC_EXTERNAL_Msk   (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos)

Bit mask of EXTERNAL field.

◆ CLOCK_LFCLKSRC_EXTERNAL_Pos

#define CLOCK_LFCLKSRC_EXTERNAL_Pos   (17UL)

Position of EXTERNAL field.

◆ CLOCK_LFCLKSRC_SRC_Msk

#define CLOCK_LFCLKSRC_SRC_Msk   (0x3UL << CLOCK_LFCLKSRC_SRC_Pos)

Bit mask of SRC field.

◆ CLOCK_LFCLKSRC_SRC_Pos

#define CLOCK_LFCLKSRC_SRC_Pos   (0UL)

Position of SRC field.

◆ CLOCK_LFCLKSRC_SRC_RC

#define CLOCK_LFCLKSRC_SRC_RC   (0UL)

32.768 kHz RC oscillator

◆ CLOCK_LFCLKSRC_SRC_Synth

#define CLOCK_LFCLKSRC_SRC_Synth   (2UL)

32.768 kHz synthesized from HFCLK

◆ CLOCK_LFCLKSRC_SRC_Xtal

#define CLOCK_LFCLKSRC_SRC_Xtal   (1UL)

32.768 kHz crystal oscillator

◆ CLOCK_LFCLKSRCCOPY_SRC_Msk

#define CLOCK_LFCLKSRCCOPY_SRC_Msk   (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos)

Bit mask of SRC field.

◆ CLOCK_LFCLKSRCCOPY_SRC_Pos

#define CLOCK_LFCLKSRCCOPY_SRC_Pos   (0UL)

Position of SRC field.

◆ CLOCK_LFCLKSRCCOPY_SRC_RC

#define CLOCK_LFCLKSRCCOPY_SRC_RC   (0UL)

32.768 kHz RC oscillator

◆ CLOCK_LFCLKSRCCOPY_SRC_Synth

#define CLOCK_LFCLKSRCCOPY_SRC_Synth   (2UL)

32.768 kHz synthesized from HFCLK

◆ CLOCK_LFCLKSRCCOPY_SRC_Xtal

#define CLOCK_LFCLKSRCCOPY_SRC_Xtal   (1UL)

32.768 kHz crystal oscillator

◆ CLOCK_LFCLKSTAT_SRC_Msk

#define CLOCK_LFCLKSTAT_SRC_Msk   (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos)

Bit mask of SRC field.

◆ CLOCK_LFCLKSTAT_SRC_Pos

#define CLOCK_LFCLKSTAT_SRC_Pos   (0UL)

Position of SRC field.

◆ CLOCK_LFCLKSTAT_SRC_RC

#define CLOCK_LFCLKSTAT_SRC_RC   (0UL)

32.768 kHz RC oscillator

◆ CLOCK_LFCLKSTAT_SRC_Synth

#define CLOCK_LFCLKSTAT_SRC_Synth   (2UL)

32.768 kHz synthesized from HFCLK

◆ CLOCK_LFCLKSTAT_SRC_Xtal

#define CLOCK_LFCLKSTAT_SRC_Xtal   (1UL)

32.768 kHz crystal oscillator

◆ CLOCK_LFCLKSTAT_STATE_Msk

#define CLOCK_LFCLKSTAT_STATE_Msk   (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos)

Bit mask of STATE field.

◆ CLOCK_LFCLKSTAT_STATE_NotRunning

#define CLOCK_LFCLKSTAT_STATE_NotRunning   (0UL)

LFCLK not running

◆ CLOCK_LFCLKSTAT_STATE_Pos

#define CLOCK_LFCLKSTAT_STATE_Pos   (16UL)

Position of STATE field.

◆ CLOCK_LFCLKSTAT_STATE_Running

#define CLOCK_LFCLKSTAT_STATE_Running   (1UL)

LFCLK running

◆ CLOCK_TRACECONFIG_TRACEMUX_GPIO

#define CLOCK_TRACECONFIG_TRACEMUX_GPIO   (0UL)

GPIOs multiplexed onto all trace-pins

◆ CLOCK_TRACECONFIG_TRACEMUX_Msk

#define CLOCK_TRACECONFIG_TRACEMUX_Msk   (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos)

Bit mask of TRACEMUX field.

◆ CLOCK_TRACECONFIG_TRACEMUX_Parallel

#define CLOCK_TRACECONFIG_TRACEMUX_Parallel   (2UL)

TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14.

◆ CLOCK_TRACECONFIG_TRACEMUX_Pos

#define CLOCK_TRACECONFIG_TRACEMUX_Pos   (16UL)

Position of TRACEMUX field.

◆ CLOCK_TRACECONFIG_TRACEMUX_Serial

#define CLOCK_TRACECONFIG_TRACEMUX_Serial   (1UL)

SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins

◆ CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz

#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz   (1UL)

16 MHz Trace Port clock (TRACECLK = 8 MHz)

◆ CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz

#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz   (0UL)

32 MHz Trace Port clock (TRACECLK = 16 MHz)

◆ CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz

#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz   (3UL)

4 MHz Trace Port clock (TRACECLK = 2 MHz)

◆ CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz

#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz   (2UL)

8 MHz Trace Port clock (TRACECLK = 4 MHz)

◆ CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk

#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk   (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos)

Bit mask of TRACEPORTSPEED field.

◆ CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos

#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos   (0UL)

Position of TRACEPORTSPEED field.

◆ COMP_ENABLE_ENABLE_Disabled

#define COMP_ENABLE_ENABLE_Disabled   (0UL)

Disable

◆ COMP_ENABLE_ENABLE_Enabled

#define COMP_ENABLE_ENABLE_Enabled   (2UL)

Enable

◆ COMP_ENABLE_ENABLE_Msk

#define COMP_ENABLE_ENABLE_Msk   (0x3UL << COMP_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ COMP_ENABLE_ENABLE_Pos

#define COMP_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ COMP_EXTREFSEL_EXTREFSEL_AnalogReference0

#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0   (0UL)

Use AIN0 as external analog reference

◆ COMP_EXTREFSEL_EXTREFSEL_AnalogReference1

#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1   (1UL)

Use AIN1 as external analog reference

◆ COMP_EXTREFSEL_EXTREFSEL_AnalogReference2

#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2   (2UL)

Use AIN2 as external analog reference

◆ COMP_EXTREFSEL_EXTREFSEL_AnalogReference3

#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3   (3UL)

Use AIN3 as external analog reference

◆ COMP_EXTREFSEL_EXTREFSEL_AnalogReference4

#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4   (4UL)

Use AIN4 as external analog reference

◆ COMP_EXTREFSEL_EXTREFSEL_AnalogReference5

#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5   (5UL)

Use AIN5 as external analog reference

◆ COMP_EXTREFSEL_EXTREFSEL_AnalogReference6

#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6   (6UL)

Use AIN6 as external analog reference

◆ COMP_EXTREFSEL_EXTREFSEL_AnalogReference7

#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7   (7UL)

Use AIN7 as external analog reference

◆ COMP_EXTREFSEL_EXTREFSEL_Msk

#define COMP_EXTREFSEL_EXTREFSEL_Msk   (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos)

Bit mask of EXTREFSEL field.

◆ COMP_EXTREFSEL_EXTREFSEL_Pos

#define COMP_EXTREFSEL_EXTREFSEL_Pos   (0UL)

Position of EXTREFSEL field.

◆ COMP_HYST_HYST_Hyst50mV

#define COMP_HYST_HYST_Hyst50mV   (1UL)

Comparator hysteresis enabled

◆ COMP_HYST_HYST_Msk

#define COMP_HYST_HYST_Msk   (0x1UL << COMP_HYST_HYST_Pos)

Bit mask of HYST field.

◆ COMP_HYST_HYST_NoHyst

#define COMP_HYST_HYST_NoHyst   (0UL)

Comparator hysteresis disabled

◆ COMP_HYST_HYST_Pos

#define COMP_HYST_HYST_Pos   (0UL)

Position of HYST field.

◆ COMP_INTEN_CROSS_Disabled

#define COMP_INTEN_CROSS_Disabled   (0UL)

Disable

◆ COMP_INTEN_CROSS_Enabled

#define COMP_INTEN_CROSS_Enabled   (1UL)

Enable

◆ COMP_INTEN_CROSS_Msk

#define COMP_INTEN_CROSS_Msk   (0x1UL << COMP_INTEN_CROSS_Pos)

Bit mask of CROSS field.

◆ COMP_INTEN_CROSS_Pos

#define COMP_INTEN_CROSS_Pos   (3UL)

Position of CROSS field.

◆ COMP_INTEN_DOWN_Disabled

#define COMP_INTEN_DOWN_Disabled   (0UL)

Disable

◆ COMP_INTEN_DOWN_Enabled

#define COMP_INTEN_DOWN_Enabled   (1UL)

Enable

◆ COMP_INTEN_DOWN_Msk

#define COMP_INTEN_DOWN_Msk   (0x1UL << COMP_INTEN_DOWN_Pos)

Bit mask of DOWN field.

◆ COMP_INTEN_DOWN_Pos

#define COMP_INTEN_DOWN_Pos   (1UL)

Position of DOWN field.

◆ COMP_INTEN_READY_Disabled

#define COMP_INTEN_READY_Disabled   (0UL)

Disable

◆ COMP_INTEN_READY_Enabled

#define COMP_INTEN_READY_Enabled   (1UL)

Enable

◆ COMP_INTEN_READY_Msk

#define COMP_INTEN_READY_Msk   (0x1UL << COMP_INTEN_READY_Pos)

Bit mask of READY field.

◆ COMP_INTEN_READY_Pos

#define COMP_INTEN_READY_Pos   (0UL)

Position of READY field.

◆ COMP_INTEN_UP_Disabled

#define COMP_INTEN_UP_Disabled   (0UL)

Disable

◆ COMP_INTEN_UP_Enabled

#define COMP_INTEN_UP_Enabled   (1UL)

Enable

◆ COMP_INTEN_UP_Msk

#define COMP_INTEN_UP_Msk   (0x1UL << COMP_INTEN_UP_Pos)

Bit mask of UP field.

◆ COMP_INTEN_UP_Pos

#define COMP_INTEN_UP_Pos   (2UL)

Position of UP field.

◆ COMP_INTENCLR_CROSS_Clear

#define COMP_INTENCLR_CROSS_Clear   (1UL)

Disable

◆ COMP_INTENCLR_CROSS_Disabled

#define COMP_INTENCLR_CROSS_Disabled   (0UL)

Read: Disabled

◆ COMP_INTENCLR_CROSS_Enabled

#define COMP_INTENCLR_CROSS_Enabled   (1UL)

Read: Enabled

◆ COMP_INTENCLR_CROSS_Msk

#define COMP_INTENCLR_CROSS_Msk   (0x1UL << COMP_INTENCLR_CROSS_Pos)

Bit mask of CROSS field.

◆ COMP_INTENCLR_CROSS_Pos

#define COMP_INTENCLR_CROSS_Pos   (3UL)

Position of CROSS field.

◆ COMP_INTENCLR_DOWN_Clear

#define COMP_INTENCLR_DOWN_Clear   (1UL)

Disable

◆ COMP_INTENCLR_DOWN_Disabled

#define COMP_INTENCLR_DOWN_Disabled   (0UL)

Read: Disabled

◆ COMP_INTENCLR_DOWN_Enabled

#define COMP_INTENCLR_DOWN_Enabled   (1UL)

Read: Enabled

◆ COMP_INTENCLR_DOWN_Msk

#define COMP_INTENCLR_DOWN_Msk   (0x1UL << COMP_INTENCLR_DOWN_Pos)

Bit mask of DOWN field.

◆ COMP_INTENCLR_DOWN_Pos

#define COMP_INTENCLR_DOWN_Pos   (1UL)

Position of DOWN field.

◆ COMP_INTENCLR_READY_Clear

#define COMP_INTENCLR_READY_Clear   (1UL)

Disable

◆ COMP_INTENCLR_READY_Disabled

#define COMP_INTENCLR_READY_Disabled   (0UL)

Read: Disabled

◆ COMP_INTENCLR_READY_Enabled

#define COMP_INTENCLR_READY_Enabled   (1UL)

Read: Enabled

◆ COMP_INTENCLR_READY_Msk

#define COMP_INTENCLR_READY_Msk   (0x1UL << COMP_INTENCLR_READY_Pos)

Bit mask of READY field.

◆ COMP_INTENCLR_READY_Pos

#define COMP_INTENCLR_READY_Pos   (0UL)

Position of READY field.

◆ COMP_INTENCLR_UP_Clear

#define COMP_INTENCLR_UP_Clear   (1UL)

Disable

◆ COMP_INTENCLR_UP_Disabled

#define COMP_INTENCLR_UP_Disabled   (0UL)

Read: Disabled

◆ COMP_INTENCLR_UP_Enabled

#define COMP_INTENCLR_UP_Enabled   (1UL)

Read: Enabled

◆ COMP_INTENCLR_UP_Msk

#define COMP_INTENCLR_UP_Msk   (0x1UL << COMP_INTENCLR_UP_Pos)

Bit mask of UP field.

◆ COMP_INTENCLR_UP_Pos

#define COMP_INTENCLR_UP_Pos   (2UL)

Position of UP field.

◆ COMP_INTENSET_CROSS_Disabled

#define COMP_INTENSET_CROSS_Disabled   (0UL)

Read: Disabled

◆ COMP_INTENSET_CROSS_Enabled

#define COMP_INTENSET_CROSS_Enabled   (1UL)

Read: Enabled

◆ COMP_INTENSET_CROSS_Msk

#define COMP_INTENSET_CROSS_Msk   (0x1UL << COMP_INTENSET_CROSS_Pos)

Bit mask of CROSS field.

◆ COMP_INTENSET_CROSS_Pos

#define COMP_INTENSET_CROSS_Pos   (3UL)

Position of CROSS field.

◆ COMP_INTENSET_CROSS_Set

#define COMP_INTENSET_CROSS_Set   (1UL)

Enable

◆ COMP_INTENSET_DOWN_Disabled

#define COMP_INTENSET_DOWN_Disabled   (0UL)

Read: Disabled

◆ COMP_INTENSET_DOWN_Enabled

#define COMP_INTENSET_DOWN_Enabled   (1UL)

Read: Enabled

◆ COMP_INTENSET_DOWN_Msk

#define COMP_INTENSET_DOWN_Msk   (0x1UL << COMP_INTENSET_DOWN_Pos)

Bit mask of DOWN field.

◆ COMP_INTENSET_DOWN_Pos

#define COMP_INTENSET_DOWN_Pos   (1UL)

Position of DOWN field.

◆ COMP_INTENSET_DOWN_Set

#define COMP_INTENSET_DOWN_Set   (1UL)

Enable

◆ COMP_INTENSET_READY_Disabled

#define COMP_INTENSET_READY_Disabled   (0UL)

Read: Disabled

◆ COMP_INTENSET_READY_Enabled

#define COMP_INTENSET_READY_Enabled   (1UL)

Read: Enabled

◆ COMP_INTENSET_READY_Msk

#define COMP_INTENSET_READY_Msk   (0x1UL << COMP_INTENSET_READY_Pos)

Bit mask of READY field.

◆ COMP_INTENSET_READY_Pos

#define COMP_INTENSET_READY_Pos   (0UL)

Position of READY field.

◆ COMP_INTENSET_READY_Set

#define COMP_INTENSET_READY_Set   (1UL)

Enable

◆ COMP_INTENSET_UP_Disabled

#define COMP_INTENSET_UP_Disabled   (0UL)

Read: Disabled

◆ COMP_INTENSET_UP_Enabled

#define COMP_INTENSET_UP_Enabled   (1UL)

Read: Enabled

◆ COMP_INTENSET_UP_Msk

#define COMP_INTENSET_UP_Msk   (0x1UL << COMP_INTENSET_UP_Pos)

Bit mask of UP field.

◆ COMP_INTENSET_UP_Pos

#define COMP_INTENSET_UP_Pos   (2UL)

Position of UP field.

◆ COMP_INTENSET_UP_Set

#define COMP_INTENSET_UP_Set   (1UL)

Enable

◆ COMP_ISOURCE_ISOURCE_Ien10mA

#define COMP_ISOURCE_ISOURCE_Ien10mA   (3UL)

Current source enabled (+/- 10 uA)

◆ COMP_ISOURCE_ISOURCE_Ien2mA5

#define COMP_ISOURCE_ISOURCE_Ien2mA5   (1UL)

Current source enabled (+/- 2.5 uA)

◆ COMP_ISOURCE_ISOURCE_Ien5mA

#define COMP_ISOURCE_ISOURCE_Ien5mA   (2UL)

Current source enabled (+/- 5 uA)

◆ COMP_ISOURCE_ISOURCE_Msk

#define COMP_ISOURCE_ISOURCE_Msk   (0x3UL << COMP_ISOURCE_ISOURCE_Pos)

Bit mask of ISOURCE field.

◆ COMP_ISOURCE_ISOURCE_Off

#define COMP_ISOURCE_ISOURCE_Off   (0UL)

Current source disabled

◆ COMP_ISOURCE_ISOURCE_Pos

#define COMP_ISOURCE_ISOURCE_Pos   (0UL)

Position of ISOURCE field.

◆ COMP_MODE_MAIN_Diff

#define COMP_MODE_MAIN_Diff   (1UL)

Differential mode

◆ COMP_MODE_MAIN_Msk

#define COMP_MODE_MAIN_Msk   (0x1UL << COMP_MODE_MAIN_Pos)

Bit mask of MAIN field.

◆ COMP_MODE_MAIN_Pos

#define COMP_MODE_MAIN_Pos   (8UL)

Position of MAIN field.

◆ COMP_MODE_MAIN_SE

#define COMP_MODE_MAIN_SE   (0UL)

Single-ended mode

◆ COMP_MODE_SP_High

#define COMP_MODE_SP_High   (2UL)

High-speed mode

◆ COMP_MODE_SP_Low

#define COMP_MODE_SP_Low   (0UL)

Low-power mode

◆ COMP_MODE_SP_Msk

#define COMP_MODE_SP_Msk   (0x3UL << COMP_MODE_SP_Pos)

Bit mask of SP field.

◆ COMP_MODE_SP_Normal

#define COMP_MODE_SP_Normal   (1UL)

Normal mode

◆ COMP_MODE_SP_Pos

#define COMP_MODE_SP_Pos   (0UL)

Position of SP field.

◆ COMP_PSEL_PSEL_AnalogInput0

#define COMP_PSEL_PSEL_AnalogInput0   (0UL)

AIN0 selected as analog input

◆ COMP_PSEL_PSEL_AnalogInput1

#define COMP_PSEL_PSEL_AnalogInput1   (1UL)

AIN1 selected as analog input

◆ COMP_PSEL_PSEL_AnalogInput2

#define COMP_PSEL_PSEL_AnalogInput2   (2UL)

AIN2 selected as analog input

◆ COMP_PSEL_PSEL_AnalogInput3

#define COMP_PSEL_PSEL_AnalogInput3   (3UL)

AIN3 selected as analog input

◆ COMP_PSEL_PSEL_AnalogInput4

#define COMP_PSEL_PSEL_AnalogInput4   (4UL)

AIN4 selected as analog input

◆ COMP_PSEL_PSEL_AnalogInput5

#define COMP_PSEL_PSEL_AnalogInput5   (5UL)

AIN5 selected as analog input

◆ COMP_PSEL_PSEL_AnalogInput6

#define COMP_PSEL_PSEL_AnalogInput6   (6UL)

AIN6 selected as analog input

◆ COMP_PSEL_PSEL_AnalogInput7

#define COMP_PSEL_PSEL_AnalogInput7   (7UL)

AIN7 selected as analog input

◆ COMP_PSEL_PSEL_Msk

#define COMP_PSEL_PSEL_Msk   (0x7UL << COMP_PSEL_PSEL_Pos)

Bit mask of PSEL field.

◆ COMP_PSEL_PSEL_Pos

#define COMP_PSEL_PSEL_Pos   (0UL)

Position of PSEL field.

◆ COMP_REFSEL_REFSEL_ARef

#define COMP_REFSEL_REFSEL_ARef   (7UL)

VREF = AREF (VDD >= VREF >= AREFMIN)

◆ COMP_REFSEL_REFSEL_Int1V2

#define COMP_REFSEL_REFSEL_Int1V2   (0UL)

VREF = internal 1.2 V reference (VDD >= 1.7 V)

◆ COMP_REFSEL_REFSEL_Int1V8

#define COMP_REFSEL_REFSEL_Int1V8   (1UL)

VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)

◆ COMP_REFSEL_REFSEL_Int2V4

#define COMP_REFSEL_REFSEL_Int2V4   (2UL)

VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)

◆ COMP_REFSEL_REFSEL_Msk

#define COMP_REFSEL_REFSEL_Msk   (0x7UL << COMP_REFSEL_REFSEL_Pos)

Bit mask of REFSEL field.

◆ COMP_REFSEL_REFSEL_Pos

#define COMP_REFSEL_REFSEL_Pos   (0UL)

Position of REFSEL field.

◆ COMP_REFSEL_REFSEL_VDD

#define COMP_REFSEL_REFSEL_VDD   (4UL)

VREF = VDD

◆ COMP_RESULT_RESULT_Above

#define COMP_RESULT_RESULT_Above   (1UL)

Input voltage is above the threshold (VIN+ > VIN-)

◆ COMP_RESULT_RESULT_Below

#define COMP_RESULT_RESULT_Below   (0UL)

Input voltage is below the threshold (VIN+ < VIN-)

◆ COMP_RESULT_RESULT_Msk

#define COMP_RESULT_RESULT_Msk   (0x1UL << COMP_RESULT_RESULT_Pos)

Bit mask of RESULT field.

◆ COMP_RESULT_RESULT_Pos

#define COMP_RESULT_RESULT_Pos   (0UL)

Position of RESULT field.

◆ COMP_SHORTS_CROSS_STOP_Disabled

#define COMP_SHORTS_CROSS_STOP_Disabled   (0UL)

Disable shortcut

◆ COMP_SHORTS_CROSS_STOP_Enabled

#define COMP_SHORTS_CROSS_STOP_Enabled   (1UL)

Enable shortcut

◆ COMP_SHORTS_CROSS_STOP_Msk

#define COMP_SHORTS_CROSS_STOP_Msk   (0x1UL << COMP_SHORTS_CROSS_STOP_Pos)

Bit mask of CROSS_STOP field.

◆ COMP_SHORTS_CROSS_STOP_Pos

#define COMP_SHORTS_CROSS_STOP_Pos   (4UL)

Position of CROSS_STOP field.

◆ COMP_SHORTS_DOWN_STOP_Disabled

#define COMP_SHORTS_DOWN_STOP_Disabled   (0UL)

Disable shortcut

◆ COMP_SHORTS_DOWN_STOP_Enabled

#define COMP_SHORTS_DOWN_STOP_Enabled   (1UL)

Enable shortcut

◆ COMP_SHORTS_DOWN_STOP_Msk

#define COMP_SHORTS_DOWN_STOP_Msk   (0x1UL << COMP_SHORTS_DOWN_STOP_Pos)

Bit mask of DOWN_STOP field.

◆ COMP_SHORTS_DOWN_STOP_Pos

#define COMP_SHORTS_DOWN_STOP_Pos   (2UL)

Position of DOWN_STOP field.

◆ COMP_SHORTS_READY_SAMPLE_Disabled

#define COMP_SHORTS_READY_SAMPLE_Disabled   (0UL)

Disable shortcut

◆ COMP_SHORTS_READY_SAMPLE_Enabled

#define COMP_SHORTS_READY_SAMPLE_Enabled   (1UL)

Enable shortcut

◆ COMP_SHORTS_READY_SAMPLE_Msk

#define COMP_SHORTS_READY_SAMPLE_Msk   (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos)

Bit mask of READY_SAMPLE field.

◆ COMP_SHORTS_READY_SAMPLE_Pos

#define COMP_SHORTS_READY_SAMPLE_Pos   (0UL)

Position of READY_SAMPLE field.

◆ COMP_SHORTS_READY_STOP_Disabled

#define COMP_SHORTS_READY_STOP_Disabled   (0UL)

Disable shortcut

◆ COMP_SHORTS_READY_STOP_Enabled

#define COMP_SHORTS_READY_STOP_Enabled   (1UL)

Enable shortcut

◆ COMP_SHORTS_READY_STOP_Msk

#define COMP_SHORTS_READY_STOP_Msk   (0x1UL << COMP_SHORTS_READY_STOP_Pos)

Bit mask of READY_STOP field.

◆ COMP_SHORTS_READY_STOP_Pos

#define COMP_SHORTS_READY_STOP_Pos   (1UL)

Position of READY_STOP field.

◆ COMP_SHORTS_UP_STOP_Disabled

#define COMP_SHORTS_UP_STOP_Disabled   (0UL)

Disable shortcut

◆ COMP_SHORTS_UP_STOP_Enabled

#define COMP_SHORTS_UP_STOP_Enabled   (1UL)

Enable shortcut

◆ COMP_SHORTS_UP_STOP_Msk

#define COMP_SHORTS_UP_STOP_Msk   (0x1UL << COMP_SHORTS_UP_STOP_Pos)

Bit mask of UP_STOP field.

◆ COMP_SHORTS_UP_STOP_Pos

#define COMP_SHORTS_UP_STOP_Pos   (3UL)

Position of UP_STOP field.

◆ COMP_TH_THDOWN_Msk

#define COMP_TH_THDOWN_Msk   (0x3FUL << COMP_TH_THDOWN_Pos)

Bit mask of THDOWN field.

◆ COMP_TH_THDOWN_Pos

#define COMP_TH_THDOWN_Pos   (0UL)

Position of THDOWN field.

◆ COMP_TH_THUP_Msk

#define COMP_TH_THUP_Msk   (0x3FUL << COMP_TH_THUP_Pos)

Bit mask of THUP field.

◆ COMP_TH_THUP_Pos

#define COMP_TH_THUP_Pos   (8UL)

Position of THUP field.

◆ ECB_ECBDATAPTR_ECBDATAPTR_Msk

#define ECB_ECBDATAPTR_ECBDATAPTR_Msk   (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos)

Bit mask of ECBDATAPTR field.

◆ ECB_ECBDATAPTR_ECBDATAPTR_Pos

#define ECB_ECBDATAPTR_ECBDATAPTR_Pos   (0UL)

Position of ECBDATAPTR field.

◆ ECB_INTENCLR_ENDECB_Clear

#define ECB_INTENCLR_ENDECB_Clear   (1UL)

Disable

◆ ECB_INTENCLR_ENDECB_Disabled

#define ECB_INTENCLR_ENDECB_Disabled   (0UL)

Read: Disabled

◆ ECB_INTENCLR_ENDECB_Enabled

#define ECB_INTENCLR_ENDECB_Enabled   (1UL)

Read: Enabled

◆ ECB_INTENCLR_ENDECB_Msk

#define ECB_INTENCLR_ENDECB_Msk   (0x1UL << ECB_INTENCLR_ENDECB_Pos)

Bit mask of ENDECB field.

◆ ECB_INTENCLR_ENDECB_Pos

#define ECB_INTENCLR_ENDECB_Pos   (0UL)

Position of ENDECB field.

◆ ECB_INTENCLR_ERRORECB_Clear

#define ECB_INTENCLR_ERRORECB_Clear   (1UL)

Disable

◆ ECB_INTENCLR_ERRORECB_Disabled

#define ECB_INTENCLR_ERRORECB_Disabled   (0UL)

Read: Disabled

◆ ECB_INTENCLR_ERRORECB_Enabled

#define ECB_INTENCLR_ERRORECB_Enabled   (1UL)

Read: Enabled

◆ ECB_INTENCLR_ERRORECB_Msk

#define ECB_INTENCLR_ERRORECB_Msk   (0x1UL << ECB_INTENCLR_ERRORECB_Pos)

Bit mask of ERRORECB field.

◆ ECB_INTENCLR_ERRORECB_Pos

#define ECB_INTENCLR_ERRORECB_Pos   (1UL)

Position of ERRORECB field.

◆ ECB_INTENSET_ENDECB_Disabled

#define ECB_INTENSET_ENDECB_Disabled   (0UL)

Read: Disabled

◆ ECB_INTENSET_ENDECB_Enabled

#define ECB_INTENSET_ENDECB_Enabled   (1UL)

Read: Enabled

◆ ECB_INTENSET_ENDECB_Msk

#define ECB_INTENSET_ENDECB_Msk   (0x1UL << ECB_INTENSET_ENDECB_Pos)

Bit mask of ENDECB field.

◆ ECB_INTENSET_ENDECB_Pos

#define ECB_INTENSET_ENDECB_Pos   (0UL)

Position of ENDECB field.

◆ ECB_INTENSET_ENDECB_Set

#define ECB_INTENSET_ENDECB_Set   (1UL)

Enable

◆ ECB_INTENSET_ERRORECB_Disabled

#define ECB_INTENSET_ERRORECB_Disabled   (0UL)

Read: Disabled

◆ ECB_INTENSET_ERRORECB_Enabled

#define ECB_INTENSET_ERRORECB_Enabled   (1UL)

Read: Enabled

◆ ECB_INTENSET_ERRORECB_Msk

#define ECB_INTENSET_ERRORECB_Msk   (0x1UL << ECB_INTENSET_ERRORECB_Pos)

Bit mask of ERRORECB field.

◆ ECB_INTENSET_ERRORECB_Pos

#define ECB_INTENSET_ERRORECB_Pos   (1UL)

Position of ERRORECB field.

◆ ECB_INTENSET_ERRORECB_Set

#define ECB_INTENSET_ERRORECB_Set   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED0_Disabled

#define EGU_INTEN_TRIGGERED0_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED0_Enabled

#define EGU_INTEN_TRIGGERED0_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED0_Msk

#define EGU_INTEN_TRIGGERED0_Msk   (0x1UL << EGU_INTEN_TRIGGERED0_Pos)

Bit mask of TRIGGERED0 field.

◆ EGU_INTEN_TRIGGERED0_Pos

#define EGU_INTEN_TRIGGERED0_Pos   (0UL)

Position of TRIGGERED0 field.

◆ EGU_INTEN_TRIGGERED10_Disabled

#define EGU_INTEN_TRIGGERED10_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED10_Enabled

#define EGU_INTEN_TRIGGERED10_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED10_Msk

#define EGU_INTEN_TRIGGERED10_Msk   (0x1UL << EGU_INTEN_TRIGGERED10_Pos)

Bit mask of TRIGGERED10 field.

◆ EGU_INTEN_TRIGGERED10_Pos

#define EGU_INTEN_TRIGGERED10_Pos   (10UL)

Position of TRIGGERED10 field.

◆ EGU_INTEN_TRIGGERED11_Disabled

#define EGU_INTEN_TRIGGERED11_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED11_Enabled

#define EGU_INTEN_TRIGGERED11_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED11_Msk

#define EGU_INTEN_TRIGGERED11_Msk   (0x1UL << EGU_INTEN_TRIGGERED11_Pos)

Bit mask of TRIGGERED11 field.

◆ EGU_INTEN_TRIGGERED11_Pos

#define EGU_INTEN_TRIGGERED11_Pos   (11UL)

Position of TRIGGERED11 field.

◆ EGU_INTEN_TRIGGERED12_Disabled

#define EGU_INTEN_TRIGGERED12_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED12_Enabled

#define EGU_INTEN_TRIGGERED12_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED12_Msk

#define EGU_INTEN_TRIGGERED12_Msk   (0x1UL << EGU_INTEN_TRIGGERED12_Pos)

Bit mask of TRIGGERED12 field.

◆ EGU_INTEN_TRIGGERED12_Pos

#define EGU_INTEN_TRIGGERED12_Pos   (12UL)

Position of TRIGGERED12 field.

◆ EGU_INTEN_TRIGGERED13_Disabled

#define EGU_INTEN_TRIGGERED13_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED13_Enabled

#define EGU_INTEN_TRIGGERED13_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED13_Msk

#define EGU_INTEN_TRIGGERED13_Msk   (0x1UL << EGU_INTEN_TRIGGERED13_Pos)

Bit mask of TRIGGERED13 field.

◆ EGU_INTEN_TRIGGERED13_Pos

#define EGU_INTEN_TRIGGERED13_Pos   (13UL)

Position of TRIGGERED13 field.

◆ EGU_INTEN_TRIGGERED14_Disabled

#define EGU_INTEN_TRIGGERED14_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED14_Enabled

#define EGU_INTEN_TRIGGERED14_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED14_Msk

#define EGU_INTEN_TRIGGERED14_Msk   (0x1UL << EGU_INTEN_TRIGGERED14_Pos)

Bit mask of TRIGGERED14 field.

◆ EGU_INTEN_TRIGGERED14_Pos

#define EGU_INTEN_TRIGGERED14_Pos   (14UL)

Position of TRIGGERED14 field.

◆ EGU_INTEN_TRIGGERED15_Disabled

#define EGU_INTEN_TRIGGERED15_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED15_Enabled

#define EGU_INTEN_TRIGGERED15_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED15_Msk

#define EGU_INTEN_TRIGGERED15_Msk   (0x1UL << EGU_INTEN_TRIGGERED15_Pos)

Bit mask of TRIGGERED15 field.

◆ EGU_INTEN_TRIGGERED15_Pos

#define EGU_INTEN_TRIGGERED15_Pos   (15UL)

Position of TRIGGERED15 field.

◆ EGU_INTEN_TRIGGERED1_Disabled

#define EGU_INTEN_TRIGGERED1_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED1_Enabled

#define EGU_INTEN_TRIGGERED1_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED1_Msk

#define EGU_INTEN_TRIGGERED1_Msk   (0x1UL << EGU_INTEN_TRIGGERED1_Pos)

Bit mask of TRIGGERED1 field.

◆ EGU_INTEN_TRIGGERED1_Pos

#define EGU_INTEN_TRIGGERED1_Pos   (1UL)

Position of TRIGGERED1 field.

◆ EGU_INTEN_TRIGGERED2_Disabled

#define EGU_INTEN_TRIGGERED2_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED2_Enabled

#define EGU_INTEN_TRIGGERED2_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED2_Msk

#define EGU_INTEN_TRIGGERED2_Msk   (0x1UL << EGU_INTEN_TRIGGERED2_Pos)

Bit mask of TRIGGERED2 field.

◆ EGU_INTEN_TRIGGERED2_Pos

#define EGU_INTEN_TRIGGERED2_Pos   (2UL)

Position of TRIGGERED2 field.

◆ EGU_INTEN_TRIGGERED3_Disabled

#define EGU_INTEN_TRIGGERED3_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED3_Enabled

#define EGU_INTEN_TRIGGERED3_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED3_Msk

#define EGU_INTEN_TRIGGERED3_Msk   (0x1UL << EGU_INTEN_TRIGGERED3_Pos)

Bit mask of TRIGGERED3 field.

◆ EGU_INTEN_TRIGGERED3_Pos

#define EGU_INTEN_TRIGGERED3_Pos   (3UL)

Position of TRIGGERED3 field.

◆ EGU_INTEN_TRIGGERED4_Disabled

#define EGU_INTEN_TRIGGERED4_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED4_Enabled

#define EGU_INTEN_TRIGGERED4_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED4_Msk

#define EGU_INTEN_TRIGGERED4_Msk   (0x1UL << EGU_INTEN_TRIGGERED4_Pos)

Bit mask of TRIGGERED4 field.

◆ EGU_INTEN_TRIGGERED4_Pos

#define EGU_INTEN_TRIGGERED4_Pos   (4UL)

Position of TRIGGERED4 field.

◆ EGU_INTEN_TRIGGERED5_Disabled

#define EGU_INTEN_TRIGGERED5_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED5_Enabled

#define EGU_INTEN_TRIGGERED5_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED5_Msk

#define EGU_INTEN_TRIGGERED5_Msk   (0x1UL << EGU_INTEN_TRIGGERED5_Pos)

Bit mask of TRIGGERED5 field.

◆ EGU_INTEN_TRIGGERED5_Pos

#define EGU_INTEN_TRIGGERED5_Pos   (5UL)

Position of TRIGGERED5 field.

◆ EGU_INTEN_TRIGGERED6_Disabled

#define EGU_INTEN_TRIGGERED6_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED6_Enabled

#define EGU_INTEN_TRIGGERED6_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED6_Msk

#define EGU_INTEN_TRIGGERED6_Msk   (0x1UL << EGU_INTEN_TRIGGERED6_Pos)

Bit mask of TRIGGERED6 field.

◆ EGU_INTEN_TRIGGERED6_Pos

#define EGU_INTEN_TRIGGERED6_Pos   (6UL)

Position of TRIGGERED6 field.

◆ EGU_INTEN_TRIGGERED7_Disabled

#define EGU_INTEN_TRIGGERED7_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED7_Enabled

#define EGU_INTEN_TRIGGERED7_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED7_Msk

#define EGU_INTEN_TRIGGERED7_Msk   (0x1UL << EGU_INTEN_TRIGGERED7_Pos)

Bit mask of TRIGGERED7 field.

◆ EGU_INTEN_TRIGGERED7_Pos

#define EGU_INTEN_TRIGGERED7_Pos   (7UL)

Position of TRIGGERED7 field.

◆ EGU_INTEN_TRIGGERED8_Disabled

#define EGU_INTEN_TRIGGERED8_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED8_Enabled

#define EGU_INTEN_TRIGGERED8_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED8_Msk

#define EGU_INTEN_TRIGGERED8_Msk   (0x1UL << EGU_INTEN_TRIGGERED8_Pos)

Bit mask of TRIGGERED8 field.

◆ EGU_INTEN_TRIGGERED8_Pos

#define EGU_INTEN_TRIGGERED8_Pos   (8UL)

Position of TRIGGERED8 field.

◆ EGU_INTEN_TRIGGERED9_Disabled

#define EGU_INTEN_TRIGGERED9_Disabled   (0UL)

Disable

◆ EGU_INTEN_TRIGGERED9_Enabled

#define EGU_INTEN_TRIGGERED9_Enabled   (1UL)

Enable

◆ EGU_INTEN_TRIGGERED9_Msk

#define EGU_INTEN_TRIGGERED9_Msk   (0x1UL << EGU_INTEN_TRIGGERED9_Pos)

Bit mask of TRIGGERED9 field.

◆ EGU_INTEN_TRIGGERED9_Pos

#define EGU_INTEN_TRIGGERED9_Pos   (9UL)

Position of TRIGGERED9 field.

◆ EGU_INTENCLR_TRIGGERED0_Clear

#define EGU_INTENCLR_TRIGGERED0_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED0_Disabled

#define EGU_INTENCLR_TRIGGERED0_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED0_Enabled

#define EGU_INTENCLR_TRIGGERED0_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED0_Msk

#define EGU_INTENCLR_TRIGGERED0_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos)

Bit mask of TRIGGERED0 field.

◆ EGU_INTENCLR_TRIGGERED0_Pos

#define EGU_INTENCLR_TRIGGERED0_Pos   (0UL)

Position of TRIGGERED0 field.

◆ EGU_INTENCLR_TRIGGERED10_Clear

#define EGU_INTENCLR_TRIGGERED10_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED10_Disabled

#define EGU_INTENCLR_TRIGGERED10_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED10_Enabled

#define EGU_INTENCLR_TRIGGERED10_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED10_Msk

#define EGU_INTENCLR_TRIGGERED10_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos)

Bit mask of TRIGGERED10 field.

◆ EGU_INTENCLR_TRIGGERED10_Pos

#define EGU_INTENCLR_TRIGGERED10_Pos   (10UL)

Position of TRIGGERED10 field.

◆ EGU_INTENCLR_TRIGGERED11_Clear

#define EGU_INTENCLR_TRIGGERED11_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED11_Disabled

#define EGU_INTENCLR_TRIGGERED11_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED11_Enabled

#define EGU_INTENCLR_TRIGGERED11_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED11_Msk

#define EGU_INTENCLR_TRIGGERED11_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos)

Bit mask of TRIGGERED11 field.

◆ EGU_INTENCLR_TRIGGERED11_Pos

#define EGU_INTENCLR_TRIGGERED11_Pos   (11UL)

Position of TRIGGERED11 field.

◆ EGU_INTENCLR_TRIGGERED12_Clear

#define EGU_INTENCLR_TRIGGERED12_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED12_Disabled

#define EGU_INTENCLR_TRIGGERED12_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED12_Enabled

#define EGU_INTENCLR_TRIGGERED12_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED12_Msk

#define EGU_INTENCLR_TRIGGERED12_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos)

Bit mask of TRIGGERED12 field.

◆ EGU_INTENCLR_TRIGGERED12_Pos

#define EGU_INTENCLR_TRIGGERED12_Pos   (12UL)

Position of TRIGGERED12 field.

◆ EGU_INTENCLR_TRIGGERED13_Clear

#define EGU_INTENCLR_TRIGGERED13_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED13_Disabled

#define EGU_INTENCLR_TRIGGERED13_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED13_Enabled

#define EGU_INTENCLR_TRIGGERED13_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED13_Msk

#define EGU_INTENCLR_TRIGGERED13_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos)

Bit mask of TRIGGERED13 field.

◆ EGU_INTENCLR_TRIGGERED13_Pos

#define EGU_INTENCLR_TRIGGERED13_Pos   (13UL)

Position of TRIGGERED13 field.

◆ EGU_INTENCLR_TRIGGERED14_Clear

#define EGU_INTENCLR_TRIGGERED14_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED14_Disabled

#define EGU_INTENCLR_TRIGGERED14_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED14_Enabled

#define EGU_INTENCLR_TRIGGERED14_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED14_Msk

#define EGU_INTENCLR_TRIGGERED14_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos)

Bit mask of TRIGGERED14 field.

◆ EGU_INTENCLR_TRIGGERED14_Pos

#define EGU_INTENCLR_TRIGGERED14_Pos   (14UL)

Position of TRIGGERED14 field.

◆ EGU_INTENCLR_TRIGGERED15_Clear

#define EGU_INTENCLR_TRIGGERED15_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED15_Disabled

#define EGU_INTENCLR_TRIGGERED15_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED15_Enabled

#define EGU_INTENCLR_TRIGGERED15_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED15_Msk

#define EGU_INTENCLR_TRIGGERED15_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos)

Bit mask of TRIGGERED15 field.

◆ EGU_INTENCLR_TRIGGERED15_Pos

#define EGU_INTENCLR_TRIGGERED15_Pos   (15UL)

Position of TRIGGERED15 field.

◆ EGU_INTENCLR_TRIGGERED1_Clear

#define EGU_INTENCLR_TRIGGERED1_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED1_Disabled

#define EGU_INTENCLR_TRIGGERED1_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED1_Enabled

#define EGU_INTENCLR_TRIGGERED1_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED1_Msk

#define EGU_INTENCLR_TRIGGERED1_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos)

Bit mask of TRIGGERED1 field.

◆ EGU_INTENCLR_TRIGGERED1_Pos

#define EGU_INTENCLR_TRIGGERED1_Pos   (1UL)

Position of TRIGGERED1 field.

◆ EGU_INTENCLR_TRIGGERED2_Clear

#define EGU_INTENCLR_TRIGGERED2_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED2_Disabled

#define EGU_INTENCLR_TRIGGERED2_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED2_Enabled

#define EGU_INTENCLR_TRIGGERED2_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED2_Msk

#define EGU_INTENCLR_TRIGGERED2_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos)

Bit mask of TRIGGERED2 field.

◆ EGU_INTENCLR_TRIGGERED2_Pos

#define EGU_INTENCLR_TRIGGERED2_Pos   (2UL)

Position of TRIGGERED2 field.

◆ EGU_INTENCLR_TRIGGERED3_Clear

#define EGU_INTENCLR_TRIGGERED3_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED3_Disabled

#define EGU_INTENCLR_TRIGGERED3_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED3_Enabled

#define EGU_INTENCLR_TRIGGERED3_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED3_Msk

#define EGU_INTENCLR_TRIGGERED3_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos)

Bit mask of TRIGGERED3 field.

◆ EGU_INTENCLR_TRIGGERED3_Pos

#define EGU_INTENCLR_TRIGGERED3_Pos   (3UL)

Position of TRIGGERED3 field.

◆ EGU_INTENCLR_TRIGGERED4_Clear

#define EGU_INTENCLR_TRIGGERED4_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED4_Disabled

#define EGU_INTENCLR_TRIGGERED4_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED4_Enabled

#define EGU_INTENCLR_TRIGGERED4_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED4_Msk

#define EGU_INTENCLR_TRIGGERED4_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos)

Bit mask of TRIGGERED4 field.

◆ EGU_INTENCLR_TRIGGERED4_Pos

#define EGU_INTENCLR_TRIGGERED4_Pos   (4UL)

Position of TRIGGERED4 field.

◆ EGU_INTENCLR_TRIGGERED5_Clear

#define EGU_INTENCLR_TRIGGERED5_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED5_Disabled

#define EGU_INTENCLR_TRIGGERED5_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED5_Enabled

#define EGU_INTENCLR_TRIGGERED5_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED5_Msk

#define EGU_INTENCLR_TRIGGERED5_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos)

Bit mask of TRIGGERED5 field.

◆ EGU_INTENCLR_TRIGGERED5_Pos

#define EGU_INTENCLR_TRIGGERED5_Pos   (5UL)

Position of TRIGGERED5 field.

◆ EGU_INTENCLR_TRIGGERED6_Clear

#define EGU_INTENCLR_TRIGGERED6_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED6_Disabled

#define EGU_INTENCLR_TRIGGERED6_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED6_Enabled

#define EGU_INTENCLR_TRIGGERED6_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED6_Msk

#define EGU_INTENCLR_TRIGGERED6_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos)

Bit mask of TRIGGERED6 field.

◆ EGU_INTENCLR_TRIGGERED6_Pos

#define EGU_INTENCLR_TRIGGERED6_Pos   (6UL)

Position of TRIGGERED6 field.

◆ EGU_INTENCLR_TRIGGERED7_Clear

#define EGU_INTENCLR_TRIGGERED7_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED7_Disabled

#define EGU_INTENCLR_TRIGGERED7_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED7_Enabled

#define EGU_INTENCLR_TRIGGERED7_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED7_Msk

#define EGU_INTENCLR_TRIGGERED7_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos)

Bit mask of TRIGGERED7 field.

◆ EGU_INTENCLR_TRIGGERED7_Pos

#define EGU_INTENCLR_TRIGGERED7_Pos   (7UL)

Position of TRIGGERED7 field.

◆ EGU_INTENCLR_TRIGGERED8_Clear

#define EGU_INTENCLR_TRIGGERED8_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED8_Disabled

#define EGU_INTENCLR_TRIGGERED8_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED8_Enabled

#define EGU_INTENCLR_TRIGGERED8_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED8_Msk

#define EGU_INTENCLR_TRIGGERED8_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos)

Bit mask of TRIGGERED8 field.

◆ EGU_INTENCLR_TRIGGERED8_Pos

#define EGU_INTENCLR_TRIGGERED8_Pos   (8UL)

Position of TRIGGERED8 field.

◆ EGU_INTENCLR_TRIGGERED9_Clear

#define EGU_INTENCLR_TRIGGERED9_Clear   (1UL)

Disable

◆ EGU_INTENCLR_TRIGGERED9_Disabled

#define EGU_INTENCLR_TRIGGERED9_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENCLR_TRIGGERED9_Enabled

#define EGU_INTENCLR_TRIGGERED9_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENCLR_TRIGGERED9_Msk

#define EGU_INTENCLR_TRIGGERED9_Msk   (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos)

Bit mask of TRIGGERED9 field.

◆ EGU_INTENCLR_TRIGGERED9_Pos

#define EGU_INTENCLR_TRIGGERED9_Pos   (9UL)

Position of TRIGGERED9 field.

◆ EGU_INTENSET_TRIGGERED0_Disabled

#define EGU_INTENSET_TRIGGERED0_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED0_Enabled

#define EGU_INTENSET_TRIGGERED0_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED0_Msk

#define EGU_INTENSET_TRIGGERED0_Msk   (0x1UL << EGU_INTENSET_TRIGGERED0_Pos)

Bit mask of TRIGGERED0 field.

◆ EGU_INTENSET_TRIGGERED0_Pos

#define EGU_INTENSET_TRIGGERED0_Pos   (0UL)

Position of TRIGGERED0 field.

◆ EGU_INTENSET_TRIGGERED0_Set

#define EGU_INTENSET_TRIGGERED0_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED10_Disabled

#define EGU_INTENSET_TRIGGERED10_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED10_Enabled

#define EGU_INTENSET_TRIGGERED10_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED10_Msk

#define EGU_INTENSET_TRIGGERED10_Msk   (0x1UL << EGU_INTENSET_TRIGGERED10_Pos)

Bit mask of TRIGGERED10 field.

◆ EGU_INTENSET_TRIGGERED10_Pos

#define EGU_INTENSET_TRIGGERED10_Pos   (10UL)

Position of TRIGGERED10 field.

◆ EGU_INTENSET_TRIGGERED10_Set

#define EGU_INTENSET_TRIGGERED10_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED11_Disabled

#define EGU_INTENSET_TRIGGERED11_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED11_Enabled

#define EGU_INTENSET_TRIGGERED11_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED11_Msk

#define EGU_INTENSET_TRIGGERED11_Msk   (0x1UL << EGU_INTENSET_TRIGGERED11_Pos)

Bit mask of TRIGGERED11 field.

◆ EGU_INTENSET_TRIGGERED11_Pos

#define EGU_INTENSET_TRIGGERED11_Pos   (11UL)

Position of TRIGGERED11 field.

◆ EGU_INTENSET_TRIGGERED11_Set

#define EGU_INTENSET_TRIGGERED11_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED12_Disabled

#define EGU_INTENSET_TRIGGERED12_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED12_Enabled

#define EGU_INTENSET_TRIGGERED12_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED12_Msk

#define EGU_INTENSET_TRIGGERED12_Msk   (0x1UL << EGU_INTENSET_TRIGGERED12_Pos)

Bit mask of TRIGGERED12 field.

◆ EGU_INTENSET_TRIGGERED12_Pos

#define EGU_INTENSET_TRIGGERED12_Pos   (12UL)

Position of TRIGGERED12 field.

◆ EGU_INTENSET_TRIGGERED12_Set

#define EGU_INTENSET_TRIGGERED12_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED13_Disabled

#define EGU_INTENSET_TRIGGERED13_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED13_Enabled

#define EGU_INTENSET_TRIGGERED13_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED13_Msk

#define EGU_INTENSET_TRIGGERED13_Msk   (0x1UL << EGU_INTENSET_TRIGGERED13_Pos)

Bit mask of TRIGGERED13 field.

◆ EGU_INTENSET_TRIGGERED13_Pos

#define EGU_INTENSET_TRIGGERED13_Pos   (13UL)

Position of TRIGGERED13 field.

◆ EGU_INTENSET_TRIGGERED13_Set

#define EGU_INTENSET_TRIGGERED13_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED14_Disabled

#define EGU_INTENSET_TRIGGERED14_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED14_Enabled

#define EGU_INTENSET_TRIGGERED14_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED14_Msk

#define EGU_INTENSET_TRIGGERED14_Msk   (0x1UL << EGU_INTENSET_TRIGGERED14_Pos)

Bit mask of TRIGGERED14 field.

◆ EGU_INTENSET_TRIGGERED14_Pos

#define EGU_INTENSET_TRIGGERED14_Pos   (14UL)

Position of TRIGGERED14 field.

◆ EGU_INTENSET_TRIGGERED14_Set

#define EGU_INTENSET_TRIGGERED14_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED15_Disabled

#define EGU_INTENSET_TRIGGERED15_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED15_Enabled

#define EGU_INTENSET_TRIGGERED15_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED15_Msk

#define EGU_INTENSET_TRIGGERED15_Msk   (0x1UL << EGU_INTENSET_TRIGGERED15_Pos)

Bit mask of TRIGGERED15 field.

◆ EGU_INTENSET_TRIGGERED15_Pos

#define EGU_INTENSET_TRIGGERED15_Pos   (15UL)

Position of TRIGGERED15 field.

◆ EGU_INTENSET_TRIGGERED15_Set

#define EGU_INTENSET_TRIGGERED15_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED1_Disabled

#define EGU_INTENSET_TRIGGERED1_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED1_Enabled

#define EGU_INTENSET_TRIGGERED1_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED1_Msk

#define EGU_INTENSET_TRIGGERED1_Msk   (0x1UL << EGU_INTENSET_TRIGGERED1_Pos)

Bit mask of TRIGGERED1 field.

◆ EGU_INTENSET_TRIGGERED1_Pos

#define EGU_INTENSET_TRIGGERED1_Pos   (1UL)

Position of TRIGGERED1 field.

◆ EGU_INTENSET_TRIGGERED1_Set

#define EGU_INTENSET_TRIGGERED1_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED2_Disabled

#define EGU_INTENSET_TRIGGERED2_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED2_Enabled

#define EGU_INTENSET_TRIGGERED2_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED2_Msk

#define EGU_INTENSET_TRIGGERED2_Msk   (0x1UL << EGU_INTENSET_TRIGGERED2_Pos)

Bit mask of TRIGGERED2 field.

◆ EGU_INTENSET_TRIGGERED2_Pos

#define EGU_INTENSET_TRIGGERED2_Pos   (2UL)

Position of TRIGGERED2 field.

◆ EGU_INTENSET_TRIGGERED2_Set

#define EGU_INTENSET_TRIGGERED2_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED3_Disabled

#define EGU_INTENSET_TRIGGERED3_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED3_Enabled

#define EGU_INTENSET_TRIGGERED3_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED3_Msk

#define EGU_INTENSET_TRIGGERED3_Msk   (0x1UL << EGU_INTENSET_TRIGGERED3_Pos)

Bit mask of TRIGGERED3 field.

◆ EGU_INTENSET_TRIGGERED3_Pos

#define EGU_INTENSET_TRIGGERED3_Pos   (3UL)

Position of TRIGGERED3 field.

◆ EGU_INTENSET_TRIGGERED3_Set

#define EGU_INTENSET_TRIGGERED3_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED4_Disabled

#define EGU_INTENSET_TRIGGERED4_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED4_Enabled

#define EGU_INTENSET_TRIGGERED4_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED4_Msk

#define EGU_INTENSET_TRIGGERED4_Msk   (0x1UL << EGU_INTENSET_TRIGGERED4_Pos)

Bit mask of TRIGGERED4 field.

◆ EGU_INTENSET_TRIGGERED4_Pos

#define EGU_INTENSET_TRIGGERED4_Pos   (4UL)

Position of TRIGGERED4 field.

◆ EGU_INTENSET_TRIGGERED4_Set

#define EGU_INTENSET_TRIGGERED4_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED5_Disabled

#define EGU_INTENSET_TRIGGERED5_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED5_Enabled

#define EGU_INTENSET_TRIGGERED5_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED5_Msk

#define EGU_INTENSET_TRIGGERED5_Msk   (0x1UL << EGU_INTENSET_TRIGGERED5_Pos)

Bit mask of TRIGGERED5 field.

◆ EGU_INTENSET_TRIGGERED5_Pos

#define EGU_INTENSET_TRIGGERED5_Pos   (5UL)

Position of TRIGGERED5 field.

◆ EGU_INTENSET_TRIGGERED5_Set

#define EGU_INTENSET_TRIGGERED5_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED6_Disabled

#define EGU_INTENSET_TRIGGERED6_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED6_Enabled

#define EGU_INTENSET_TRIGGERED6_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED6_Msk

#define EGU_INTENSET_TRIGGERED6_Msk   (0x1UL << EGU_INTENSET_TRIGGERED6_Pos)

Bit mask of TRIGGERED6 field.

◆ EGU_INTENSET_TRIGGERED6_Pos

#define EGU_INTENSET_TRIGGERED6_Pos   (6UL)

Position of TRIGGERED6 field.

◆ EGU_INTENSET_TRIGGERED6_Set

#define EGU_INTENSET_TRIGGERED6_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED7_Disabled

#define EGU_INTENSET_TRIGGERED7_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED7_Enabled

#define EGU_INTENSET_TRIGGERED7_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED7_Msk

#define EGU_INTENSET_TRIGGERED7_Msk   (0x1UL << EGU_INTENSET_TRIGGERED7_Pos)

Bit mask of TRIGGERED7 field.

◆ EGU_INTENSET_TRIGGERED7_Pos

#define EGU_INTENSET_TRIGGERED7_Pos   (7UL)

Position of TRIGGERED7 field.

◆ EGU_INTENSET_TRIGGERED7_Set

#define EGU_INTENSET_TRIGGERED7_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED8_Disabled

#define EGU_INTENSET_TRIGGERED8_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED8_Enabled

#define EGU_INTENSET_TRIGGERED8_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED8_Msk

#define EGU_INTENSET_TRIGGERED8_Msk   (0x1UL << EGU_INTENSET_TRIGGERED8_Pos)

Bit mask of TRIGGERED8 field.

◆ EGU_INTENSET_TRIGGERED8_Pos

#define EGU_INTENSET_TRIGGERED8_Pos   (8UL)

Position of TRIGGERED8 field.

◆ EGU_INTENSET_TRIGGERED8_Set

#define EGU_INTENSET_TRIGGERED8_Set   (1UL)

Enable

◆ EGU_INTENSET_TRIGGERED9_Disabled

#define EGU_INTENSET_TRIGGERED9_Disabled   (0UL)

Read: Disabled

◆ EGU_INTENSET_TRIGGERED9_Enabled

#define EGU_INTENSET_TRIGGERED9_Enabled   (1UL)

Read: Enabled

◆ EGU_INTENSET_TRIGGERED9_Msk

#define EGU_INTENSET_TRIGGERED9_Msk   (0x1UL << EGU_INTENSET_TRIGGERED9_Pos)

Bit mask of TRIGGERED9 field.

◆ EGU_INTENSET_TRIGGERED9_Pos

#define EGU_INTENSET_TRIGGERED9_Pos   (9UL)

Position of TRIGGERED9 field.

◆ EGU_INTENSET_TRIGGERED9_Set

#define EGU_INTENSET_TRIGGERED9_Set   (1UL)

Enable

◆ FICR_CODEPAGESIZE_CODEPAGESIZE_Msk

#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk   (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos)

Bit mask of CODEPAGESIZE field.

◆ FICR_CODEPAGESIZE_CODEPAGESIZE_Pos

#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos   (0UL)

Position of CODEPAGESIZE field.

◆ FICR_CODESIZE_CODESIZE_Msk

#define FICR_CODESIZE_CODESIZE_Msk   (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos)

Bit mask of CODESIZE field.

◆ FICR_CODESIZE_CODESIZE_Pos

#define FICR_CODESIZE_CODESIZE_Pos   (0UL)

Position of CODESIZE field.

◆ FICR_DEVICEADDR_DEVICEADDR_Msk

#define FICR_DEVICEADDR_DEVICEADDR_Msk   (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos)

Bit mask of DEVICEADDR field.

◆ FICR_DEVICEADDR_DEVICEADDR_Pos

#define FICR_DEVICEADDR_DEVICEADDR_Pos   (0UL)

Position of DEVICEADDR field.

◆ FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk

#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk   (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos)

Bit mask of DEVICEADDRTYPE field.

◆ FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos

#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos   (0UL)

Position of DEVICEADDRTYPE field.

◆ FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public

#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public   (0UL)

Public address

◆ FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random

#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random   (1UL)

Random address

◆ FICR_DEVICEID_DEVICEID_Msk

#define FICR_DEVICEID_DEVICEID_Msk   (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos)

Bit mask of DEVICEID field.

◆ FICR_DEVICEID_DEVICEID_Pos

#define FICR_DEVICEID_DEVICEID_Pos   (0UL)

Position of DEVICEID field.

◆ FICR_ER_ER_Msk

#define FICR_ER_ER_Msk   (0xFFFFFFFFUL << FICR_ER_ER_Pos)

Bit mask of ER field.

◆ FICR_ER_ER_Pos

#define FICR_ER_ER_Pos   (0UL)

Position of ER field.

◆ FICR_INFO_FLASH_FLASH_K128

#define FICR_INFO_FLASH_FLASH_K128   (0x80UL)

128 kByte FLASH

◆ FICR_INFO_FLASH_FLASH_K256

#define FICR_INFO_FLASH_FLASH_K256   (0x100UL)

256 kByte FLASH

◆ FICR_INFO_FLASH_FLASH_K512

#define FICR_INFO_FLASH_FLASH_K512   (0x200UL)

512 kByte FLASH

◆ FICR_INFO_FLASH_FLASH_Msk

#define FICR_INFO_FLASH_FLASH_Msk   (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos)

Bit mask of FLASH field.

◆ FICR_INFO_FLASH_FLASH_Pos

#define FICR_INFO_FLASH_FLASH_Pos   (0UL)

Position of FLASH field.

◆ FICR_INFO_FLASH_FLASH_Unspecified

#define FICR_INFO_FLASH_FLASH_Unspecified   (0xFFFFFFFFUL)

Unspecified

◆ FICR_INFO_PACKAGE_PACKAGE_CH

#define FICR_INFO_PACKAGE_PACKAGE_CH   (0x2001UL)

CHxx - 7x8 WLCSP 56 balls

◆ FICR_INFO_PACKAGE_PACKAGE_CI

#define FICR_INFO_PACKAGE_PACKAGE_CI   (0x2002UL)

CIxx - 7x8 WLCSP 56 balls

◆ FICR_INFO_PACKAGE_PACKAGE_CK

#define FICR_INFO_PACKAGE_PACKAGE_CK   (0x2005UL)

CKxx - 7x8 WLCSP 56 balls with backside coating for light protection

◆ FICR_INFO_PACKAGE_PACKAGE_Msk

#define FICR_INFO_PACKAGE_PACKAGE_Msk   (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos)

Bit mask of PACKAGE field.

◆ FICR_INFO_PACKAGE_PACKAGE_Pos

#define FICR_INFO_PACKAGE_PACKAGE_Pos   (0UL)

Position of PACKAGE field.

◆ FICR_INFO_PACKAGE_PACKAGE_QF

#define FICR_INFO_PACKAGE_PACKAGE_QF   (0x2000UL)

QFxx - 48-pin QFN

◆ FICR_INFO_PACKAGE_PACKAGE_Unspecified

#define FICR_INFO_PACKAGE_PACKAGE_Unspecified   (0xFFFFFFFFUL)

Unspecified

◆ FICR_INFO_PART_PART_Msk

#define FICR_INFO_PART_PART_Msk   (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos)

Bit mask of PART field.

◆ FICR_INFO_PART_PART_N52832

#define FICR_INFO_PART_PART_N52832   (0x52832UL)

nRF52832

◆ FICR_INFO_PART_PART_Pos

#define FICR_INFO_PART_PART_Pos   (0UL)

Position of PART field.

◆ FICR_INFO_PART_PART_Unspecified

#define FICR_INFO_PART_PART_Unspecified   (0xFFFFFFFFUL)

Unspecified

◆ FICR_INFO_RAM_RAM_K16

#define FICR_INFO_RAM_RAM_K16   (0x10UL)

16 kByte RAM

◆ FICR_INFO_RAM_RAM_K32

#define FICR_INFO_RAM_RAM_K32   (0x20UL)

32 kByte RAM

◆ FICR_INFO_RAM_RAM_K64

#define FICR_INFO_RAM_RAM_K64   (0x40UL)

64 kByte RAM

◆ FICR_INFO_RAM_RAM_Msk

#define FICR_INFO_RAM_RAM_Msk   (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos)

Bit mask of RAM field.

◆ FICR_INFO_RAM_RAM_Pos

#define FICR_INFO_RAM_RAM_Pos   (0UL)

Position of RAM field.

◆ FICR_INFO_RAM_RAM_Unspecified

#define FICR_INFO_RAM_RAM_Unspecified   (0xFFFFFFFFUL)

Unspecified

◆ FICR_INFO_VARIANT_VARIANT_AAAA

#define FICR_INFO_VARIANT_VARIANT_AAAA   (0x41414141UL)

AAAA

◆ FICR_INFO_VARIANT_VARIANT_AAAB

#define FICR_INFO_VARIANT_VARIANT_AAAB   (0x41414142UL)

AAAB

◆ FICR_INFO_VARIANT_VARIANT_AAB0

#define FICR_INFO_VARIANT_VARIANT_AAB0   (0x41414230UL)

AAB0

◆ FICR_INFO_VARIANT_VARIANT_AABA

#define FICR_INFO_VARIANT_VARIANT_AABA   (0x41414241UL)

AABA

◆ FICR_INFO_VARIANT_VARIANT_AABB

#define FICR_INFO_VARIANT_VARIANT_AABB   (0x41414242UL)

AABB

◆ FICR_INFO_VARIANT_VARIANT_AAE0

#define FICR_INFO_VARIANT_VARIANT_AAE0   (0x41414530UL)

AAE0

◆ FICR_INFO_VARIANT_VARIANT_Msk

#define FICR_INFO_VARIANT_VARIANT_Msk   (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos)

Bit mask of VARIANT field.

◆ FICR_INFO_VARIANT_VARIANT_Pos

#define FICR_INFO_VARIANT_VARIANT_Pos   (0UL)

Position of VARIANT field.

◆ FICR_INFO_VARIANT_VARIANT_Unspecified

#define FICR_INFO_VARIANT_VARIANT_Unspecified   (0xFFFFFFFFUL)

Unspecified

◆ FICR_IR_IR_Msk

#define FICR_IR_IR_Msk   (0xFFFFFFFFUL << FICR_IR_IR_Pos)

Bit mask of IR field.

◆ FICR_IR_IR_Pos

#define FICR_IR_IR_Pos   (0UL)

Position of IR field.

◆ FICR_NFC_TAGHEADER0_MFGID_Msk

#define FICR_NFC_TAGHEADER0_MFGID_Msk   (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos)

Bit mask of MFGID field.

◆ FICR_NFC_TAGHEADER0_MFGID_Pos

#define FICR_NFC_TAGHEADER0_MFGID_Pos   (0UL)

Position of MFGID field.

◆ FICR_NFC_TAGHEADER0_UD1_Msk

#define FICR_NFC_TAGHEADER0_UD1_Msk   (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos)

Bit mask of UD1 field.

◆ FICR_NFC_TAGHEADER0_UD1_Pos

#define FICR_NFC_TAGHEADER0_UD1_Pos   (8UL)

Position of UD1 field.

◆ FICR_NFC_TAGHEADER0_UD2_Msk

#define FICR_NFC_TAGHEADER0_UD2_Msk   (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos)

Bit mask of UD2 field.

◆ FICR_NFC_TAGHEADER0_UD2_Pos

#define FICR_NFC_TAGHEADER0_UD2_Pos   (16UL)

Position of UD2 field.

◆ FICR_NFC_TAGHEADER0_UD3_Msk

#define FICR_NFC_TAGHEADER0_UD3_Msk   (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos)

Bit mask of UD3 field.

◆ FICR_NFC_TAGHEADER0_UD3_Pos

#define FICR_NFC_TAGHEADER0_UD3_Pos   (24UL)

Position of UD3 field.

◆ FICR_NFC_TAGHEADER1_UD4_Msk

#define FICR_NFC_TAGHEADER1_UD4_Msk   (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos)

Bit mask of UD4 field.

◆ FICR_NFC_TAGHEADER1_UD4_Pos

#define FICR_NFC_TAGHEADER1_UD4_Pos   (0UL)

Position of UD4 field.

◆ FICR_NFC_TAGHEADER1_UD5_Msk

#define FICR_NFC_TAGHEADER1_UD5_Msk   (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos)

Bit mask of UD5 field.

◆ FICR_NFC_TAGHEADER1_UD5_Pos

#define FICR_NFC_TAGHEADER1_UD5_Pos   (8UL)

Position of UD5 field.

◆ FICR_NFC_TAGHEADER1_UD6_Msk

#define FICR_NFC_TAGHEADER1_UD6_Msk   (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos)

Bit mask of UD6 field.

◆ FICR_NFC_TAGHEADER1_UD6_Pos

#define FICR_NFC_TAGHEADER1_UD6_Pos   (16UL)

Position of UD6 field.

◆ FICR_NFC_TAGHEADER1_UD7_Msk

#define FICR_NFC_TAGHEADER1_UD7_Msk   (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos)

Bit mask of UD7 field.

◆ FICR_NFC_TAGHEADER1_UD7_Pos

#define FICR_NFC_TAGHEADER1_UD7_Pos   (24UL)

Position of UD7 field.

◆ FICR_NFC_TAGHEADER2_UD10_Msk

#define FICR_NFC_TAGHEADER2_UD10_Msk   (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos)

Bit mask of UD10 field.

◆ FICR_NFC_TAGHEADER2_UD10_Pos

#define FICR_NFC_TAGHEADER2_UD10_Pos   (16UL)

Position of UD10 field.

◆ FICR_NFC_TAGHEADER2_UD11_Msk

#define FICR_NFC_TAGHEADER2_UD11_Msk   (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos)

Bit mask of UD11 field.

◆ FICR_NFC_TAGHEADER2_UD11_Pos

#define FICR_NFC_TAGHEADER2_UD11_Pos   (24UL)

Position of UD11 field.

◆ FICR_NFC_TAGHEADER2_UD8_Msk

#define FICR_NFC_TAGHEADER2_UD8_Msk   (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos)

Bit mask of UD8 field.

◆ FICR_NFC_TAGHEADER2_UD8_Pos

#define FICR_NFC_TAGHEADER2_UD8_Pos   (0UL)

Position of UD8 field.

◆ FICR_NFC_TAGHEADER2_UD9_Msk

#define FICR_NFC_TAGHEADER2_UD9_Msk   (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos)

Bit mask of UD9 field.

◆ FICR_NFC_TAGHEADER2_UD9_Pos

#define FICR_NFC_TAGHEADER2_UD9_Pos   (8UL)

Position of UD9 field.

◆ FICR_NFC_TAGHEADER3_UD12_Msk

#define FICR_NFC_TAGHEADER3_UD12_Msk   (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos)

Bit mask of UD12 field.

◆ FICR_NFC_TAGHEADER3_UD12_Pos

#define FICR_NFC_TAGHEADER3_UD12_Pos   (0UL)

Position of UD12 field.

◆ FICR_NFC_TAGHEADER3_UD13_Msk

#define FICR_NFC_TAGHEADER3_UD13_Msk   (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos)

Bit mask of UD13 field.

◆ FICR_NFC_TAGHEADER3_UD13_Pos

#define FICR_NFC_TAGHEADER3_UD13_Pos   (8UL)

Position of UD13 field.

◆ FICR_NFC_TAGHEADER3_UD14_Msk

#define FICR_NFC_TAGHEADER3_UD14_Msk   (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos)

Bit mask of UD14 field.

◆ FICR_NFC_TAGHEADER3_UD14_Pos

#define FICR_NFC_TAGHEADER3_UD14_Pos   (16UL)

Position of UD14 field.

◆ FICR_NFC_TAGHEADER3_UD15_Msk

#define FICR_NFC_TAGHEADER3_UD15_Msk   (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos)

Bit mask of UD15 field.

◆ FICR_NFC_TAGHEADER3_UD15_Pos

#define FICR_NFC_TAGHEADER3_UD15_Pos   (24UL)

Position of UD15 field.

◆ FICR_TEMP_A0_A_Msk

#define FICR_TEMP_A0_A_Msk   (0xFFFUL << FICR_TEMP_A0_A_Pos)

Bit mask of A field.

◆ FICR_TEMP_A0_A_Pos

#define FICR_TEMP_A0_A_Pos   (0UL)

Position of A field.

◆ FICR_TEMP_A1_A_Msk

#define FICR_TEMP_A1_A_Msk   (0xFFFUL << FICR_TEMP_A1_A_Pos)

Bit mask of A field.

◆ FICR_TEMP_A1_A_Pos

#define FICR_TEMP_A1_A_Pos   (0UL)

Position of A field.

◆ FICR_TEMP_A2_A_Msk

#define FICR_TEMP_A2_A_Msk   (0xFFFUL << FICR_TEMP_A2_A_Pos)

Bit mask of A field.

◆ FICR_TEMP_A2_A_Pos

#define FICR_TEMP_A2_A_Pos   (0UL)

Position of A field.

◆ FICR_TEMP_A3_A_Msk

#define FICR_TEMP_A3_A_Msk   (0xFFFUL << FICR_TEMP_A3_A_Pos)

Bit mask of A field.

◆ FICR_TEMP_A3_A_Pos

#define FICR_TEMP_A3_A_Pos   (0UL)

Position of A field.

◆ FICR_TEMP_A4_A_Msk

#define FICR_TEMP_A4_A_Msk   (0xFFFUL << FICR_TEMP_A4_A_Pos)

Bit mask of A field.

◆ FICR_TEMP_A4_A_Pos

#define FICR_TEMP_A4_A_Pos   (0UL)

Position of A field.

◆ FICR_TEMP_A5_A_Msk

#define FICR_TEMP_A5_A_Msk   (0xFFFUL << FICR_TEMP_A5_A_Pos)

Bit mask of A field.

◆ FICR_TEMP_A5_A_Pos

#define FICR_TEMP_A5_A_Pos   (0UL)

Position of A field.

◆ FICR_TEMP_B0_B_Msk

#define FICR_TEMP_B0_B_Msk   (0x3FFFUL << FICR_TEMP_B0_B_Pos)

Bit mask of B field.

◆ FICR_TEMP_B0_B_Pos

#define FICR_TEMP_B0_B_Pos   (0UL)

Position of B field.

◆ FICR_TEMP_B1_B_Msk

#define FICR_TEMP_B1_B_Msk   (0x3FFFUL << FICR_TEMP_B1_B_Pos)

Bit mask of B field.

◆ FICR_TEMP_B1_B_Pos

#define FICR_TEMP_B1_B_Pos   (0UL)

Position of B field.

◆ FICR_TEMP_B2_B_Msk

#define FICR_TEMP_B2_B_Msk   (0x3FFFUL << FICR_TEMP_B2_B_Pos)

Bit mask of B field.

◆ FICR_TEMP_B2_B_Pos

#define FICR_TEMP_B2_B_Pos   (0UL)

Position of B field.

◆ FICR_TEMP_B3_B_Msk

#define FICR_TEMP_B3_B_Msk   (0x3FFFUL << FICR_TEMP_B3_B_Pos)

Bit mask of B field.

◆ FICR_TEMP_B3_B_Pos

#define FICR_TEMP_B3_B_Pos   (0UL)

Position of B field.

◆ FICR_TEMP_B4_B_Msk

#define FICR_TEMP_B4_B_Msk   (0x3FFFUL << FICR_TEMP_B4_B_Pos)

Bit mask of B field.

◆ FICR_TEMP_B4_B_Pos

#define FICR_TEMP_B4_B_Pos   (0UL)

Position of B field.

◆ FICR_TEMP_B5_B_Msk

#define FICR_TEMP_B5_B_Msk   (0x3FFFUL << FICR_TEMP_B5_B_Pos)

Bit mask of B field.

◆ FICR_TEMP_B5_B_Pos

#define FICR_TEMP_B5_B_Pos   (0UL)

Position of B field.

◆ FICR_TEMP_T0_T_Msk

#define FICR_TEMP_T0_T_Msk   (0xFFUL << FICR_TEMP_T0_T_Pos)

Bit mask of T field.

◆ FICR_TEMP_T0_T_Pos

#define FICR_TEMP_T0_T_Pos   (0UL)

Position of T field.

◆ FICR_TEMP_T1_T_Msk

#define FICR_TEMP_T1_T_Msk   (0xFFUL << FICR_TEMP_T1_T_Pos)

Bit mask of T field.

◆ FICR_TEMP_T1_T_Pos

#define FICR_TEMP_T1_T_Pos   (0UL)

Position of T field.

◆ FICR_TEMP_T2_T_Msk

#define FICR_TEMP_T2_T_Msk   (0xFFUL << FICR_TEMP_T2_T_Pos)

Bit mask of T field.

◆ FICR_TEMP_T2_T_Pos

#define FICR_TEMP_T2_T_Pos   (0UL)

Position of T field.

◆ FICR_TEMP_T3_T_Msk

#define FICR_TEMP_T3_T_Msk   (0xFFUL << FICR_TEMP_T3_T_Pos)

Bit mask of T field.

◆ FICR_TEMP_T3_T_Pos

#define FICR_TEMP_T3_T_Pos   (0UL)

Position of T field.

◆ FICR_TEMP_T4_T_Msk

#define FICR_TEMP_T4_T_Msk   (0xFFUL << FICR_TEMP_T4_T_Pos)

Bit mask of T field.

◆ FICR_TEMP_T4_T_Pos

#define FICR_TEMP_T4_T_Pos   (0UL)

Position of T field.

◆ GPIO_DETECTMODE_DETECTMODE_Default

#define GPIO_DETECTMODE_DETECTMODE_Default   (0UL)

DETECT directly connected to PIN DETECT signals

◆ GPIO_DETECTMODE_DETECTMODE_LDETECT

#define GPIO_DETECTMODE_DETECTMODE_LDETECT   (1UL)

Use the latched LDETECT behaviour

◆ GPIO_DETECTMODE_DETECTMODE_Msk

#define GPIO_DETECTMODE_DETECTMODE_Msk   (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos)

Bit mask of DETECTMODE field.

◆ GPIO_DETECTMODE_DETECTMODE_Pos

#define GPIO_DETECTMODE_DETECTMODE_Pos   (0UL)

Position of DETECTMODE field.

◆ GPIO_DIR_PIN0_Input

#define GPIO_DIR_PIN0_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN0_Msk

#define GPIO_DIR_PIN0_Msk   (0x1UL << GPIO_DIR_PIN0_Pos)

Bit mask of PIN0 field.

◆ GPIO_DIR_PIN0_Output

#define GPIO_DIR_PIN0_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN0_Pos

#define GPIO_DIR_PIN0_Pos   (0UL)

Position of PIN0 field.

◆ GPIO_DIR_PIN10_Input

#define GPIO_DIR_PIN10_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN10_Msk

#define GPIO_DIR_PIN10_Msk   (0x1UL << GPIO_DIR_PIN10_Pos)

Bit mask of PIN10 field.

◆ GPIO_DIR_PIN10_Output

#define GPIO_DIR_PIN10_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN10_Pos

#define GPIO_DIR_PIN10_Pos   (10UL)

Position of PIN10 field.

◆ GPIO_DIR_PIN11_Input

#define GPIO_DIR_PIN11_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN11_Msk

#define GPIO_DIR_PIN11_Msk   (0x1UL << GPIO_DIR_PIN11_Pos)

Bit mask of PIN11 field.

◆ GPIO_DIR_PIN11_Output

#define GPIO_DIR_PIN11_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN11_Pos

#define GPIO_DIR_PIN11_Pos   (11UL)

Position of PIN11 field.

◆ GPIO_DIR_PIN12_Input

#define GPIO_DIR_PIN12_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN12_Msk

#define GPIO_DIR_PIN12_Msk   (0x1UL << GPIO_DIR_PIN12_Pos)

Bit mask of PIN12 field.

◆ GPIO_DIR_PIN12_Output

#define GPIO_DIR_PIN12_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN12_Pos

#define GPIO_DIR_PIN12_Pos   (12UL)

Position of PIN12 field.

◆ GPIO_DIR_PIN13_Input

#define GPIO_DIR_PIN13_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN13_Msk

#define GPIO_DIR_PIN13_Msk   (0x1UL << GPIO_DIR_PIN13_Pos)

Bit mask of PIN13 field.

◆ GPIO_DIR_PIN13_Output

#define GPIO_DIR_PIN13_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN13_Pos

#define GPIO_DIR_PIN13_Pos   (13UL)

Position of PIN13 field.

◆ GPIO_DIR_PIN14_Input

#define GPIO_DIR_PIN14_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN14_Msk

#define GPIO_DIR_PIN14_Msk   (0x1UL << GPIO_DIR_PIN14_Pos)

Bit mask of PIN14 field.

◆ GPIO_DIR_PIN14_Output

#define GPIO_DIR_PIN14_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN14_Pos

#define GPIO_DIR_PIN14_Pos   (14UL)

Position of PIN14 field.

◆ GPIO_DIR_PIN15_Input

#define GPIO_DIR_PIN15_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN15_Msk

#define GPIO_DIR_PIN15_Msk   (0x1UL << GPIO_DIR_PIN15_Pos)

Bit mask of PIN15 field.

◆ GPIO_DIR_PIN15_Output

#define GPIO_DIR_PIN15_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN15_Pos

#define GPIO_DIR_PIN15_Pos   (15UL)

Position of PIN15 field.

◆ GPIO_DIR_PIN16_Input

#define GPIO_DIR_PIN16_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN16_Msk

#define GPIO_DIR_PIN16_Msk   (0x1UL << GPIO_DIR_PIN16_Pos)

Bit mask of PIN16 field.

◆ GPIO_DIR_PIN16_Output

#define GPIO_DIR_PIN16_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN16_Pos

#define GPIO_DIR_PIN16_Pos   (16UL)

Position of PIN16 field.

◆ GPIO_DIR_PIN17_Input

#define GPIO_DIR_PIN17_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN17_Msk

#define GPIO_DIR_PIN17_Msk   (0x1UL << GPIO_DIR_PIN17_Pos)

Bit mask of PIN17 field.

◆ GPIO_DIR_PIN17_Output

#define GPIO_DIR_PIN17_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN17_Pos

#define GPIO_DIR_PIN17_Pos   (17UL)

Position of PIN17 field.

◆ GPIO_DIR_PIN18_Input

#define GPIO_DIR_PIN18_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN18_Msk

#define GPIO_DIR_PIN18_Msk   (0x1UL << GPIO_DIR_PIN18_Pos)

Bit mask of PIN18 field.

◆ GPIO_DIR_PIN18_Output

#define GPIO_DIR_PIN18_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN18_Pos

#define GPIO_DIR_PIN18_Pos   (18UL)

Position of PIN18 field.

◆ GPIO_DIR_PIN19_Input

#define GPIO_DIR_PIN19_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN19_Msk

#define GPIO_DIR_PIN19_Msk   (0x1UL << GPIO_DIR_PIN19_Pos)

Bit mask of PIN19 field.

◆ GPIO_DIR_PIN19_Output

#define GPIO_DIR_PIN19_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN19_Pos

#define GPIO_DIR_PIN19_Pos   (19UL)

Position of PIN19 field.

◆ GPIO_DIR_PIN1_Input

#define GPIO_DIR_PIN1_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN1_Msk

#define GPIO_DIR_PIN1_Msk   (0x1UL << GPIO_DIR_PIN1_Pos)

Bit mask of PIN1 field.

◆ GPIO_DIR_PIN1_Output

#define GPIO_DIR_PIN1_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN1_Pos

#define GPIO_DIR_PIN1_Pos   (1UL)

Position of PIN1 field.

◆ GPIO_DIR_PIN20_Input

#define GPIO_DIR_PIN20_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN20_Msk

#define GPIO_DIR_PIN20_Msk   (0x1UL << GPIO_DIR_PIN20_Pos)

Bit mask of PIN20 field.

◆ GPIO_DIR_PIN20_Output

#define GPIO_DIR_PIN20_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN20_Pos

#define GPIO_DIR_PIN20_Pos   (20UL)

Position of PIN20 field.

◆ GPIO_DIR_PIN21_Input

#define GPIO_DIR_PIN21_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN21_Msk

#define GPIO_DIR_PIN21_Msk   (0x1UL << GPIO_DIR_PIN21_Pos)

Bit mask of PIN21 field.

◆ GPIO_DIR_PIN21_Output

#define GPIO_DIR_PIN21_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN21_Pos

#define GPIO_DIR_PIN21_Pos   (21UL)

Position of PIN21 field.

◆ GPIO_DIR_PIN22_Input

#define GPIO_DIR_PIN22_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN22_Msk

#define GPIO_DIR_PIN22_Msk   (0x1UL << GPIO_DIR_PIN22_Pos)

Bit mask of PIN22 field.

◆ GPIO_DIR_PIN22_Output

#define GPIO_DIR_PIN22_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN22_Pos

#define GPIO_DIR_PIN22_Pos   (22UL)

Position of PIN22 field.

◆ GPIO_DIR_PIN23_Input

#define GPIO_DIR_PIN23_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN23_Msk

#define GPIO_DIR_PIN23_Msk   (0x1UL << GPIO_DIR_PIN23_Pos)

Bit mask of PIN23 field.

◆ GPIO_DIR_PIN23_Output

#define GPIO_DIR_PIN23_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN23_Pos

#define GPIO_DIR_PIN23_Pos   (23UL)

Position of PIN23 field.

◆ GPIO_DIR_PIN24_Input

#define GPIO_DIR_PIN24_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN24_Msk

#define GPIO_DIR_PIN24_Msk   (0x1UL << GPIO_DIR_PIN24_Pos)

Bit mask of PIN24 field.

◆ GPIO_DIR_PIN24_Output

#define GPIO_DIR_PIN24_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN24_Pos

#define GPIO_DIR_PIN24_Pos   (24UL)

Position of PIN24 field.

◆ GPIO_DIR_PIN25_Input

#define GPIO_DIR_PIN25_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN25_Msk

#define GPIO_DIR_PIN25_Msk   (0x1UL << GPIO_DIR_PIN25_Pos)

Bit mask of PIN25 field.

◆ GPIO_DIR_PIN25_Output

#define GPIO_DIR_PIN25_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN25_Pos

#define GPIO_DIR_PIN25_Pos   (25UL)

Position of PIN25 field.

◆ GPIO_DIR_PIN26_Input

#define GPIO_DIR_PIN26_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN26_Msk

#define GPIO_DIR_PIN26_Msk   (0x1UL << GPIO_DIR_PIN26_Pos)

Bit mask of PIN26 field.

◆ GPIO_DIR_PIN26_Output

#define GPIO_DIR_PIN26_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN26_Pos

#define GPIO_DIR_PIN26_Pos   (26UL)

Position of PIN26 field.

◆ GPIO_DIR_PIN27_Input

#define GPIO_DIR_PIN27_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN27_Msk

#define GPIO_DIR_PIN27_Msk   (0x1UL << GPIO_DIR_PIN27_Pos)

Bit mask of PIN27 field.

◆ GPIO_DIR_PIN27_Output

#define GPIO_DIR_PIN27_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN27_Pos

#define GPIO_DIR_PIN27_Pos   (27UL)

Position of PIN27 field.

◆ GPIO_DIR_PIN28_Input

#define GPIO_DIR_PIN28_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN28_Msk

#define GPIO_DIR_PIN28_Msk   (0x1UL << GPIO_DIR_PIN28_Pos)

Bit mask of PIN28 field.

◆ GPIO_DIR_PIN28_Output

#define GPIO_DIR_PIN28_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN28_Pos

#define GPIO_DIR_PIN28_Pos   (28UL)

Position of PIN28 field.

◆ GPIO_DIR_PIN29_Input

#define GPIO_DIR_PIN29_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN29_Msk

#define GPIO_DIR_PIN29_Msk   (0x1UL << GPIO_DIR_PIN29_Pos)

Bit mask of PIN29 field.

◆ GPIO_DIR_PIN29_Output

#define GPIO_DIR_PIN29_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN29_Pos

#define GPIO_DIR_PIN29_Pos   (29UL)

Position of PIN29 field.

◆ GPIO_DIR_PIN2_Input

#define GPIO_DIR_PIN2_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN2_Msk

#define GPIO_DIR_PIN2_Msk   (0x1UL << GPIO_DIR_PIN2_Pos)

Bit mask of PIN2 field.

◆ GPIO_DIR_PIN2_Output

#define GPIO_DIR_PIN2_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN2_Pos

#define GPIO_DIR_PIN2_Pos   (2UL)

Position of PIN2 field.

◆ GPIO_DIR_PIN30_Input

#define GPIO_DIR_PIN30_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN30_Msk

#define GPIO_DIR_PIN30_Msk   (0x1UL << GPIO_DIR_PIN30_Pos)

Bit mask of PIN30 field.

◆ GPIO_DIR_PIN30_Output

#define GPIO_DIR_PIN30_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN30_Pos

#define GPIO_DIR_PIN30_Pos   (30UL)

Position of PIN30 field.

◆ GPIO_DIR_PIN31_Input

#define GPIO_DIR_PIN31_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN31_Msk

#define GPIO_DIR_PIN31_Msk   (0x1UL << GPIO_DIR_PIN31_Pos)

Bit mask of PIN31 field.

◆ GPIO_DIR_PIN31_Output

#define GPIO_DIR_PIN31_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN31_Pos

#define GPIO_DIR_PIN31_Pos   (31UL)

Position of PIN31 field.

◆ GPIO_DIR_PIN3_Input

#define GPIO_DIR_PIN3_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN3_Msk

#define GPIO_DIR_PIN3_Msk   (0x1UL << GPIO_DIR_PIN3_Pos)

Bit mask of PIN3 field.

◆ GPIO_DIR_PIN3_Output

#define GPIO_DIR_PIN3_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN3_Pos

#define GPIO_DIR_PIN3_Pos   (3UL)

Position of PIN3 field.

◆ GPIO_DIR_PIN4_Input

#define GPIO_DIR_PIN4_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN4_Msk

#define GPIO_DIR_PIN4_Msk   (0x1UL << GPIO_DIR_PIN4_Pos)

Bit mask of PIN4 field.

◆ GPIO_DIR_PIN4_Output

#define GPIO_DIR_PIN4_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN4_Pos

#define GPIO_DIR_PIN4_Pos   (4UL)

Position of PIN4 field.

◆ GPIO_DIR_PIN5_Input

#define GPIO_DIR_PIN5_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN5_Msk

#define GPIO_DIR_PIN5_Msk   (0x1UL << GPIO_DIR_PIN5_Pos)

Bit mask of PIN5 field.

◆ GPIO_DIR_PIN5_Output

#define GPIO_DIR_PIN5_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN5_Pos

#define GPIO_DIR_PIN5_Pos   (5UL)

Position of PIN5 field.

◆ GPIO_DIR_PIN6_Input

#define GPIO_DIR_PIN6_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN6_Msk

#define GPIO_DIR_PIN6_Msk   (0x1UL << GPIO_DIR_PIN6_Pos)

Bit mask of PIN6 field.

◆ GPIO_DIR_PIN6_Output

#define GPIO_DIR_PIN6_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN6_Pos

#define GPIO_DIR_PIN6_Pos   (6UL)

Position of PIN6 field.

◆ GPIO_DIR_PIN7_Input

#define GPIO_DIR_PIN7_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN7_Msk

#define GPIO_DIR_PIN7_Msk   (0x1UL << GPIO_DIR_PIN7_Pos)

Bit mask of PIN7 field.

◆ GPIO_DIR_PIN7_Output

#define GPIO_DIR_PIN7_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN7_Pos

#define GPIO_DIR_PIN7_Pos   (7UL)

Position of PIN7 field.

◆ GPIO_DIR_PIN8_Input

#define GPIO_DIR_PIN8_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN8_Msk

#define GPIO_DIR_PIN8_Msk   (0x1UL << GPIO_DIR_PIN8_Pos)

Bit mask of PIN8 field.

◆ GPIO_DIR_PIN8_Output

#define GPIO_DIR_PIN8_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN8_Pos

#define GPIO_DIR_PIN8_Pos   (8UL)

Position of PIN8 field.

◆ GPIO_DIR_PIN9_Input

#define GPIO_DIR_PIN9_Input   (0UL)

Pin set as input

◆ GPIO_DIR_PIN9_Msk

#define GPIO_DIR_PIN9_Msk   (0x1UL << GPIO_DIR_PIN9_Pos)

Bit mask of PIN9 field.

◆ GPIO_DIR_PIN9_Output

#define GPIO_DIR_PIN9_Output   (1UL)

Pin set as output

◆ GPIO_DIR_PIN9_Pos

#define GPIO_DIR_PIN9_Pos   (9UL)

Position of PIN9 field.

◆ GPIO_DIRCLR_PIN0_Clear

#define GPIO_DIRCLR_PIN0_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN0_Input

#define GPIO_DIRCLR_PIN0_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN0_Msk

#define GPIO_DIRCLR_PIN0_Msk   (0x1UL << GPIO_DIRCLR_PIN0_Pos)

Bit mask of PIN0 field.

◆ GPIO_DIRCLR_PIN0_Output

#define GPIO_DIRCLR_PIN0_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN0_Pos

#define GPIO_DIRCLR_PIN0_Pos   (0UL)

Position of PIN0 field.

◆ GPIO_DIRCLR_PIN10_Clear

#define GPIO_DIRCLR_PIN10_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN10_Input

#define GPIO_DIRCLR_PIN10_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN10_Msk

#define GPIO_DIRCLR_PIN10_Msk   (0x1UL << GPIO_DIRCLR_PIN10_Pos)

Bit mask of PIN10 field.

◆ GPIO_DIRCLR_PIN10_Output

#define GPIO_DIRCLR_PIN10_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN10_Pos

#define GPIO_DIRCLR_PIN10_Pos   (10UL)

Position of PIN10 field.

◆ GPIO_DIRCLR_PIN11_Clear

#define GPIO_DIRCLR_PIN11_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN11_Input

#define GPIO_DIRCLR_PIN11_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN11_Msk

#define GPIO_DIRCLR_PIN11_Msk   (0x1UL << GPIO_DIRCLR_PIN11_Pos)

Bit mask of PIN11 field.

◆ GPIO_DIRCLR_PIN11_Output

#define GPIO_DIRCLR_PIN11_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN11_Pos

#define GPIO_DIRCLR_PIN11_Pos   (11UL)

Position of PIN11 field.

◆ GPIO_DIRCLR_PIN12_Clear

#define GPIO_DIRCLR_PIN12_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN12_Input

#define GPIO_DIRCLR_PIN12_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN12_Msk

#define GPIO_DIRCLR_PIN12_Msk   (0x1UL << GPIO_DIRCLR_PIN12_Pos)

Bit mask of PIN12 field.

◆ GPIO_DIRCLR_PIN12_Output

#define GPIO_DIRCLR_PIN12_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN12_Pos

#define GPIO_DIRCLR_PIN12_Pos   (12UL)

Position of PIN12 field.

◆ GPIO_DIRCLR_PIN13_Clear

#define GPIO_DIRCLR_PIN13_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN13_Input

#define GPIO_DIRCLR_PIN13_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN13_Msk

#define GPIO_DIRCLR_PIN13_Msk   (0x1UL << GPIO_DIRCLR_PIN13_Pos)

Bit mask of PIN13 field.

◆ GPIO_DIRCLR_PIN13_Output

#define GPIO_DIRCLR_PIN13_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN13_Pos

#define GPIO_DIRCLR_PIN13_Pos   (13UL)

Position of PIN13 field.

◆ GPIO_DIRCLR_PIN14_Clear

#define GPIO_DIRCLR_PIN14_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN14_Input

#define GPIO_DIRCLR_PIN14_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN14_Msk

#define GPIO_DIRCLR_PIN14_Msk   (0x1UL << GPIO_DIRCLR_PIN14_Pos)

Bit mask of PIN14 field.

◆ GPIO_DIRCLR_PIN14_Output

#define GPIO_DIRCLR_PIN14_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN14_Pos

#define GPIO_DIRCLR_PIN14_Pos   (14UL)

Position of PIN14 field.

◆ GPIO_DIRCLR_PIN15_Clear

#define GPIO_DIRCLR_PIN15_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN15_Input

#define GPIO_DIRCLR_PIN15_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN15_Msk

#define GPIO_DIRCLR_PIN15_Msk   (0x1UL << GPIO_DIRCLR_PIN15_Pos)

Bit mask of PIN15 field.

◆ GPIO_DIRCLR_PIN15_Output

#define GPIO_DIRCLR_PIN15_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN15_Pos

#define GPIO_DIRCLR_PIN15_Pos   (15UL)

Position of PIN15 field.

◆ GPIO_DIRCLR_PIN16_Clear

#define GPIO_DIRCLR_PIN16_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN16_Input

#define GPIO_DIRCLR_PIN16_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN16_Msk

#define GPIO_DIRCLR_PIN16_Msk   (0x1UL << GPIO_DIRCLR_PIN16_Pos)

Bit mask of PIN16 field.

◆ GPIO_DIRCLR_PIN16_Output

#define GPIO_DIRCLR_PIN16_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN16_Pos

#define GPIO_DIRCLR_PIN16_Pos   (16UL)

Position of PIN16 field.

◆ GPIO_DIRCLR_PIN17_Clear

#define GPIO_DIRCLR_PIN17_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN17_Input

#define GPIO_DIRCLR_PIN17_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN17_Msk

#define GPIO_DIRCLR_PIN17_Msk   (0x1UL << GPIO_DIRCLR_PIN17_Pos)

Bit mask of PIN17 field.

◆ GPIO_DIRCLR_PIN17_Output

#define GPIO_DIRCLR_PIN17_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN17_Pos

#define GPIO_DIRCLR_PIN17_Pos   (17UL)

Position of PIN17 field.

◆ GPIO_DIRCLR_PIN18_Clear

#define GPIO_DIRCLR_PIN18_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN18_Input

#define GPIO_DIRCLR_PIN18_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN18_Msk

#define GPIO_DIRCLR_PIN18_Msk   (0x1UL << GPIO_DIRCLR_PIN18_Pos)

Bit mask of PIN18 field.

◆ GPIO_DIRCLR_PIN18_Output

#define GPIO_DIRCLR_PIN18_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN18_Pos

#define GPIO_DIRCLR_PIN18_Pos   (18UL)

Position of PIN18 field.

◆ GPIO_DIRCLR_PIN19_Clear

#define GPIO_DIRCLR_PIN19_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN19_Input

#define GPIO_DIRCLR_PIN19_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN19_Msk

#define GPIO_DIRCLR_PIN19_Msk   (0x1UL << GPIO_DIRCLR_PIN19_Pos)

Bit mask of PIN19 field.

◆ GPIO_DIRCLR_PIN19_Output

#define GPIO_DIRCLR_PIN19_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN19_Pos

#define GPIO_DIRCLR_PIN19_Pos   (19UL)

Position of PIN19 field.

◆ GPIO_DIRCLR_PIN1_Clear

#define GPIO_DIRCLR_PIN1_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN1_Input

#define GPIO_DIRCLR_PIN1_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN1_Msk

#define GPIO_DIRCLR_PIN1_Msk   (0x1UL << GPIO_DIRCLR_PIN1_Pos)

Bit mask of PIN1 field.

◆ GPIO_DIRCLR_PIN1_Output

#define GPIO_DIRCLR_PIN1_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN1_Pos

#define GPIO_DIRCLR_PIN1_Pos   (1UL)

Position of PIN1 field.

◆ GPIO_DIRCLR_PIN20_Clear

#define GPIO_DIRCLR_PIN20_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN20_Input

#define GPIO_DIRCLR_PIN20_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN20_Msk

#define GPIO_DIRCLR_PIN20_Msk   (0x1UL << GPIO_DIRCLR_PIN20_Pos)

Bit mask of PIN20 field.

◆ GPIO_DIRCLR_PIN20_Output

#define GPIO_DIRCLR_PIN20_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN20_Pos

#define GPIO_DIRCLR_PIN20_Pos   (20UL)

Position of PIN20 field.

◆ GPIO_DIRCLR_PIN21_Clear

#define GPIO_DIRCLR_PIN21_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN21_Input

#define GPIO_DIRCLR_PIN21_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN21_Msk

#define GPIO_DIRCLR_PIN21_Msk   (0x1UL << GPIO_DIRCLR_PIN21_Pos)

Bit mask of PIN21 field.

◆ GPIO_DIRCLR_PIN21_Output

#define GPIO_DIRCLR_PIN21_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN21_Pos

#define GPIO_DIRCLR_PIN21_Pos   (21UL)

Position of PIN21 field.

◆ GPIO_DIRCLR_PIN22_Clear

#define GPIO_DIRCLR_PIN22_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN22_Input

#define GPIO_DIRCLR_PIN22_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN22_Msk

#define GPIO_DIRCLR_PIN22_Msk   (0x1UL << GPIO_DIRCLR_PIN22_Pos)

Bit mask of PIN22 field.

◆ GPIO_DIRCLR_PIN22_Output

#define GPIO_DIRCLR_PIN22_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN22_Pos

#define GPIO_DIRCLR_PIN22_Pos   (22UL)

Position of PIN22 field.

◆ GPIO_DIRCLR_PIN23_Clear

#define GPIO_DIRCLR_PIN23_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN23_Input

#define GPIO_DIRCLR_PIN23_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN23_Msk

#define GPIO_DIRCLR_PIN23_Msk   (0x1UL << GPIO_DIRCLR_PIN23_Pos)

Bit mask of PIN23 field.

◆ GPIO_DIRCLR_PIN23_Output

#define GPIO_DIRCLR_PIN23_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN23_Pos

#define GPIO_DIRCLR_PIN23_Pos   (23UL)

Position of PIN23 field.

◆ GPIO_DIRCLR_PIN24_Clear

#define GPIO_DIRCLR_PIN24_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN24_Input

#define GPIO_DIRCLR_PIN24_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN24_Msk

#define GPIO_DIRCLR_PIN24_Msk   (0x1UL << GPIO_DIRCLR_PIN24_Pos)

Bit mask of PIN24 field.

◆ GPIO_DIRCLR_PIN24_Output

#define GPIO_DIRCLR_PIN24_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN24_Pos

#define GPIO_DIRCLR_PIN24_Pos   (24UL)

Position of PIN24 field.

◆ GPIO_DIRCLR_PIN25_Clear

#define GPIO_DIRCLR_PIN25_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN25_Input

#define GPIO_DIRCLR_PIN25_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN25_Msk

#define GPIO_DIRCLR_PIN25_Msk   (0x1UL << GPIO_DIRCLR_PIN25_Pos)

Bit mask of PIN25 field.

◆ GPIO_DIRCLR_PIN25_Output

#define GPIO_DIRCLR_PIN25_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN25_Pos

#define GPIO_DIRCLR_PIN25_Pos   (25UL)

Position of PIN25 field.

◆ GPIO_DIRCLR_PIN26_Clear

#define GPIO_DIRCLR_PIN26_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN26_Input

#define GPIO_DIRCLR_PIN26_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN26_Msk

#define GPIO_DIRCLR_PIN26_Msk   (0x1UL << GPIO_DIRCLR_PIN26_Pos)

Bit mask of PIN26 field.

◆ GPIO_DIRCLR_PIN26_Output

#define GPIO_DIRCLR_PIN26_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN26_Pos

#define GPIO_DIRCLR_PIN26_Pos   (26UL)

Position of PIN26 field.

◆ GPIO_DIRCLR_PIN27_Clear

#define GPIO_DIRCLR_PIN27_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN27_Input

#define GPIO_DIRCLR_PIN27_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN27_Msk

#define GPIO_DIRCLR_PIN27_Msk   (0x1UL << GPIO_DIRCLR_PIN27_Pos)

Bit mask of PIN27 field.

◆ GPIO_DIRCLR_PIN27_Output

#define GPIO_DIRCLR_PIN27_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN27_Pos

#define GPIO_DIRCLR_PIN27_Pos   (27UL)

Position of PIN27 field.

◆ GPIO_DIRCLR_PIN28_Clear

#define GPIO_DIRCLR_PIN28_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN28_Input

#define GPIO_DIRCLR_PIN28_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN28_Msk

#define GPIO_DIRCLR_PIN28_Msk   (0x1UL << GPIO_DIRCLR_PIN28_Pos)

Bit mask of PIN28 field.

◆ GPIO_DIRCLR_PIN28_Output

#define GPIO_DIRCLR_PIN28_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN28_Pos

#define GPIO_DIRCLR_PIN28_Pos   (28UL)

Position of PIN28 field.

◆ GPIO_DIRCLR_PIN29_Clear

#define GPIO_DIRCLR_PIN29_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN29_Input

#define GPIO_DIRCLR_PIN29_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN29_Msk

#define GPIO_DIRCLR_PIN29_Msk   (0x1UL << GPIO_DIRCLR_PIN29_Pos)

Bit mask of PIN29 field.

◆ GPIO_DIRCLR_PIN29_Output

#define GPIO_DIRCLR_PIN29_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN29_Pos

#define GPIO_DIRCLR_PIN29_Pos   (29UL)

Position of PIN29 field.

◆ GPIO_DIRCLR_PIN2_Clear

#define GPIO_DIRCLR_PIN2_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN2_Input

#define GPIO_DIRCLR_PIN2_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN2_Msk

#define GPIO_DIRCLR_PIN2_Msk   (0x1UL << GPIO_DIRCLR_PIN2_Pos)

Bit mask of PIN2 field.

◆ GPIO_DIRCLR_PIN2_Output

#define GPIO_DIRCLR_PIN2_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN2_Pos

#define GPIO_DIRCLR_PIN2_Pos   (2UL)

Position of PIN2 field.

◆ GPIO_DIRCLR_PIN30_Clear

#define GPIO_DIRCLR_PIN30_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN30_Input

#define GPIO_DIRCLR_PIN30_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN30_Msk

#define GPIO_DIRCLR_PIN30_Msk   (0x1UL << GPIO_DIRCLR_PIN30_Pos)

Bit mask of PIN30 field.

◆ GPIO_DIRCLR_PIN30_Output

#define GPIO_DIRCLR_PIN30_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN30_Pos

#define GPIO_DIRCLR_PIN30_Pos   (30UL)

Position of PIN30 field.

◆ GPIO_DIRCLR_PIN31_Clear

#define GPIO_DIRCLR_PIN31_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN31_Input

#define GPIO_DIRCLR_PIN31_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN31_Msk

#define GPIO_DIRCLR_PIN31_Msk   (0x1UL << GPIO_DIRCLR_PIN31_Pos)

Bit mask of PIN31 field.

◆ GPIO_DIRCLR_PIN31_Output

#define GPIO_DIRCLR_PIN31_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN31_Pos

#define GPIO_DIRCLR_PIN31_Pos   (31UL)

Position of PIN31 field.

◆ GPIO_DIRCLR_PIN3_Clear

#define GPIO_DIRCLR_PIN3_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN3_Input

#define GPIO_DIRCLR_PIN3_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN3_Msk

#define GPIO_DIRCLR_PIN3_Msk   (0x1UL << GPIO_DIRCLR_PIN3_Pos)

Bit mask of PIN3 field.

◆ GPIO_DIRCLR_PIN3_Output

#define GPIO_DIRCLR_PIN3_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN3_Pos

#define GPIO_DIRCLR_PIN3_Pos   (3UL)

Position of PIN3 field.

◆ GPIO_DIRCLR_PIN4_Clear

#define GPIO_DIRCLR_PIN4_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN4_Input

#define GPIO_DIRCLR_PIN4_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN4_Msk

#define GPIO_DIRCLR_PIN4_Msk   (0x1UL << GPIO_DIRCLR_PIN4_Pos)

Bit mask of PIN4 field.

◆ GPIO_DIRCLR_PIN4_Output

#define GPIO_DIRCLR_PIN4_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN4_Pos

#define GPIO_DIRCLR_PIN4_Pos   (4UL)

Position of PIN4 field.

◆ GPIO_DIRCLR_PIN5_Clear

#define GPIO_DIRCLR_PIN5_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN5_Input

#define GPIO_DIRCLR_PIN5_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN5_Msk

#define GPIO_DIRCLR_PIN5_Msk   (0x1UL << GPIO_DIRCLR_PIN5_Pos)

Bit mask of PIN5 field.

◆ GPIO_DIRCLR_PIN5_Output

#define GPIO_DIRCLR_PIN5_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN5_Pos

#define GPIO_DIRCLR_PIN5_Pos   (5UL)

Position of PIN5 field.

◆ GPIO_DIRCLR_PIN6_Clear

#define GPIO_DIRCLR_PIN6_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN6_Input

#define GPIO_DIRCLR_PIN6_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN6_Msk

#define GPIO_DIRCLR_PIN6_Msk   (0x1UL << GPIO_DIRCLR_PIN6_Pos)

Bit mask of PIN6 field.

◆ GPIO_DIRCLR_PIN6_Output

#define GPIO_DIRCLR_PIN6_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN6_Pos

#define GPIO_DIRCLR_PIN6_Pos   (6UL)

Position of PIN6 field.

◆ GPIO_DIRCLR_PIN7_Clear

#define GPIO_DIRCLR_PIN7_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN7_Input

#define GPIO_DIRCLR_PIN7_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN7_Msk

#define GPIO_DIRCLR_PIN7_Msk   (0x1UL << GPIO_DIRCLR_PIN7_Pos)

Bit mask of PIN7 field.

◆ GPIO_DIRCLR_PIN7_Output

#define GPIO_DIRCLR_PIN7_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN7_Pos

#define GPIO_DIRCLR_PIN7_Pos   (7UL)

Position of PIN7 field.

◆ GPIO_DIRCLR_PIN8_Clear

#define GPIO_DIRCLR_PIN8_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN8_Input

#define GPIO_DIRCLR_PIN8_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN8_Msk

#define GPIO_DIRCLR_PIN8_Msk   (0x1UL << GPIO_DIRCLR_PIN8_Pos)

Bit mask of PIN8 field.

◆ GPIO_DIRCLR_PIN8_Output

#define GPIO_DIRCLR_PIN8_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN8_Pos

#define GPIO_DIRCLR_PIN8_Pos   (8UL)

Position of PIN8 field.

◆ GPIO_DIRCLR_PIN9_Clear

#define GPIO_DIRCLR_PIN9_Clear   (1UL)

Write: writing a '1' sets pin to input; writing a '0' has no effect

◆ GPIO_DIRCLR_PIN9_Input

#define GPIO_DIRCLR_PIN9_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRCLR_PIN9_Msk

#define GPIO_DIRCLR_PIN9_Msk   (0x1UL << GPIO_DIRCLR_PIN9_Pos)

Bit mask of PIN9 field.

◆ GPIO_DIRCLR_PIN9_Output

#define GPIO_DIRCLR_PIN9_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRCLR_PIN9_Pos

#define GPIO_DIRCLR_PIN9_Pos   (9UL)

Position of PIN9 field.

◆ GPIO_DIRSET_PIN0_Input

#define GPIO_DIRSET_PIN0_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN0_Msk

#define GPIO_DIRSET_PIN0_Msk   (0x1UL << GPIO_DIRSET_PIN0_Pos)

Bit mask of PIN0 field.

◆ GPIO_DIRSET_PIN0_Output

#define GPIO_DIRSET_PIN0_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN0_Pos

#define GPIO_DIRSET_PIN0_Pos   (0UL)

Position of PIN0 field.

◆ GPIO_DIRSET_PIN0_Set

#define GPIO_DIRSET_PIN0_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN10_Input

#define GPIO_DIRSET_PIN10_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN10_Msk

#define GPIO_DIRSET_PIN10_Msk   (0x1UL << GPIO_DIRSET_PIN10_Pos)

Bit mask of PIN10 field.

◆ GPIO_DIRSET_PIN10_Output

#define GPIO_DIRSET_PIN10_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN10_Pos

#define GPIO_DIRSET_PIN10_Pos   (10UL)

Position of PIN10 field.

◆ GPIO_DIRSET_PIN10_Set

#define GPIO_DIRSET_PIN10_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN11_Input

#define GPIO_DIRSET_PIN11_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN11_Msk

#define GPIO_DIRSET_PIN11_Msk   (0x1UL << GPIO_DIRSET_PIN11_Pos)

Bit mask of PIN11 field.

◆ GPIO_DIRSET_PIN11_Output

#define GPIO_DIRSET_PIN11_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN11_Pos

#define GPIO_DIRSET_PIN11_Pos   (11UL)

Position of PIN11 field.

◆ GPIO_DIRSET_PIN11_Set

#define GPIO_DIRSET_PIN11_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN12_Input

#define GPIO_DIRSET_PIN12_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN12_Msk

#define GPIO_DIRSET_PIN12_Msk   (0x1UL << GPIO_DIRSET_PIN12_Pos)

Bit mask of PIN12 field.

◆ GPIO_DIRSET_PIN12_Output

#define GPIO_DIRSET_PIN12_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN12_Pos

#define GPIO_DIRSET_PIN12_Pos   (12UL)

Position of PIN12 field.

◆ GPIO_DIRSET_PIN12_Set

#define GPIO_DIRSET_PIN12_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN13_Input

#define GPIO_DIRSET_PIN13_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN13_Msk

#define GPIO_DIRSET_PIN13_Msk   (0x1UL << GPIO_DIRSET_PIN13_Pos)

Bit mask of PIN13 field.

◆ GPIO_DIRSET_PIN13_Output

#define GPIO_DIRSET_PIN13_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN13_Pos

#define GPIO_DIRSET_PIN13_Pos   (13UL)

Position of PIN13 field.

◆ GPIO_DIRSET_PIN13_Set

#define GPIO_DIRSET_PIN13_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN14_Input

#define GPIO_DIRSET_PIN14_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN14_Msk

#define GPIO_DIRSET_PIN14_Msk   (0x1UL << GPIO_DIRSET_PIN14_Pos)

Bit mask of PIN14 field.

◆ GPIO_DIRSET_PIN14_Output

#define GPIO_DIRSET_PIN14_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN14_Pos

#define GPIO_DIRSET_PIN14_Pos   (14UL)

Position of PIN14 field.

◆ GPIO_DIRSET_PIN14_Set

#define GPIO_DIRSET_PIN14_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN15_Input

#define GPIO_DIRSET_PIN15_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN15_Msk

#define GPIO_DIRSET_PIN15_Msk   (0x1UL << GPIO_DIRSET_PIN15_Pos)

Bit mask of PIN15 field.

◆ GPIO_DIRSET_PIN15_Output

#define GPIO_DIRSET_PIN15_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN15_Pos

#define GPIO_DIRSET_PIN15_Pos   (15UL)

Position of PIN15 field.

◆ GPIO_DIRSET_PIN15_Set

#define GPIO_DIRSET_PIN15_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN16_Input

#define GPIO_DIRSET_PIN16_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN16_Msk

#define GPIO_DIRSET_PIN16_Msk   (0x1UL << GPIO_DIRSET_PIN16_Pos)

Bit mask of PIN16 field.

◆ GPIO_DIRSET_PIN16_Output

#define GPIO_DIRSET_PIN16_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN16_Pos

#define GPIO_DIRSET_PIN16_Pos   (16UL)

Position of PIN16 field.

◆ GPIO_DIRSET_PIN16_Set

#define GPIO_DIRSET_PIN16_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN17_Input

#define GPIO_DIRSET_PIN17_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN17_Msk

#define GPIO_DIRSET_PIN17_Msk   (0x1UL << GPIO_DIRSET_PIN17_Pos)

Bit mask of PIN17 field.

◆ GPIO_DIRSET_PIN17_Output

#define GPIO_DIRSET_PIN17_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN17_Pos

#define GPIO_DIRSET_PIN17_Pos   (17UL)

Position of PIN17 field.

◆ GPIO_DIRSET_PIN17_Set

#define GPIO_DIRSET_PIN17_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN18_Input

#define GPIO_DIRSET_PIN18_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN18_Msk

#define GPIO_DIRSET_PIN18_Msk   (0x1UL << GPIO_DIRSET_PIN18_Pos)

Bit mask of PIN18 field.

◆ GPIO_DIRSET_PIN18_Output

#define GPIO_DIRSET_PIN18_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN18_Pos

#define GPIO_DIRSET_PIN18_Pos   (18UL)

Position of PIN18 field.

◆ GPIO_DIRSET_PIN18_Set

#define GPIO_DIRSET_PIN18_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN19_Input

#define GPIO_DIRSET_PIN19_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN19_Msk

#define GPIO_DIRSET_PIN19_Msk   (0x1UL << GPIO_DIRSET_PIN19_Pos)

Bit mask of PIN19 field.

◆ GPIO_DIRSET_PIN19_Output

#define GPIO_DIRSET_PIN19_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN19_Pos

#define GPIO_DIRSET_PIN19_Pos   (19UL)

Position of PIN19 field.

◆ GPIO_DIRSET_PIN19_Set

#define GPIO_DIRSET_PIN19_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN1_Input

#define GPIO_DIRSET_PIN1_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN1_Msk

#define GPIO_DIRSET_PIN1_Msk   (0x1UL << GPIO_DIRSET_PIN1_Pos)

Bit mask of PIN1 field.

◆ GPIO_DIRSET_PIN1_Output

#define GPIO_DIRSET_PIN1_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN1_Pos

#define GPIO_DIRSET_PIN1_Pos   (1UL)

Position of PIN1 field.

◆ GPIO_DIRSET_PIN1_Set

#define GPIO_DIRSET_PIN1_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN20_Input

#define GPIO_DIRSET_PIN20_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN20_Msk

#define GPIO_DIRSET_PIN20_Msk   (0x1UL << GPIO_DIRSET_PIN20_Pos)

Bit mask of PIN20 field.

◆ GPIO_DIRSET_PIN20_Output

#define GPIO_DIRSET_PIN20_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN20_Pos

#define GPIO_DIRSET_PIN20_Pos   (20UL)

Position of PIN20 field.

◆ GPIO_DIRSET_PIN20_Set

#define GPIO_DIRSET_PIN20_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN21_Input

#define GPIO_DIRSET_PIN21_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN21_Msk

#define GPIO_DIRSET_PIN21_Msk   (0x1UL << GPIO_DIRSET_PIN21_Pos)

Bit mask of PIN21 field.

◆ GPIO_DIRSET_PIN21_Output

#define GPIO_DIRSET_PIN21_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN21_Pos

#define GPIO_DIRSET_PIN21_Pos   (21UL)

Position of PIN21 field.

◆ GPIO_DIRSET_PIN21_Set

#define GPIO_DIRSET_PIN21_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN22_Input

#define GPIO_DIRSET_PIN22_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN22_Msk

#define GPIO_DIRSET_PIN22_Msk   (0x1UL << GPIO_DIRSET_PIN22_Pos)

Bit mask of PIN22 field.

◆ GPIO_DIRSET_PIN22_Output

#define GPIO_DIRSET_PIN22_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN22_Pos

#define GPIO_DIRSET_PIN22_Pos   (22UL)

Position of PIN22 field.

◆ GPIO_DIRSET_PIN22_Set

#define GPIO_DIRSET_PIN22_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN23_Input

#define GPIO_DIRSET_PIN23_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN23_Msk

#define GPIO_DIRSET_PIN23_Msk   (0x1UL << GPIO_DIRSET_PIN23_Pos)

Bit mask of PIN23 field.

◆ GPIO_DIRSET_PIN23_Output

#define GPIO_DIRSET_PIN23_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN23_Pos

#define GPIO_DIRSET_PIN23_Pos   (23UL)

Position of PIN23 field.

◆ GPIO_DIRSET_PIN23_Set

#define GPIO_DIRSET_PIN23_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN24_Input

#define GPIO_DIRSET_PIN24_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN24_Msk

#define GPIO_DIRSET_PIN24_Msk   (0x1UL << GPIO_DIRSET_PIN24_Pos)

Bit mask of PIN24 field.

◆ GPIO_DIRSET_PIN24_Output

#define GPIO_DIRSET_PIN24_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN24_Pos

#define GPIO_DIRSET_PIN24_Pos   (24UL)

Position of PIN24 field.

◆ GPIO_DIRSET_PIN24_Set

#define GPIO_DIRSET_PIN24_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN25_Input

#define GPIO_DIRSET_PIN25_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN25_Msk

#define GPIO_DIRSET_PIN25_Msk   (0x1UL << GPIO_DIRSET_PIN25_Pos)

Bit mask of PIN25 field.

◆ GPIO_DIRSET_PIN25_Output

#define GPIO_DIRSET_PIN25_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN25_Pos

#define GPIO_DIRSET_PIN25_Pos   (25UL)

Position of PIN25 field.

◆ GPIO_DIRSET_PIN25_Set

#define GPIO_DIRSET_PIN25_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN26_Input

#define GPIO_DIRSET_PIN26_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN26_Msk

#define GPIO_DIRSET_PIN26_Msk   (0x1UL << GPIO_DIRSET_PIN26_Pos)

Bit mask of PIN26 field.

◆ GPIO_DIRSET_PIN26_Output

#define GPIO_DIRSET_PIN26_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN26_Pos

#define GPIO_DIRSET_PIN26_Pos   (26UL)

Position of PIN26 field.

◆ GPIO_DIRSET_PIN26_Set

#define GPIO_DIRSET_PIN26_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN27_Input

#define GPIO_DIRSET_PIN27_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN27_Msk

#define GPIO_DIRSET_PIN27_Msk   (0x1UL << GPIO_DIRSET_PIN27_Pos)

Bit mask of PIN27 field.

◆ GPIO_DIRSET_PIN27_Output

#define GPIO_DIRSET_PIN27_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN27_Pos

#define GPIO_DIRSET_PIN27_Pos   (27UL)

Position of PIN27 field.

◆ GPIO_DIRSET_PIN27_Set

#define GPIO_DIRSET_PIN27_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN28_Input

#define GPIO_DIRSET_PIN28_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN28_Msk

#define GPIO_DIRSET_PIN28_Msk   (0x1UL << GPIO_DIRSET_PIN28_Pos)

Bit mask of PIN28 field.

◆ GPIO_DIRSET_PIN28_Output

#define GPIO_DIRSET_PIN28_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN28_Pos

#define GPIO_DIRSET_PIN28_Pos   (28UL)

Position of PIN28 field.

◆ GPIO_DIRSET_PIN28_Set

#define GPIO_DIRSET_PIN28_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN29_Input

#define GPIO_DIRSET_PIN29_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN29_Msk

#define GPIO_DIRSET_PIN29_Msk   (0x1UL << GPIO_DIRSET_PIN29_Pos)

Bit mask of PIN29 field.

◆ GPIO_DIRSET_PIN29_Output

#define GPIO_DIRSET_PIN29_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN29_Pos

#define GPIO_DIRSET_PIN29_Pos   (29UL)

Position of PIN29 field.

◆ GPIO_DIRSET_PIN29_Set

#define GPIO_DIRSET_PIN29_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN2_Input

#define GPIO_DIRSET_PIN2_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN2_Msk

#define GPIO_DIRSET_PIN2_Msk   (0x1UL << GPIO_DIRSET_PIN2_Pos)

Bit mask of PIN2 field.

◆ GPIO_DIRSET_PIN2_Output

#define GPIO_DIRSET_PIN2_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN2_Pos

#define GPIO_DIRSET_PIN2_Pos   (2UL)

Position of PIN2 field.

◆ GPIO_DIRSET_PIN2_Set

#define GPIO_DIRSET_PIN2_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN30_Input

#define GPIO_DIRSET_PIN30_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN30_Msk

#define GPIO_DIRSET_PIN30_Msk   (0x1UL << GPIO_DIRSET_PIN30_Pos)

Bit mask of PIN30 field.

◆ GPIO_DIRSET_PIN30_Output

#define GPIO_DIRSET_PIN30_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN30_Pos

#define GPIO_DIRSET_PIN30_Pos   (30UL)

Position of PIN30 field.

◆ GPIO_DIRSET_PIN30_Set

#define GPIO_DIRSET_PIN30_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN31_Input

#define GPIO_DIRSET_PIN31_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN31_Msk

#define GPIO_DIRSET_PIN31_Msk   (0x1UL << GPIO_DIRSET_PIN31_Pos)

Bit mask of PIN31 field.

◆ GPIO_DIRSET_PIN31_Output

#define GPIO_DIRSET_PIN31_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN31_Pos

#define GPIO_DIRSET_PIN31_Pos   (31UL)

Position of PIN31 field.

◆ GPIO_DIRSET_PIN31_Set

#define GPIO_DIRSET_PIN31_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN3_Input

#define GPIO_DIRSET_PIN3_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN3_Msk

#define GPIO_DIRSET_PIN3_Msk   (0x1UL << GPIO_DIRSET_PIN3_Pos)

Bit mask of PIN3 field.

◆ GPIO_DIRSET_PIN3_Output

#define GPIO_DIRSET_PIN3_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN3_Pos

#define GPIO_DIRSET_PIN3_Pos   (3UL)

Position of PIN3 field.

◆ GPIO_DIRSET_PIN3_Set

#define GPIO_DIRSET_PIN3_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN4_Input

#define GPIO_DIRSET_PIN4_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN4_Msk

#define GPIO_DIRSET_PIN4_Msk   (0x1UL << GPIO_DIRSET_PIN4_Pos)

Bit mask of PIN4 field.

◆ GPIO_DIRSET_PIN4_Output

#define GPIO_DIRSET_PIN4_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN4_Pos

#define GPIO_DIRSET_PIN4_Pos   (4UL)

Position of PIN4 field.

◆ GPIO_DIRSET_PIN4_Set

#define GPIO_DIRSET_PIN4_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN5_Input

#define GPIO_DIRSET_PIN5_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN5_Msk

#define GPIO_DIRSET_PIN5_Msk   (0x1UL << GPIO_DIRSET_PIN5_Pos)

Bit mask of PIN5 field.

◆ GPIO_DIRSET_PIN5_Output

#define GPIO_DIRSET_PIN5_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN5_Pos

#define GPIO_DIRSET_PIN5_Pos   (5UL)

Position of PIN5 field.

◆ GPIO_DIRSET_PIN5_Set

#define GPIO_DIRSET_PIN5_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN6_Input

#define GPIO_DIRSET_PIN6_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN6_Msk

#define GPIO_DIRSET_PIN6_Msk   (0x1UL << GPIO_DIRSET_PIN6_Pos)

Bit mask of PIN6 field.

◆ GPIO_DIRSET_PIN6_Output

#define GPIO_DIRSET_PIN6_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN6_Pos

#define GPIO_DIRSET_PIN6_Pos   (6UL)

Position of PIN6 field.

◆ GPIO_DIRSET_PIN6_Set

#define GPIO_DIRSET_PIN6_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN7_Input

#define GPIO_DIRSET_PIN7_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN7_Msk

#define GPIO_DIRSET_PIN7_Msk   (0x1UL << GPIO_DIRSET_PIN7_Pos)

Bit mask of PIN7 field.

◆ GPIO_DIRSET_PIN7_Output

#define GPIO_DIRSET_PIN7_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN7_Pos

#define GPIO_DIRSET_PIN7_Pos   (7UL)

Position of PIN7 field.

◆ GPIO_DIRSET_PIN7_Set

#define GPIO_DIRSET_PIN7_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN8_Input

#define GPIO_DIRSET_PIN8_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN8_Msk

#define GPIO_DIRSET_PIN8_Msk   (0x1UL << GPIO_DIRSET_PIN8_Pos)

Bit mask of PIN8 field.

◆ GPIO_DIRSET_PIN8_Output

#define GPIO_DIRSET_PIN8_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN8_Pos

#define GPIO_DIRSET_PIN8_Pos   (8UL)

Position of PIN8 field.

◆ GPIO_DIRSET_PIN8_Set

#define GPIO_DIRSET_PIN8_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_DIRSET_PIN9_Input

#define GPIO_DIRSET_PIN9_Input   (0UL)

Read: pin set as input

◆ GPIO_DIRSET_PIN9_Msk

#define GPIO_DIRSET_PIN9_Msk   (0x1UL << GPIO_DIRSET_PIN9_Pos)

Bit mask of PIN9 field.

◆ GPIO_DIRSET_PIN9_Output

#define GPIO_DIRSET_PIN9_Output   (1UL)

Read: pin set as output

◆ GPIO_DIRSET_PIN9_Pos

#define GPIO_DIRSET_PIN9_Pos   (9UL)

Position of PIN9 field.

◆ GPIO_DIRSET_PIN9_Set

#define GPIO_DIRSET_PIN9_Set   (1UL)

Write: writing a '1' sets pin to output; writing a '0' has no effect

◆ GPIO_IN_PIN0_High

#define GPIO_IN_PIN0_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN0_Low

#define GPIO_IN_PIN0_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN0_Msk

#define GPIO_IN_PIN0_Msk   (0x1UL << GPIO_IN_PIN0_Pos)

Bit mask of PIN0 field.

◆ GPIO_IN_PIN0_Pos

#define GPIO_IN_PIN0_Pos   (0UL)

Position of PIN0 field.

◆ GPIO_IN_PIN10_High

#define GPIO_IN_PIN10_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN10_Low

#define GPIO_IN_PIN10_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN10_Msk

#define GPIO_IN_PIN10_Msk   (0x1UL << GPIO_IN_PIN10_Pos)

Bit mask of PIN10 field.

◆ GPIO_IN_PIN10_Pos

#define GPIO_IN_PIN10_Pos   (10UL)

Position of PIN10 field.

◆ GPIO_IN_PIN11_High

#define GPIO_IN_PIN11_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN11_Low

#define GPIO_IN_PIN11_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN11_Msk

#define GPIO_IN_PIN11_Msk   (0x1UL << GPIO_IN_PIN11_Pos)

Bit mask of PIN11 field.

◆ GPIO_IN_PIN11_Pos

#define GPIO_IN_PIN11_Pos   (11UL)

Position of PIN11 field.

◆ GPIO_IN_PIN12_High

#define GPIO_IN_PIN12_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN12_Low

#define GPIO_IN_PIN12_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN12_Msk

#define GPIO_IN_PIN12_Msk   (0x1UL << GPIO_IN_PIN12_Pos)

Bit mask of PIN12 field.

◆ GPIO_IN_PIN12_Pos

#define GPIO_IN_PIN12_Pos   (12UL)

Position of PIN12 field.

◆ GPIO_IN_PIN13_High

#define GPIO_IN_PIN13_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN13_Low

#define GPIO_IN_PIN13_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN13_Msk

#define GPIO_IN_PIN13_Msk   (0x1UL << GPIO_IN_PIN13_Pos)

Bit mask of PIN13 field.

◆ GPIO_IN_PIN13_Pos

#define GPIO_IN_PIN13_Pos   (13UL)

Position of PIN13 field.

◆ GPIO_IN_PIN14_High

#define GPIO_IN_PIN14_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN14_Low

#define GPIO_IN_PIN14_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN14_Msk

#define GPIO_IN_PIN14_Msk   (0x1UL << GPIO_IN_PIN14_Pos)

Bit mask of PIN14 field.

◆ GPIO_IN_PIN14_Pos

#define GPIO_IN_PIN14_Pos   (14UL)

Position of PIN14 field.

◆ GPIO_IN_PIN15_High

#define GPIO_IN_PIN15_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN15_Low

#define GPIO_IN_PIN15_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN15_Msk

#define GPIO_IN_PIN15_Msk   (0x1UL << GPIO_IN_PIN15_Pos)

Bit mask of PIN15 field.

◆ GPIO_IN_PIN15_Pos

#define GPIO_IN_PIN15_Pos   (15UL)

Position of PIN15 field.

◆ GPIO_IN_PIN16_High

#define GPIO_IN_PIN16_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN16_Low

#define GPIO_IN_PIN16_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN16_Msk

#define GPIO_IN_PIN16_Msk   (0x1UL << GPIO_IN_PIN16_Pos)

Bit mask of PIN16 field.

◆ GPIO_IN_PIN16_Pos

#define GPIO_IN_PIN16_Pos   (16UL)

Position of PIN16 field.

◆ GPIO_IN_PIN17_High

#define GPIO_IN_PIN17_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN17_Low

#define GPIO_IN_PIN17_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN17_Msk

#define GPIO_IN_PIN17_Msk   (0x1UL << GPIO_IN_PIN17_Pos)

Bit mask of PIN17 field.

◆ GPIO_IN_PIN17_Pos

#define GPIO_IN_PIN17_Pos   (17UL)

Position of PIN17 field.

◆ GPIO_IN_PIN18_High

#define GPIO_IN_PIN18_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN18_Low

#define GPIO_IN_PIN18_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN18_Msk

#define GPIO_IN_PIN18_Msk   (0x1UL << GPIO_IN_PIN18_Pos)

Bit mask of PIN18 field.

◆ GPIO_IN_PIN18_Pos

#define GPIO_IN_PIN18_Pos   (18UL)

Position of PIN18 field.

◆ GPIO_IN_PIN19_High

#define GPIO_IN_PIN19_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN19_Low

#define GPIO_IN_PIN19_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN19_Msk

#define GPIO_IN_PIN19_Msk   (0x1UL << GPIO_IN_PIN19_Pos)

Bit mask of PIN19 field.

◆ GPIO_IN_PIN19_Pos

#define GPIO_IN_PIN19_Pos   (19UL)

Position of PIN19 field.

◆ GPIO_IN_PIN1_High

#define GPIO_IN_PIN1_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN1_Low

#define GPIO_IN_PIN1_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN1_Msk

#define GPIO_IN_PIN1_Msk   (0x1UL << GPIO_IN_PIN1_Pos)

Bit mask of PIN1 field.

◆ GPIO_IN_PIN1_Pos

#define GPIO_IN_PIN1_Pos   (1UL)

Position of PIN1 field.

◆ GPIO_IN_PIN20_High

#define GPIO_IN_PIN20_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN20_Low

#define GPIO_IN_PIN20_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN20_Msk

#define GPIO_IN_PIN20_Msk   (0x1UL << GPIO_IN_PIN20_Pos)

Bit mask of PIN20 field.

◆ GPIO_IN_PIN20_Pos

#define GPIO_IN_PIN20_Pos   (20UL)

Position of PIN20 field.

◆ GPIO_IN_PIN21_High

#define GPIO_IN_PIN21_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN21_Low

#define GPIO_IN_PIN21_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN21_Msk

#define GPIO_IN_PIN21_Msk   (0x1UL << GPIO_IN_PIN21_Pos)

Bit mask of PIN21 field.

◆ GPIO_IN_PIN21_Pos

#define GPIO_IN_PIN21_Pos   (21UL)

Position of PIN21 field.

◆ GPIO_IN_PIN22_High

#define GPIO_IN_PIN22_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN22_Low

#define GPIO_IN_PIN22_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN22_Msk

#define GPIO_IN_PIN22_Msk   (0x1UL << GPIO_IN_PIN22_Pos)

Bit mask of PIN22 field.

◆ GPIO_IN_PIN22_Pos

#define GPIO_IN_PIN22_Pos   (22UL)

Position of PIN22 field.

◆ GPIO_IN_PIN23_High

#define GPIO_IN_PIN23_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN23_Low

#define GPIO_IN_PIN23_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN23_Msk

#define GPIO_IN_PIN23_Msk   (0x1UL << GPIO_IN_PIN23_Pos)

Bit mask of PIN23 field.

◆ GPIO_IN_PIN23_Pos

#define GPIO_IN_PIN23_Pos   (23UL)

Position of PIN23 field.

◆ GPIO_IN_PIN24_High

#define GPIO_IN_PIN24_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN24_Low

#define GPIO_IN_PIN24_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN24_Msk

#define GPIO_IN_PIN24_Msk   (0x1UL << GPIO_IN_PIN24_Pos)

Bit mask of PIN24 field.

◆ GPIO_IN_PIN24_Pos

#define GPIO_IN_PIN24_Pos   (24UL)

Position of PIN24 field.

◆ GPIO_IN_PIN25_High

#define GPIO_IN_PIN25_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN25_Low

#define GPIO_IN_PIN25_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN25_Msk

#define GPIO_IN_PIN25_Msk   (0x1UL << GPIO_IN_PIN25_Pos)

Bit mask of PIN25 field.

◆ GPIO_IN_PIN25_Pos

#define GPIO_IN_PIN25_Pos   (25UL)

Position of PIN25 field.

◆ GPIO_IN_PIN26_High

#define GPIO_IN_PIN26_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN26_Low

#define GPIO_IN_PIN26_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN26_Msk

#define GPIO_IN_PIN26_Msk   (0x1UL << GPIO_IN_PIN26_Pos)

Bit mask of PIN26 field.

◆ GPIO_IN_PIN26_Pos

#define GPIO_IN_PIN26_Pos   (26UL)

Position of PIN26 field.

◆ GPIO_IN_PIN27_High

#define GPIO_IN_PIN27_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN27_Low

#define GPIO_IN_PIN27_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN27_Msk

#define GPIO_IN_PIN27_Msk   (0x1UL << GPIO_IN_PIN27_Pos)

Bit mask of PIN27 field.

◆ GPIO_IN_PIN27_Pos

#define GPIO_IN_PIN27_Pos   (27UL)

Position of PIN27 field.

◆ GPIO_IN_PIN28_High

#define GPIO_IN_PIN28_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN28_Low

#define GPIO_IN_PIN28_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN28_Msk

#define GPIO_IN_PIN28_Msk   (0x1UL << GPIO_IN_PIN28_Pos)

Bit mask of PIN28 field.

◆ GPIO_IN_PIN28_Pos

#define GPIO_IN_PIN28_Pos   (28UL)

Position of PIN28 field.

◆ GPIO_IN_PIN29_High

#define GPIO_IN_PIN29_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN29_Low

#define GPIO_IN_PIN29_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN29_Msk

#define GPIO_IN_PIN29_Msk   (0x1UL << GPIO_IN_PIN29_Pos)

Bit mask of PIN29 field.

◆ GPIO_IN_PIN29_Pos

#define GPIO_IN_PIN29_Pos   (29UL)

Position of PIN29 field.

◆ GPIO_IN_PIN2_High

#define GPIO_IN_PIN2_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN2_Low

#define GPIO_IN_PIN2_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN2_Msk

#define GPIO_IN_PIN2_Msk   (0x1UL << GPIO_IN_PIN2_Pos)

Bit mask of PIN2 field.

◆ GPIO_IN_PIN2_Pos

#define GPIO_IN_PIN2_Pos   (2UL)

Position of PIN2 field.

◆ GPIO_IN_PIN30_High

#define GPIO_IN_PIN30_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN30_Low

#define GPIO_IN_PIN30_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN30_Msk

#define GPIO_IN_PIN30_Msk   (0x1UL << GPIO_IN_PIN30_Pos)

Bit mask of PIN30 field.

◆ GPIO_IN_PIN30_Pos

#define GPIO_IN_PIN30_Pos   (30UL)

Position of PIN30 field.

◆ GPIO_IN_PIN31_High

#define GPIO_IN_PIN31_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN31_Low

#define GPIO_IN_PIN31_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN31_Msk

#define GPIO_IN_PIN31_Msk   (0x1UL << GPIO_IN_PIN31_Pos)

Bit mask of PIN31 field.

◆ GPIO_IN_PIN31_Pos

#define GPIO_IN_PIN31_Pos   (31UL)

Position of PIN31 field.

◆ GPIO_IN_PIN3_High

#define GPIO_IN_PIN3_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN3_Low

#define GPIO_IN_PIN3_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN3_Msk

#define GPIO_IN_PIN3_Msk   (0x1UL << GPIO_IN_PIN3_Pos)

Bit mask of PIN3 field.

◆ GPIO_IN_PIN3_Pos

#define GPIO_IN_PIN3_Pos   (3UL)

Position of PIN3 field.

◆ GPIO_IN_PIN4_High

#define GPIO_IN_PIN4_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN4_Low

#define GPIO_IN_PIN4_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN4_Msk

#define GPIO_IN_PIN4_Msk   (0x1UL << GPIO_IN_PIN4_Pos)

Bit mask of PIN4 field.

◆ GPIO_IN_PIN4_Pos

#define GPIO_IN_PIN4_Pos   (4UL)

Position of PIN4 field.

◆ GPIO_IN_PIN5_High

#define GPIO_IN_PIN5_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN5_Low

#define GPIO_IN_PIN5_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN5_Msk

#define GPIO_IN_PIN5_Msk   (0x1UL << GPIO_IN_PIN5_Pos)

Bit mask of PIN5 field.

◆ GPIO_IN_PIN5_Pos

#define GPIO_IN_PIN5_Pos   (5UL)

Position of PIN5 field.

◆ GPIO_IN_PIN6_High

#define GPIO_IN_PIN6_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN6_Low

#define GPIO_IN_PIN6_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN6_Msk

#define GPIO_IN_PIN6_Msk   (0x1UL << GPIO_IN_PIN6_Pos)

Bit mask of PIN6 field.

◆ GPIO_IN_PIN6_Pos

#define GPIO_IN_PIN6_Pos   (6UL)

Position of PIN6 field.

◆ GPIO_IN_PIN7_High

#define GPIO_IN_PIN7_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN7_Low

#define GPIO_IN_PIN7_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN7_Msk

#define GPIO_IN_PIN7_Msk   (0x1UL << GPIO_IN_PIN7_Pos)

Bit mask of PIN7 field.

◆ GPIO_IN_PIN7_Pos

#define GPIO_IN_PIN7_Pos   (7UL)

Position of PIN7 field.

◆ GPIO_IN_PIN8_High

#define GPIO_IN_PIN8_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN8_Low

#define GPIO_IN_PIN8_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN8_Msk

#define GPIO_IN_PIN8_Msk   (0x1UL << GPIO_IN_PIN8_Pos)

Bit mask of PIN8 field.

◆ GPIO_IN_PIN8_Pos

#define GPIO_IN_PIN8_Pos   (8UL)

Position of PIN8 field.

◆ GPIO_IN_PIN9_High

#define GPIO_IN_PIN9_High   (1UL)

Pin input is high

◆ GPIO_IN_PIN9_Low

#define GPIO_IN_PIN9_Low   (0UL)

Pin input is low

◆ GPIO_IN_PIN9_Msk

#define GPIO_IN_PIN9_Msk   (0x1UL << GPIO_IN_PIN9_Pos)

Bit mask of PIN9 field.

◆ GPIO_IN_PIN9_Pos

#define GPIO_IN_PIN9_Pos   (9UL)

Position of PIN9 field.

◆ GPIO_LATCH_PIN0_Latched

#define GPIO_LATCH_PIN0_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN0_Msk

#define GPIO_LATCH_PIN0_Msk   (0x1UL << GPIO_LATCH_PIN0_Pos)

Bit mask of PIN0 field.

◆ GPIO_LATCH_PIN0_NotLatched

#define GPIO_LATCH_PIN0_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN0_Pos

#define GPIO_LATCH_PIN0_Pos   (0UL)

Position of PIN0 field.

◆ GPIO_LATCH_PIN10_Latched

#define GPIO_LATCH_PIN10_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN10_Msk

#define GPIO_LATCH_PIN10_Msk   (0x1UL << GPIO_LATCH_PIN10_Pos)

Bit mask of PIN10 field.

◆ GPIO_LATCH_PIN10_NotLatched

#define GPIO_LATCH_PIN10_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN10_Pos

#define GPIO_LATCH_PIN10_Pos   (10UL)

Position of PIN10 field.

◆ GPIO_LATCH_PIN11_Latched

#define GPIO_LATCH_PIN11_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN11_Msk

#define GPIO_LATCH_PIN11_Msk   (0x1UL << GPIO_LATCH_PIN11_Pos)

Bit mask of PIN11 field.

◆ GPIO_LATCH_PIN11_NotLatched

#define GPIO_LATCH_PIN11_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN11_Pos

#define GPIO_LATCH_PIN11_Pos   (11UL)

Position of PIN11 field.

◆ GPIO_LATCH_PIN12_Latched

#define GPIO_LATCH_PIN12_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN12_Msk

#define GPIO_LATCH_PIN12_Msk   (0x1UL << GPIO_LATCH_PIN12_Pos)

Bit mask of PIN12 field.

◆ GPIO_LATCH_PIN12_NotLatched

#define GPIO_LATCH_PIN12_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN12_Pos

#define GPIO_LATCH_PIN12_Pos   (12UL)

Position of PIN12 field.

◆ GPIO_LATCH_PIN13_Latched

#define GPIO_LATCH_PIN13_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN13_Msk

#define GPIO_LATCH_PIN13_Msk   (0x1UL << GPIO_LATCH_PIN13_Pos)

Bit mask of PIN13 field.

◆ GPIO_LATCH_PIN13_NotLatched

#define GPIO_LATCH_PIN13_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN13_Pos

#define GPIO_LATCH_PIN13_Pos   (13UL)

Position of PIN13 field.

◆ GPIO_LATCH_PIN14_Latched

#define GPIO_LATCH_PIN14_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN14_Msk

#define GPIO_LATCH_PIN14_Msk   (0x1UL << GPIO_LATCH_PIN14_Pos)

Bit mask of PIN14 field.

◆ GPIO_LATCH_PIN14_NotLatched

#define GPIO_LATCH_PIN14_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN14_Pos

#define GPIO_LATCH_PIN14_Pos   (14UL)

Position of PIN14 field.

◆ GPIO_LATCH_PIN15_Latched

#define GPIO_LATCH_PIN15_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN15_Msk

#define GPIO_LATCH_PIN15_Msk   (0x1UL << GPIO_LATCH_PIN15_Pos)

Bit mask of PIN15 field.

◆ GPIO_LATCH_PIN15_NotLatched

#define GPIO_LATCH_PIN15_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN15_Pos

#define GPIO_LATCH_PIN15_Pos   (15UL)

Position of PIN15 field.

◆ GPIO_LATCH_PIN16_Latched

#define GPIO_LATCH_PIN16_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN16_Msk

#define GPIO_LATCH_PIN16_Msk   (0x1UL << GPIO_LATCH_PIN16_Pos)

Bit mask of PIN16 field.

◆ GPIO_LATCH_PIN16_NotLatched

#define GPIO_LATCH_PIN16_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN16_Pos

#define GPIO_LATCH_PIN16_Pos   (16UL)

Position of PIN16 field.

◆ GPIO_LATCH_PIN17_Latched

#define GPIO_LATCH_PIN17_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN17_Msk

#define GPIO_LATCH_PIN17_Msk   (0x1UL << GPIO_LATCH_PIN17_Pos)

Bit mask of PIN17 field.

◆ GPIO_LATCH_PIN17_NotLatched

#define GPIO_LATCH_PIN17_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN17_Pos

#define GPIO_LATCH_PIN17_Pos   (17UL)

Position of PIN17 field.

◆ GPIO_LATCH_PIN18_Latched

#define GPIO_LATCH_PIN18_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN18_Msk

#define GPIO_LATCH_PIN18_Msk   (0x1UL << GPIO_LATCH_PIN18_Pos)

Bit mask of PIN18 field.

◆ GPIO_LATCH_PIN18_NotLatched

#define GPIO_LATCH_PIN18_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN18_Pos

#define GPIO_LATCH_PIN18_Pos   (18UL)

Position of PIN18 field.

◆ GPIO_LATCH_PIN19_Latched

#define GPIO_LATCH_PIN19_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN19_Msk

#define GPIO_LATCH_PIN19_Msk   (0x1UL << GPIO_LATCH_PIN19_Pos)

Bit mask of PIN19 field.

◆ GPIO_LATCH_PIN19_NotLatched

#define GPIO_LATCH_PIN19_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN19_Pos

#define GPIO_LATCH_PIN19_Pos   (19UL)

Position of PIN19 field.

◆ GPIO_LATCH_PIN1_Latched

#define GPIO_LATCH_PIN1_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN1_Msk

#define GPIO_LATCH_PIN1_Msk   (0x1UL << GPIO_LATCH_PIN1_Pos)

Bit mask of PIN1 field.

◆ GPIO_LATCH_PIN1_NotLatched

#define GPIO_LATCH_PIN1_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN1_Pos

#define GPIO_LATCH_PIN1_Pos   (1UL)

Position of PIN1 field.

◆ GPIO_LATCH_PIN20_Latched

#define GPIO_LATCH_PIN20_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN20_Msk

#define GPIO_LATCH_PIN20_Msk   (0x1UL << GPIO_LATCH_PIN20_Pos)

Bit mask of PIN20 field.

◆ GPIO_LATCH_PIN20_NotLatched

#define GPIO_LATCH_PIN20_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN20_Pos

#define GPIO_LATCH_PIN20_Pos   (20UL)

Position of PIN20 field.

◆ GPIO_LATCH_PIN21_Latched

#define GPIO_LATCH_PIN21_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN21_Msk

#define GPIO_LATCH_PIN21_Msk   (0x1UL << GPIO_LATCH_PIN21_Pos)

Bit mask of PIN21 field.

◆ GPIO_LATCH_PIN21_NotLatched

#define GPIO_LATCH_PIN21_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN21_Pos

#define GPIO_LATCH_PIN21_Pos   (21UL)

Position of PIN21 field.

◆ GPIO_LATCH_PIN22_Latched

#define GPIO_LATCH_PIN22_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN22_Msk

#define GPIO_LATCH_PIN22_Msk   (0x1UL << GPIO_LATCH_PIN22_Pos)

Bit mask of PIN22 field.

◆ GPIO_LATCH_PIN22_NotLatched

#define GPIO_LATCH_PIN22_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN22_Pos

#define GPIO_LATCH_PIN22_Pos   (22UL)

Position of PIN22 field.

◆ GPIO_LATCH_PIN23_Latched

#define GPIO_LATCH_PIN23_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN23_Msk

#define GPIO_LATCH_PIN23_Msk   (0x1UL << GPIO_LATCH_PIN23_Pos)

Bit mask of PIN23 field.

◆ GPIO_LATCH_PIN23_NotLatched

#define GPIO_LATCH_PIN23_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN23_Pos

#define GPIO_LATCH_PIN23_Pos   (23UL)

Position of PIN23 field.

◆ GPIO_LATCH_PIN24_Latched

#define GPIO_LATCH_PIN24_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN24_Msk

#define GPIO_LATCH_PIN24_Msk   (0x1UL << GPIO_LATCH_PIN24_Pos)

Bit mask of PIN24 field.

◆ GPIO_LATCH_PIN24_NotLatched

#define GPIO_LATCH_PIN24_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN24_Pos

#define GPIO_LATCH_PIN24_Pos   (24UL)

Position of PIN24 field.

◆ GPIO_LATCH_PIN25_Latched

#define GPIO_LATCH_PIN25_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN25_Msk

#define GPIO_LATCH_PIN25_Msk   (0x1UL << GPIO_LATCH_PIN25_Pos)

Bit mask of PIN25 field.

◆ GPIO_LATCH_PIN25_NotLatched

#define GPIO_LATCH_PIN25_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN25_Pos

#define GPIO_LATCH_PIN25_Pos   (25UL)

Position of PIN25 field.

◆ GPIO_LATCH_PIN26_Latched

#define GPIO_LATCH_PIN26_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN26_Msk

#define GPIO_LATCH_PIN26_Msk   (0x1UL << GPIO_LATCH_PIN26_Pos)

Bit mask of PIN26 field.

◆ GPIO_LATCH_PIN26_NotLatched

#define GPIO_LATCH_PIN26_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN26_Pos

#define GPIO_LATCH_PIN26_Pos   (26UL)

Position of PIN26 field.

◆ GPIO_LATCH_PIN27_Latched

#define GPIO_LATCH_PIN27_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN27_Msk

#define GPIO_LATCH_PIN27_Msk   (0x1UL << GPIO_LATCH_PIN27_Pos)

Bit mask of PIN27 field.

◆ GPIO_LATCH_PIN27_NotLatched

#define GPIO_LATCH_PIN27_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN27_Pos

#define GPIO_LATCH_PIN27_Pos   (27UL)

Position of PIN27 field.

◆ GPIO_LATCH_PIN28_Latched

#define GPIO_LATCH_PIN28_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN28_Msk

#define GPIO_LATCH_PIN28_Msk   (0x1UL << GPIO_LATCH_PIN28_Pos)

Bit mask of PIN28 field.

◆ GPIO_LATCH_PIN28_NotLatched

#define GPIO_LATCH_PIN28_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN28_Pos

#define GPIO_LATCH_PIN28_Pos   (28UL)

Position of PIN28 field.

◆ GPIO_LATCH_PIN29_Latched

#define GPIO_LATCH_PIN29_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN29_Msk

#define GPIO_LATCH_PIN29_Msk   (0x1UL << GPIO_LATCH_PIN29_Pos)

Bit mask of PIN29 field.

◆ GPIO_LATCH_PIN29_NotLatched

#define GPIO_LATCH_PIN29_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN29_Pos

#define GPIO_LATCH_PIN29_Pos   (29UL)

Position of PIN29 field.

◆ GPIO_LATCH_PIN2_Latched

#define GPIO_LATCH_PIN2_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN2_Msk

#define GPIO_LATCH_PIN2_Msk   (0x1UL << GPIO_LATCH_PIN2_Pos)

Bit mask of PIN2 field.

◆ GPIO_LATCH_PIN2_NotLatched

#define GPIO_LATCH_PIN2_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN2_Pos

#define GPIO_LATCH_PIN2_Pos   (2UL)

Position of PIN2 field.

◆ GPIO_LATCH_PIN30_Latched

#define GPIO_LATCH_PIN30_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN30_Msk

#define GPIO_LATCH_PIN30_Msk   (0x1UL << GPIO_LATCH_PIN30_Pos)

Bit mask of PIN30 field.

◆ GPIO_LATCH_PIN30_NotLatched

#define GPIO_LATCH_PIN30_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN30_Pos

#define GPIO_LATCH_PIN30_Pos   (30UL)

Position of PIN30 field.

◆ GPIO_LATCH_PIN31_Latched

#define GPIO_LATCH_PIN31_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN31_Msk

#define GPIO_LATCH_PIN31_Msk   (0x1UL << GPIO_LATCH_PIN31_Pos)

Bit mask of PIN31 field.

◆ GPIO_LATCH_PIN31_NotLatched

#define GPIO_LATCH_PIN31_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN31_Pos

#define GPIO_LATCH_PIN31_Pos   (31UL)

Position of PIN31 field.

◆ GPIO_LATCH_PIN3_Latched

#define GPIO_LATCH_PIN3_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN3_Msk

#define GPIO_LATCH_PIN3_Msk   (0x1UL << GPIO_LATCH_PIN3_Pos)

Bit mask of PIN3 field.

◆ GPIO_LATCH_PIN3_NotLatched

#define GPIO_LATCH_PIN3_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN3_Pos

#define GPIO_LATCH_PIN3_Pos   (3UL)

Position of PIN3 field.

◆ GPIO_LATCH_PIN4_Latched

#define GPIO_LATCH_PIN4_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN4_Msk

#define GPIO_LATCH_PIN4_Msk   (0x1UL << GPIO_LATCH_PIN4_Pos)

Bit mask of PIN4 field.

◆ GPIO_LATCH_PIN4_NotLatched

#define GPIO_LATCH_PIN4_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN4_Pos

#define GPIO_LATCH_PIN4_Pos   (4UL)

Position of PIN4 field.

◆ GPIO_LATCH_PIN5_Latched

#define GPIO_LATCH_PIN5_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN5_Msk

#define GPIO_LATCH_PIN5_Msk   (0x1UL << GPIO_LATCH_PIN5_Pos)

Bit mask of PIN5 field.

◆ GPIO_LATCH_PIN5_NotLatched

#define GPIO_LATCH_PIN5_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN5_Pos

#define GPIO_LATCH_PIN5_Pos   (5UL)

Position of PIN5 field.

◆ GPIO_LATCH_PIN6_Latched

#define GPIO_LATCH_PIN6_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN6_Msk

#define GPIO_LATCH_PIN6_Msk   (0x1UL << GPIO_LATCH_PIN6_Pos)

Bit mask of PIN6 field.

◆ GPIO_LATCH_PIN6_NotLatched

#define GPIO_LATCH_PIN6_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN6_Pos

#define GPIO_LATCH_PIN6_Pos   (6UL)

Position of PIN6 field.

◆ GPIO_LATCH_PIN7_Latched

#define GPIO_LATCH_PIN7_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN7_Msk

#define GPIO_LATCH_PIN7_Msk   (0x1UL << GPIO_LATCH_PIN7_Pos)

Bit mask of PIN7 field.

◆ GPIO_LATCH_PIN7_NotLatched

#define GPIO_LATCH_PIN7_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN7_Pos

#define GPIO_LATCH_PIN7_Pos   (7UL)

Position of PIN7 field.

◆ GPIO_LATCH_PIN8_Latched

#define GPIO_LATCH_PIN8_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN8_Msk

#define GPIO_LATCH_PIN8_Msk   (0x1UL << GPIO_LATCH_PIN8_Pos)

Bit mask of PIN8 field.

◆ GPIO_LATCH_PIN8_NotLatched

#define GPIO_LATCH_PIN8_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN8_Pos

#define GPIO_LATCH_PIN8_Pos   (8UL)

Position of PIN8 field.

◆ GPIO_LATCH_PIN9_Latched

#define GPIO_LATCH_PIN9_Latched   (1UL)

Criteria has been met

◆ GPIO_LATCH_PIN9_Msk

#define GPIO_LATCH_PIN9_Msk   (0x1UL << GPIO_LATCH_PIN9_Pos)

Bit mask of PIN9 field.

◆ GPIO_LATCH_PIN9_NotLatched

#define GPIO_LATCH_PIN9_NotLatched   (0UL)

Criteria has not been met

◆ GPIO_LATCH_PIN9_Pos

#define GPIO_LATCH_PIN9_Pos   (9UL)

Position of PIN9 field.

◆ GPIO_OUT_PIN0_High

#define GPIO_OUT_PIN0_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN0_Low

#define GPIO_OUT_PIN0_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN0_Msk

#define GPIO_OUT_PIN0_Msk   (0x1UL << GPIO_OUT_PIN0_Pos)

Bit mask of PIN0 field.

◆ GPIO_OUT_PIN0_Pos

#define GPIO_OUT_PIN0_Pos   (0UL)

Position of PIN0 field.

◆ GPIO_OUT_PIN10_High

#define GPIO_OUT_PIN10_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN10_Low

#define GPIO_OUT_PIN10_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN10_Msk

#define GPIO_OUT_PIN10_Msk   (0x1UL << GPIO_OUT_PIN10_Pos)

Bit mask of PIN10 field.

◆ GPIO_OUT_PIN10_Pos

#define GPIO_OUT_PIN10_Pos   (10UL)

Position of PIN10 field.

◆ GPIO_OUT_PIN11_High

#define GPIO_OUT_PIN11_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN11_Low

#define GPIO_OUT_PIN11_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN11_Msk

#define GPIO_OUT_PIN11_Msk   (0x1UL << GPIO_OUT_PIN11_Pos)

Bit mask of PIN11 field.

◆ GPIO_OUT_PIN11_Pos

#define GPIO_OUT_PIN11_Pos   (11UL)

Position of PIN11 field.

◆ GPIO_OUT_PIN12_High

#define GPIO_OUT_PIN12_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN12_Low

#define GPIO_OUT_PIN12_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN12_Msk

#define GPIO_OUT_PIN12_Msk   (0x1UL << GPIO_OUT_PIN12_Pos)

Bit mask of PIN12 field.

◆ GPIO_OUT_PIN12_Pos

#define GPIO_OUT_PIN12_Pos   (12UL)

Position of PIN12 field.

◆ GPIO_OUT_PIN13_High

#define GPIO_OUT_PIN13_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN13_Low

#define GPIO_OUT_PIN13_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN13_Msk

#define GPIO_OUT_PIN13_Msk   (0x1UL << GPIO_OUT_PIN13_Pos)

Bit mask of PIN13 field.

◆ GPIO_OUT_PIN13_Pos

#define GPIO_OUT_PIN13_Pos   (13UL)

Position of PIN13 field.

◆ GPIO_OUT_PIN14_High

#define GPIO_OUT_PIN14_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN14_Low

#define GPIO_OUT_PIN14_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN14_Msk

#define GPIO_OUT_PIN14_Msk   (0x1UL << GPIO_OUT_PIN14_Pos)

Bit mask of PIN14 field.

◆ GPIO_OUT_PIN14_Pos

#define GPIO_OUT_PIN14_Pos   (14UL)

Position of PIN14 field.

◆ GPIO_OUT_PIN15_High

#define GPIO_OUT_PIN15_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN15_Low

#define GPIO_OUT_PIN15_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN15_Msk

#define GPIO_OUT_PIN15_Msk   (0x1UL << GPIO_OUT_PIN15_Pos)

Bit mask of PIN15 field.

◆ GPIO_OUT_PIN15_Pos

#define GPIO_OUT_PIN15_Pos   (15UL)

Position of PIN15 field.

◆ GPIO_OUT_PIN16_High

#define GPIO_OUT_PIN16_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN16_Low

#define GPIO_OUT_PIN16_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN16_Msk

#define GPIO_OUT_PIN16_Msk   (0x1UL << GPIO_OUT_PIN16_Pos)

Bit mask of PIN16 field.

◆ GPIO_OUT_PIN16_Pos

#define GPIO_OUT_PIN16_Pos   (16UL)

Position of PIN16 field.

◆ GPIO_OUT_PIN17_High

#define GPIO_OUT_PIN17_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN17_Low

#define GPIO_OUT_PIN17_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN17_Msk

#define GPIO_OUT_PIN17_Msk   (0x1UL << GPIO_OUT_PIN17_Pos)

Bit mask of PIN17 field.

◆ GPIO_OUT_PIN17_Pos

#define GPIO_OUT_PIN17_Pos   (17UL)

Position of PIN17 field.

◆ GPIO_OUT_PIN18_High

#define GPIO_OUT_PIN18_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN18_Low

#define GPIO_OUT_PIN18_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN18_Msk

#define GPIO_OUT_PIN18_Msk   (0x1UL << GPIO_OUT_PIN18_Pos)

Bit mask of PIN18 field.

◆ GPIO_OUT_PIN18_Pos

#define GPIO_OUT_PIN18_Pos   (18UL)

Position of PIN18 field.

◆ GPIO_OUT_PIN19_High

#define GPIO_OUT_PIN19_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN19_Low

#define GPIO_OUT_PIN19_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN19_Msk

#define GPIO_OUT_PIN19_Msk   (0x1UL << GPIO_OUT_PIN19_Pos)

Bit mask of PIN19 field.

◆ GPIO_OUT_PIN19_Pos

#define GPIO_OUT_PIN19_Pos   (19UL)

Position of PIN19 field.

◆ GPIO_OUT_PIN1_High

#define GPIO_OUT_PIN1_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN1_Low

#define GPIO_OUT_PIN1_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN1_Msk

#define GPIO_OUT_PIN1_Msk   (0x1UL << GPIO_OUT_PIN1_Pos)

Bit mask of PIN1 field.

◆ GPIO_OUT_PIN1_Pos

#define GPIO_OUT_PIN1_Pos   (1UL)

Position of PIN1 field.

◆ GPIO_OUT_PIN20_High

#define GPIO_OUT_PIN20_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN20_Low

#define GPIO_OUT_PIN20_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN20_Msk

#define GPIO_OUT_PIN20_Msk   (0x1UL << GPIO_OUT_PIN20_Pos)

Bit mask of PIN20 field.

◆ GPIO_OUT_PIN20_Pos

#define GPIO_OUT_PIN20_Pos   (20UL)

Position of PIN20 field.

◆ GPIO_OUT_PIN21_High

#define GPIO_OUT_PIN21_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN21_Low

#define GPIO_OUT_PIN21_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN21_Msk

#define GPIO_OUT_PIN21_Msk   (0x1UL << GPIO_OUT_PIN21_Pos)

Bit mask of PIN21 field.

◆ GPIO_OUT_PIN21_Pos

#define GPIO_OUT_PIN21_Pos   (21UL)

Position of PIN21 field.

◆ GPIO_OUT_PIN22_High

#define GPIO_OUT_PIN22_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN22_Low

#define GPIO_OUT_PIN22_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN22_Msk

#define GPIO_OUT_PIN22_Msk   (0x1UL << GPIO_OUT_PIN22_Pos)

Bit mask of PIN22 field.

◆ GPIO_OUT_PIN22_Pos

#define GPIO_OUT_PIN22_Pos   (22UL)

Position of PIN22 field.

◆ GPIO_OUT_PIN23_High

#define GPIO_OUT_PIN23_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN23_Low

#define GPIO_OUT_PIN23_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN23_Msk

#define GPIO_OUT_PIN23_Msk   (0x1UL << GPIO_OUT_PIN23_Pos)

Bit mask of PIN23 field.

◆ GPIO_OUT_PIN23_Pos

#define GPIO_OUT_PIN23_Pos   (23UL)

Position of PIN23 field.

◆ GPIO_OUT_PIN24_High

#define GPIO_OUT_PIN24_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN24_Low

#define GPIO_OUT_PIN24_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN24_Msk

#define GPIO_OUT_PIN24_Msk   (0x1UL << GPIO_OUT_PIN24_Pos)

Bit mask of PIN24 field.

◆ GPIO_OUT_PIN24_Pos

#define GPIO_OUT_PIN24_Pos   (24UL)

Position of PIN24 field.

◆ GPIO_OUT_PIN25_High

#define GPIO_OUT_PIN25_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN25_Low

#define GPIO_OUT_PIN25_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN25_Msk

#define GPIO_OUT_PIN25_Msk   (0x1UL << GPIO_OUT_PIN25_Pos)

Bit mask of PIN25 field.

◆ GPIO_OUT_PIN25_Pos

#define GPIO_OUT_PIN25_Pos   (25UL)

Position of PIN25 field.

◆ GPIO_OUT_PIN26_High

#define GPIO_OUT_PIN26_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN26_Low

#define GPIO_OUT_PIN26_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN26_Msk

#define GPIO_OUT_PIN26_Msk   (0x1UL << GPIO_OUT_PIN26_Pos)

Bit mask of PIN26 field.

◆ GPIO_OUT_PIN26_Pos

#define GPIO_OUT_PIN26_Pos   (26UL)

Position of PIN26 field.

◆ GPIO_OUT_PIN27_High

#define GPIO_OUT_PIN27_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN27_Low

#define GPIO_OUT_PIN27_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN27_Msk

#define GPIO_OUT_PIN27_Msk   (0x1UL << GPIO_OUT_PIN27_Pos)

Bit mask of PIN27 field.

◆ GPIO_OUT_PIN27_Pos

#define GPIO_OUT_PIN27_Pos   (27UL)

Position of PIN27 field.

◆ GPIO_OUT_PIN28_High

#define GPIO_OUT_PIN28_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN28_Low

#define GPIO_OUT_PIN28_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN28_Msk

#define GPIO_OUT_PIN28_Msk   (0x1UL << GPIO_OUT_PIN28_Pos)

Bit mask of PIN28 field.

◆ GPIO_OUT_PIN28_Pos

#define GPIO_OUT_PIN28_Pos   (28UL)

Position of PIN28 field.

◆ GPIO_OUT_PIN29_High

#define GPIO_OUT_PIN29_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN29_Low

#define GPIO_OUT_PIN29_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN29_Msk

#define GPIO_OUT_PIN29_Msk   (0x1UL << GPIO_OUT_PIN29_Pos)

Bit mask of PIN29 field.

◆ GPIO_OUT_PIN29_Pos

#define GPIO_OUT_PIN29_Pos   (29UL)

Position of PIN29 field.

◆ GPIO_OUT_PIN2_High

#define GPIO_OUT_PIN2_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN2_Low

#define GPIO_OUT_PIN2_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN2_Msk

#define GPIO_OUT_PIN2_Msk   (0x1UL << GPIO_OUT_PIN2_Pos)

Bit mask of PIN2 field.

◆ GPIO_OUT_PIN2_Pos

#define GPIO_OUT_PIN2_Pos   (2UL)

Position of PIN2 field.

◆ GPIO_OUT_PIN30_High

#define GPIO_OUT_PIN30_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN30_Low

#define GPIO_OUT_PIN30_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN30_Msk

#define GPIO_OUT_PIN30_Msk   (0x1UL << GPIO_OUT_PIN30_Pos)

Bit mask of PIN30 field.

◆ GPIO_OUT_PIN30_Pos

#define GPIO_OUT_PIN30_Pos   (30UL)

Position of PIN30 field.

◆ GPIO_OUT_PIN31_High

#define GPIO_OUT_PIN31_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN31_Low

#define GPIO_OUT_PIN31_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN31_Msk

#define GPIO_OUT_PIN31_Msk   (0x1UL << GPIO_OUT_PIN31_Pos)

Bit mask of PIN31 field.

◆ GPIO_OUT_PIN31_Pos

#define GPIO_OUT_PIN31_Pos   (31UL)

Position of PIN31 field.

◆ GPIO_OUT_PIN3_High

#define GPIO_OUT_PIN3_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN3_Low

#define GPIO_OUT_PIN3_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN3_Msk

#define GPIO_OUT_PIN3_Msk   (0x1UL << GPIO_OUT_PIN3_Pos)

Bit mask of PIN3 field.

◆ GPIO_OUT_PIN3_Pos

#define GPIO_OUT_PIN3_Pos   (3UL)

Position of PIN3 field.

◆ GPIO_OUT_PIN4_High

#define GPIO_OUT_PIN4_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN4_Low

#define GPIO_OUT_PIN4_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN4_Msk

#define GPIO_OUT_PIN4_Msk   (0x1UL << GPIO_OUT_PIN4_Pos)

Bit mask of PIN4 field.

◆ GPIO_OUT_PIN4_Pos

#define GPIO_OUT_PIN4_Pos   (4UL)

Position of PIN4 field.

◆ GPIO_OUT_PIN5_High

#define GPIO_OUT_PIN5_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN5_Low

#define GPIO_OUT_PIN5_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN5_Msk

#define GPIO_OUT_PIN5_Msk   (0x1UL << GPIO_OUT_PIN5_Pos)

Bit mask of PIN5 field.

◆ GPIO_OUT_PIN5_Pos

#define GPIO_OUT_PIN5_Pos   (5UL)

Position of PIN5 field.

◆ GPIO_OUT_PIN6_High

#define GPIO_OUT_PIN6_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN6_Low

#define GPIO_OUT_PIN6_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN6_Msk

#define GPIO_OUT_PIN6_Msk   (0x1UL << GPIO_OUT_PIN6_Pos)

Bit mask of PIN6 field.

◆ GPIO_OUT_PIN6_Pos

#define GPIO_OUT_PIN6_Pos   (6UL)

Position of PIN6 field.

◆ GPIO_OUT_PIN7_High

#define GPIO_OUT_PIN7_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN7_Low

#define GPIO_OUT_PIN7_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN7_Msk

#define GPIO_OUT_PIN7_Msk   (0x1UL << GPIO_OUT_PIN7_Pos)

Bit mask of PIN7 field.

◆ GPIO_OUT_PIN7_Pos

#define GPIO_OUT_PIN7_Pos   (7UL)

Position of PIN7 field.

◆ GPIO_OUT_PIN8_High

#define GPIO_OUT_PIN8_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN8_Low

#define GPIO_OUT_PIN8_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN8_Msk

#define GPIO_OUT_PIN8_Msk   (0x1UL << GPIO_OUT_PIN8_Pos)

Bit mask of PIN8 field.

◆ GPIO_OUT_PIN8_Pos

#define GPIO_OUT_PIN8_Pos   (8UL)

Position of PIN8 field.

◆ GPIO_OUT_PIN9_High

#define GPIO_OUT_PIN9_High   (1UL)

Pin driver is high

◆ GPIO_OUT_PIN9_Low

#define GPIO_OUT_PIN9_Low   (0UL)

Pin driver is low

◆ GPIO_OUT_PIN9_Msk

#define GPIO_OUT_PIN9_Msk   (0x1UL << GPIO_OUT_PIN9_Pos)

Bit mask of PIN9 field.

◆ GPIO_OUT_PIN9_Pos

#define GPIO_OUT_PIN9_Pos   (9UL)

Position of PIN9 field.

◆ GPIO_OUTCLR_PIN0_Clear

#define GPIO_OUTCLR_PIN0_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN0_High

#define GPIO_OUTCLR_PIN0_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN0_Low

#define GPIO_OUTCLR_PIN0_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN0_Msk

#define GPIO_OUTCLR_PIN0_Msk   (0x1UL << GPIO_OUTCLR_PIN0_Pos)

Bit mask of PIN0 field.

◆ GPIO_OUTCLR_PIN0_Pos

#define GPIO_OUTCLR_PIN0_Pos   (0UL)

Position of PIN0 field.

◆ GPIO_OUTCLR_PIN10_Clear

#define GPIO_OUTCLR_PIN10_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN10_High

#define GPIO_OUTCLR_PIN10_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN10_Low

#define GPIO_OUTCLR_PIN10_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN10_Msk

#define GPIO_OUTCLR_PIN10_Msk   (0x1UL << GPIO_OUTCLR_PIN10_Pos)

Bit mask of PIN10 field.

◆ GPIO_OUTCLR_PIN10_Pos

#define GPIO_OUTCLR_PIN10_Pos   (10UL)

Position of PIN10 field.

◆ GPIO_OUTCLR_PIN11_Clear

#define GPIO_OUTCLR_PIN11_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN11_High

#define GPIO_OUTCLR_PIN11_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN11_Low

#define GPIO_OUTCLR_PIN11_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN11_Msk

#define GPIO_OUTCLR_PIN11_Msk   (0x1UL << GPIO_OUTCLR_PIN11_Pos)

Bit mask of PIN11 field.

◆ GPIO_OUTCLR_PIN11_Pos

#define GPIO_OUTCLR_PIN11_Pos   (11UL)

Position of PIN11 field.

◆ GPIO_OUTCLR_PIN12_Clear

#define GPIO_OUTCLR_PIN12_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN12_High

#define GPIO_OUTCLR_PIN12_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN12_Low

#define GPIO_OUTCLR_PIN12_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN12_Msk

#define GPIO_OUTCLR_PIN12_Msk   (0x1UL << GPIO_OUTCLR_PIN12_Pos)

Bit mask of PIN12 field.

◆ GPIO_OUTCLR_PIN12_Pos

#define GPIO_OUTCLR_PIN12_Pos   (12UL)

Position of PIN12 field.

◆ GPIO_OUTCLR_PIN13_Clear

#define GPIO_OUTCLR_PIN13_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN13_High

#define GPIO_OUTCLR_PIN13_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN13_Low

#define GPIO_OUTCLR_PIN13_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN13_Msk

#define GPIO_OUTCLR_PIN13_Msk   (0x1UL << GPIO_OUTCLR_PIN13_Pos)

Bit mask of PIN13 field.

◆ GPIO_OUTCLR_PIN13_Pos

#define GPIO_OUTCLR_PIN13_Pos   (13UL)

Position of PIN13 field.

◆ GPIO_OUTCLR_PIN14_Clear

#define GPIO_OUTCLR_PIN14_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN14_High

#define GPIO_OUTCLR_PIN14_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN14_Low

#define GPIO_OUTCLR_PIN14_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN14_Msk

#define GPIO_OUTCLR_PIN14_Msk   (0x1UL << GPIO_OUTCLR_PIN14_Pos)

Bit mask of PIN14 field.

◆ GPIO_OUTCLR_PIN14_Pos

#define GPIO_OUTCLR_PIN14_Pos   (14UL)

Position of PIN14 field.

◆ GPIO_OUTCLR_PIN15_Clear

#define GPIO_OUTCLR_PIN15_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN15_High

#define GPIO_OUTCLR_PIN15_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN15_Low

#define GPIO_OUTCLR_PIN15_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN15_Msk

#define GPIO_OUTCLR_PIN15_Msk   (0x1UL << GPIO_OUTCLR_PIN15_Pos)

Bit mask of PIN15 field.

◆ GPIO_OUTCLR_PIN15_Pos

#define GPIO_OUTCLR_PIN15_Pos   (15UL)

Position of PIN15 field.

◆ GPIO_OUTCLR_PIN16_Clear

#define GPIO_OUTCLR_PIN16_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN16_High

#define GPIO_OUTCLR_PIN16_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN16_Low

#define GPIO_OUTCLR_PIN16_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN16_Msk

#define GPIO_OUTCLR_PIN16_Msk   (0x1UL << GPIO_OUTCLR_PIN16_Pos)

Bit mask of PIN16 field.

◆ GPIO_OUTCLR_PIN16_Pos

#define GPIO_OUTCLR_PIN16_Pos   (16UL)

Position of PIN16 field.

◆ GPIO_OUTCLR_PIN17_Clear

#define GPIO_OUTCLR_PIN17_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN17_High

#define GPIO_OUTCLR_PIN17_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN17_Low

#define GPIO_OUTCLR_PIN17_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN17_Msk

#define GPIO_OUTCLR_PIN17_Msk   (0x1UL << GPIO_OUTCLR_PIN17_Pos)

Bit mask of PIN17 field.

◆ GPIO_OUTCLR_PIN17_Pos

#define GPIO_OUTCLR_PIN17_Pos   (17UL)

Position of PIN17 field.

◆ GPIO_OUTCLR_PIN18_Clear

#define GPIO_OUTCLR_PIN18_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN18_High

#define GPIO_OUTCLR_PIN18_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN18_Low

#define GPIO_OUTCLR_PIN18_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN18_Msk

#define GPIO_OUTCLR_PIN18_Msk   (0x1UL << GPIO_OUTCLR_PIN18_Pos)

Bit mask of PIN18 field.

◆ GPIO_OUTCLR_PIN18_Pos

#define GPIO_OUTCLR_PIN18_Pos   (18UL)

Position of PIN18 field.

◆ GPIO_OUTCLR_PIN19_Clear

#define GPIO_OUTCLR_PIN19_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN19_High

#define GPIO_OUTCLR_PIN19_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN19_Low

#define GPIO_OUTCLR_PIN19_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN19_Msk

#define GPIO_OUTCLR_PIN19_Msk   (0x1UL << GPIO_OUTCLR_PIN19_Pos)

Bit mask of PIN19 field.

◆ GPIO_OUTCLR_PIN19_Pos

#define GPIO_OUTCLR_PIN19_Pos   (19UL)

Position of PIN19 field.

◆ GPIO_OUTCLR_PIN1_Clear

#define GPIO_OUTCLR_PIN1_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN1_High

#define GPIO_OUTCLR_PIN1_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN1_Low

#define GPIO_OUTCLR_PIN1_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN1_Msk

#define GPIO_OUTCLR_PIN1_Msk   (0x1UL << GPIO_OUTCLR_PIN1_Pos)

Bit mask of PIN1 field.

◆ GPIO_OUTCLR_PIN1_Pos

#define GPIO_OUTCLR_PIN1_Pos   (1UL)

Position of PIN1 field.

◆ GPIO_OUTCLR_PIN20_Clear

#define GPIO_OUTCLR_PIN20_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN20_High

#define GPIO_OUTCLR_PIN20_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN20_Low

#define GPIO_OUTCLR_PIN20_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN20_Msk

#define GPIO_OUTCLR_PIN20_Msk   (0x1UL << GPIO_OUTCLR_PIN20_Pos)

Bit mask of PIN20 field.

◆ GPIO_OUTCLR_PIN20_Pos

#define GPIO_OUTCLR_PIN20_Pos   (20UL)

Position of PIN20 field.

◆ GPIO_OUTCLR_PIN21_Clear

#define GPIO_OUTCLR_PIN21_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN21_High

#define GPIO_OUTCLR_PIN21_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN21_Low

#define GPIO_OUTCLR_PIN21_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN21_Msk

#define GPIO_OUTCLR_PIN21_Msk   (0x1UL << GPIO_OUTCLR_PIN21_Pos)

Bit mask of PIN21 field.

◆ GPIO_OUTCLR_PIN21_Pos

#define GPIO_OUTCLR_PIN21_Pos   (21UL)

Position of PIN21 field.

◆ GPIO_OUTCLR_PIN22_Clear

#define GPIO_OUTCLR_PIN22_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN22_High

#define GPIO_OUTCLR_PIN22_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN22_Low

#define GPIO_OUTCLR_PIN22_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN22_Msk

#define GPIO_OUTCLR_PIN22_Msk   (0x1UL << GPIO_OUTCLR_PIN22_Pos)

Bit mask of PIN22 field.

◆ GPIO_OUTCLR_PIN22_Pos

#define GPIO_OUTCLR_PIN22_Pos   (22UL)

Position of PIN22 field.

◆ GPIO_OUTCLR_PIN23_Clear

#define GPIO_OUTCLR_PIN23_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN23_High

#define GPIO_OUTCLR_PIN23_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN23_Low

#define GPIO_OUTCLR_PIN23_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN23_Msk

#define GPIO_OUTCLR_PIN23_Msk   (0x1UL << GPIO_OUTCLR_PIN23_Pos)

Bit mask of PIN23 field.

◆ GPIO_OUTCLR_PIN23_Pos

#define GPIO_OUTCLR_PIN23_Pos   (23UL)

Position of PIN23 field.

◆ GPIO_OUTCLR_PIN24_Clear

#define GPIO_OUTCLR_PIN24_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN24_High

#define GPIO_OUTCLR_PIN24_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN24_Low

#define GPIO_OUTCLR_PIN24_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN24_Msk

#define GPIO_OUTCLR_PIN24_Msk   (0x1UL << GPIO_OUTCLR_PIN24_Pos)

Bit mask of PIN24 field.

◆ GPIO_OUTCLR_PIN24_Pos

#define GPIO_OUTCLR_PIN24_Pos   (24UL)

Position of PIN24 field.

◆ GPIO_OUTCLR_PIN25_Clear

#define GPIO_OUTCLR_PIN25_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN25_High

#define GPIO_OUTCLR_PIN25_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN25_Low

#define GPIO_OUTCLR_PIN25_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN25_Msk

#define GPIO_OUTCLR_PIN25_Msk   (0x1UL << GPIO_OUTCLR_PIN25_Pos)

Bit mask of PIN25 field.

◆ GPIO_OUTCLR_PIN25_Pos

#define GPIO_OUTCLR_PIN25_Pos   (25UL)

Position of PIN25 field.

◆ GPIO_OUTCLR_PIN26_Clear

#define GPIO_OUTCLR_PIN26_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN26_High

#define GPIO_OUTCLR_PIN26_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN26_Low

#define GPIO_OUTCLR_PIN26_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN26_Msk

#define GPIO_OUTCLR_PIN26_Msk   (0x1UL << GPIO_OUTCLR_PIN26_Pos)

Bit mask of PIN26 field.

◆ GPIO_OUTCLR_PIN26_Pos

#define GPIO_OUTCLR_PIN26_Pos   (26UL)

Position of PIN26 field.

◆ GPIO_OUTCLR_PIN27_Clear

#define GPIO_OUTCLR_PIN27_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN27_High

#define GPIO_OUTCLR_PIN27_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN27_Low

#define GPIO_OUTCLR_PIN27_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN27_Msk

#define GPIO_OUTCLR_PIN27_Msk   (0x1UL << GPIO_OUTCLR_PIN27_Pos)

Bit mask of PIN27 field.

◆ GPIO_OUTCLR_PIN27_Pos

#define GPIO_OUTCLR_PIN27_Pos   (27UL)

Position of PIN27 field.

◆ GPIO_OUTCLR_PIN28_Clear

#define GPIO_OUTCLR_PIN28_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN28_High

#define GPIO_OUTCLR_PIN28_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN28_Low

#define GPIO_OUTCLR_PIN28_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN28_Msk

#define GPIO_OUTCLR_PIN28_Msk   (0x1UL << GPIO_OUTCLR_PIN28_Pos)

Bit mask of PIN28 field.

◆ GPIO_OUTCLR_PIN28_Pos

#define GPIO_OUTCLR_PIN28_Pos   (28UL)

Position of PIN28 field.

◆ GPIO_OUTCLR_PIN29_Clear

#define GPIO_OUTCLR_PIN29_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN29_High

#define GPIO_OUTCLR_PIN29_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN29_Low

#define GPIO_OUTCLR_PIN29_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN29_Msk

#define GPIO_OUTCLR_PIN29_Msk   (0x1UL << GPIO_OUTCLR_PIN29_Pos)

Bit mask of PIN29 field.

◆ GPIO_OUTCLR_PIN29_Pos

#define GPIO_OUTCLR_PIN29_Pos   (29UL)

Position of PIN29 field.

◆ GPIO_OUTCLR_PIN2_Clear

#define GPIO_OUTCLR_PIN2_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN2_High

#define GPIO_OUTCLR_PIN2_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN2_Low

#define GPIO_OUTCLR_PIN2_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN2_Msk

#define GPIO_OUTCLR_PIN2_Msk   (0x1UL << GPIO_OUTCLR_PIN2_Pos)

Bit mask of PIN2 field.

◆ GPIO_OUTCLR_PIN2_Pos

#define GPIO_OUTCLR_PIN2_Pos   (2UL)

Position of PIN2 field.

◆ GPIO_OUTCLR_PIN30_Clear

#define GPIO_OUTCLR_PIN30_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN30_High

#define GPIO_OUTCLR_PIN30_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN30_Low

#define GPIO_OUTCLR_PIN30_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN30_Msk

#define GPIO_OUTCLR_PIN30_Msk   (0x1UL << GPIO_OUTCLR_PIN30_Pos)

Bit mask of PIN30 field.

◆ GPIO_OUTCLR_PIN30_Pos

#define GPIO_OUTCLR_PIN30_Pos   (30UL)

Position of PIN30 field.

◆ GPIO_OUTCLR_PIN31_Clear

#define GPIO_OUTCLR_PIN31_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN31_High

#define GPIO_OUTCLR_PIN31_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN31_Low

#define GPIO_OUTCLR_PIN31_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN31_Msk

#define GPIO_OUTCLR_PIN31_Msk   (0x1UL << GPIO_OUTCLR_PIN31_Pos)

Bit mask of PIN31 field.

◆ GPIO_OUTCLR_PIN31_Pos

#define GPIO_OUTCLR_PIN31_Pos   (31UL)

Position of PIN31 field.

◆ GPIO_OUTCLR_PIN3_Clear

#define GPIO_OUTCLR_PIN3_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN3_High

#define GPIO_OUTCLR_PIN3_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN3_Low

#define GPIO_OUTCLR_PIN3_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN3_Msk

#define GPIO_OUTCLR_PIN3_Msk   (0x1UL << GPIO_OUTCLR_PIN3_Pos)

Bit mask of PIN3 field.

◆ GPIO_OUTCLR_PIN3_Pos

#define GPIO_OUTCLR_PIN3_Pos   (3UL)

Position of PIN3 field.

◆ GPIO_OUTCLR_PIN4_Clear

#define GPIO_OUTCLR_PIN4_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN4_High

#define GPIO_OUTCLR_PIN4_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN4_Low

#define GPIO_OUTCLR_PIN4_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN4_Msk

#define GPIO_OUTCLR_PIN4_Msk   (0x1UL << GPIO_OUTCLR_PIN4_Pos)

Bit mask of PIN4 field.

◆ GPIO_OUTCLR_PIN4_Pos

#define GPIO_OUTCLR_PIN4_Pos   (4UL)

Position of PIN4 field.

◆ GPIO_OUTCLR_PIN5_Clear

#define GPIO_OUTCLR_PIN5_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN5_High

#define GPIO_OUTCLR_PIN5_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN5_Low

#define GPIO_OUTCLR_PIN5_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN5_Msk

#define GPIO_OUTCLR_PIN5_Msk   (0x1UL << GPIO_OUTCLR_PIN5_Pos)

Bit mask of PIN5 field.

◆ GPIO_OUTCLR_PIN5_Pos

#define GPIO_OUTCLR_PIN5_Pos   (5UL)

Position of PIN5 field.

◆ GPIO_OUTCLR_PIN6_Clear

#define GPIO_OUTCLR_PIN6_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN6_High

#define GPIO_OUTCLR_PIN6_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN6_Low

#define GPIO_OUTCLR_PIN6_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN6_Msk

#define GPIO_OUTCLR_PIN6_Msk   (0x1UL << GPIO_OUTCLR_PIN6_Pos)

Bit mask of PIN6 field.

◆ GPIO_OUTCLR_PIN6_Pos

#define GPIO_OUTCLR_PIN6_Pos   (6UL)

Position of PIN6 field.

◆ GPIO_OUTCLR_PIN7_Clear

#define GPIO_OUTCLR_PIN7_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN7_High

#define GPIO_OUTCLR_PIN7_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN7_Low

#define GPIO_OUTCLR_PIN7_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN7_Msk

#define GPIO_OUTCLR_PIN7_Msk   (0x1UL << GPIO_OUTCLR_PIN7_Pos)

Bit mask of PIN7 field.

◆ GPIO_OUTCLR_PIN7_Pos

#define GPIO_OUTCLR_PIN7_Pos   (7UL)

Position of PIN7 field.

◆ GPIO_OUTCLR_PIN8_Clear

#define GPIO_OUTCLR_PIN8_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN8_High

#define GPIO_OUTCLR_PIN8_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN8_Low

#define GPIO_OUTCLR_PIN8_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN8_Msk

#define GPIO_OUTCLR_PIN8_Msk   (0x1UL << GPIO_OUTCLR_PIN8_Pos)

Bit mask of PIN8 field.

◆ GPIO_OUTCLR_PIN8_Pos

#define GPIO_OUTCLR_PIN8_Pos   (8UL)

Position of PIN8 field.

◆ GPIO_OUTCLR_PIN9_Clear

#define GPIO_OUTCLR_PIN9_Clear   (1UL)

Write: writing a '1' sets the pin low; writing a '0' has no effect

◆ GPIO_OUTCLR_PIN9_High

#define GPIO_OUTCLR_PIN9_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTCLR_PIN9_Low

#define GPIO_OUTCLR_PIN9_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTCLR_PIN9_Msk

#define GPIO_OUTCLR_PIN9_Msk   (0x1UL << GPIO_OUTCLR_PIN9_Pos)

Bit mask of PIN9 field.

◆ GPIO_OUTCLR_PIN9_Pos

#define GPIO_OUTCLR_PIN9_Pos   (9UL)

Position of PIN9 field.

◆ GPIO_OUTSET_PIN0_High

#define GPIO_OUTSET_PIN0_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN0_Low

#define GPIO_OUTSET_PIN0_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN0_Msk

#define GPIO_OUTSET_PIN0_Msk   (0x1UL << GPIO_OUTSET_PIN0_Pos)

Bit mask of PIN0 field.

◆ GPIO_OUTSET_PIN0_Pos

#define GPIO_OUTSET_PIN0_Pos   (0UL)

Position of PIN0 field.

◆ GPIO_OUTSET_PIN0_Set

#define GPIO_OUTSET_PIN0_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN10_High

#define GPIO_OUTSET_PIN10_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN10_Low

#define GPIO_OUTSET_PIN10_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN10_Msk

#define GPIO_OUTSET_PIN10_Msk   (0x1UL << GPIO_OUTSET_PIN10_Pos)

Bit mask of PIN10 field.

◆ GPIO_OUTSET_PIN10_Pos

#define GPIO_OUTSET_PIN10_Pos   (10UL)

Position of PIN10 field.

◆ GPIO_OUTSET_PIN10_Set

#define GPIO_OUTSET_PIN10_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN11_High

#define GPIO_OUTSET_PIN11_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN11_Low

#define GPIO_OUTSET_PIN11_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN11_Msk

#define GPIO_OUTSET_PIN11_Msk   (0x1UL << GPIO_OUTSET_PIN11_Pos)

Bit mask of PIN11 field.

◆ GPIO_OUTSET_PIN11_Pos

#define GPIO_OUTSET_PIN11_Pos   (11UL)

Position of PIN11 field.

◆ GPIO_OUTSET_PIN11_Set

#define GPIO_OUTSET_PIN11_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN12_High

#define GPIO_OUTSET_PIN12_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN12_Low

#define GPIO_OUTSET_PIN12_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN12_Msk

#define GPIO_OUTSET_PIN12_Msk   (0x1UL << GPIO_OUTSET_PIN12_Pos)

Bit mask of PIN12 field.

◆ GPIO_OUTSET_PIN12_Pos

#define GPIO_OUTSET_PIN12_Pos   (12UL)

Position of PIN12 field.

◆ GPIO_OUTSET_PIN12_Set

#define GPIO_OUTSET_PIN12_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN13_High

#define GPIO_OUTSET_PIN13_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN13_Low

#define GPIO_OUTSET_PIN13_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN13_Msk

#define GPIO_OUTSET_PIN13_Msk   (0x1UL << GPIO_OUTSET_PIN13_Pos)

Bit mask of PIN13 field.

◆ GPIO_OUTSET_PIN13_Pos

#define GPIO_OUTSET_PIN13_Pos   (13UL)

Position of PIN13 field.

◆ GPIO_OUTSET_PIN13_Set

#define GPIO_OUTSET_PIN13_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN14_High

#define GPIO_OUTSET_PIN14_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN14_Low

#define GPIO_OUTSET_PIN14_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN14_Msk

#define GPIO_OUTSET_PIN14_Msk   (0x1UL << GPIO_OUTSET_PIN14_Pos)

Bit mask of PIN14 field.

◆ GPIO_OUTSET_PIN14_Pos

#define GPIO_OUTSET_PIN14_Pos   (14UL)

Position of PIN14 field.

◆ GPIO_OUTSET_PIN14_Set

#define GPIO_OUTSET_PIN14_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN15_High

#define GPIO_OUTSET_PIN15_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN15_Low

#define GPIO_OUTSET_PIN15_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN15_Msk

#define GPIO_OUTSET_PIN15_Msk   (0x1UL << GPIO_OUTSET_PIN15_Pos)

Bit mask of PIN15 field.

◆ GPIO_OUTSET_PIN15_Pos

#define GPIO_OUTSET_PIN15_Pos   (15UL)

Position of PIN15 field.

◆ GPIO_OUTSET_PIN15_Set

#define GPIO_OUTSET_PIN15_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN16_High

#define GPIO_OUTSET_PIN16_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN16_Low

#define GPIO_OUTSET_PIN16_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN16_Msk

#define GPIO_OUTSET_PIN16_Msk   (0x1UL << GPIO_OUTSET_PIN16_Pos)

Bit mask of PIN16 field.

◆ GPIO_OUTSET_PIN16_Pos

#define GPIO_OUTSET_PIN16_Pos   (16UL)

Position of PIN16 field.

◆ GPIO_OUTSET_PIN16_Set

#define GPIO_OUTSET_PIN16_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN17_High

#define GPIO_OUTSET_PIN17_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN17_Low

#define GPIO_OUTSET_PIN17_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN17_Msk

#define GPIO_OUTSET_PIN17_Msk   (0x1UL << GPIO_OUTSET_PIN17_Pos)

Bit mask of PIN17 field.

◆ GPIO_OUTSET_PIN17_Pos

#define GPIO_OUTSET_PIN17_Pos   (17UL)

Position of PIN17 field.

◆ GPIO_OUTSET_PIN17_Set

#define GPIO_OUTSET_PIN17_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN18_High

#define GPIO_OUTSET_PIN18_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN18_Low

#define GPIO_OUTSET_PIN18_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN18_Msk

#define GPIO_OUTSET_PIN18_Msk   (0x1UL << GPIO_OUTSET_PIN18_Pos)

Bit mask of PIN18 field.

◆ GPIO_OUTSET_PIN18_Pos

#define GPIO_OUTSET_PIN18_Pos   (18UL)

Position of PIN18 field.

◆ GPIO_OUTSET_PIN18_Set

#define GPIO_OUTSET_PIN18_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN19_High

#define GPIO_OUTSET_PIN19_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN19_Low

#define GPIO_OUTSET_PIN19_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN19_Msk

#define GPIO_OUTSET_PIN19_Msk   (0x1UL << GPIO_OUTSET_PIN19_Pos)

Bit mask of PIN19 field.

◆ GPIO_OUTSET_PIN19_Pos

#define GPIO_OUTSET_PIN19_Pos   (19UL)

Position of PIN19 field.

◆ GPIO_OUTSET_PIN19_Set

#define GPIO_OUTSET_PIN19_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN1_High

#define GPIO_OUTSET_PIN1_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN1_Low

#define GPIO_OUTSET_PIN1_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN1_Msk

#define GPIO_OUTSET_PIN1_Msk   (0x1UL << GPIO_OUTSET_PIN1_Pos)

Bit mask of PIN1 field.

◆ GPIO_OUTSET_PIN1_Pos

#define GPIO_OUTSET_PIN1_Pos   (1UL)

Position of PIN1 field.

◆ GPIO_OUTSET_PIN1_Set

#define GPIO_OUTSET_PIN1_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN20_High

#define GPIO_OUTSET_PIN20_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN20_Low

#define GPIO_OUTSET_PIN20_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN20_Msk

#define GPIO_OUTSET_PIN20_Msk   (0x1UL << GPIO_OUTSET_PIN20_Pos)

Bit mask of PIN20 field.

◆ GPIO_OUTSET_PIN20_Pos

#define GPIO_OUTSET_PIN20_Pos   (20UL)

Position of PIN20 field.

◆ GPIO_OUTSET_PIN20_Set

#define GPIO_OUTSET_PIN20_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN21_High

#define GPIO_OUTSET_PIN21_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN21_Low

#define GPIO_OUTSET_PIN21_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN21_Msk

#define GPIO_OUTSET_PIN21_Msk   (0x1UL << GPIO_OUTSET_PIN21_Pos)

Bit mask of PIN21 field.

◆ GPIO_OUTSET_PIN21_Pos

#define GPIO_OUTSET_PIN21_Pos   (21UL)

Position of PIN21 field.

◆ GPIO_OUTSET_PIN21_Set

#define GPIO_OUTSET_PIN21_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN22_High

#define GPIO_OUTSET_PIN22_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN22_Low

#define GPIO_OUTSET_PIN22_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN22_Msk

#define GPIO_OUTSET_PIN22_Msk   (0x1UL << GPIO_OUTSET_PIN22_Pos)

Bit mask of PIN22 field.

◆ GPIO_OUTSET_PIN22_Pos

#define GPIO_OUTSET_PIN22_Pos   (22UL)

Position of PIN22 field.

◆ GPIO_OUTSET_PIN22_Set

#define GPIO_OUTSET_PIN22_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN23_High

#define GPIO_OUTSET_PIN23_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN23_Low

#define GPIO_OUTSET_PIN23_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN23_Msk

#define GPIO_OUTSET_PIN23_Msk   (0x1UL << GPIO_OUTSET_PIN23_Pos)

Bit mask of PIN23 field.

◆ GPIO_OUTSET_PIN23_Pos

#define GPIO_OUTSET_PIN23_Pos   (23UL)

Position of PIN23 field.

◆ GPIO_OUTSET_PIN23_Set

#define GPIO_OUTSET_PIN23_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN24_High

#define GPIO_OUTSET_PIN24_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN24_Low

#define GPIO_OUTSET_PIN24_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN24_Msk

#define GPIO_OUTSET_PIN24_Msk   (0x1UL << GPIO_OUTSET_PIN24_Pos)

Bit mask of PIN24 field.

◆ GPIO_OUTSET_PIN24_Pos

#define GPIO_OUTSET_PIN24_Pos   (24UL)

Position of PIN24 field.

◆ GPIO_OUTSET_PIN24_Set

#define GPIO_OUTSET_PIN24_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN25_High

#define GPIO_OUTSET_PIN25_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN25_Low

#define GPIO_OUTSET_PIN25_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN25_Msk

#define GPIO_OUTSET_PIN25_Msk   (0x1UL << GPIO_OUTSET_PIN25_Pos)

Bit mask of PIN25 field.

◆ GPIO_OUTSET_PIN25_Pos

#define GPIO_OUTSET_PIN25_Pos   (25UL)

Position of PIN25 field.

◆ GPIO_OUTSET_PIN25_Set

#define GPIO_OUTSET_PIN25_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN26_High

#define GPIO_OUTSET_PIN26_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN26_Low

#define GPIO_OUTSET_PIN26_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN26_Msk

#define GPIO_OUTSET_PIN26_Msk   (0x1UL << GPIO_OUTSET_PIN26_Pos)

Bit mask of PIN26 field.

◆ GPIO_OUTSET_PIN26_Pos

#define GPIO_OUTSET_PIN26_Pos   (26UL)

Position of PIN26 field.

◆ GPIO_OUTSET_PIN26_Set

#define GPIO_OUTSET_PIN26_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN27_High

#define GPIO_OUTSET_PIN27_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN27_Low

#define GPIO_OUTSET_PIN27_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN27_Msk

#define GPIO_OUTSET_PIN27_Msk   (0x1UL << GPIO_OUTSET_PIN27_Pos)

Bit mask of PIN27 field.

◆ GPIO_OUTSET_PIN27_Pos

#define GPIO_OUTSET_PIN27_Pos   (27UL)

Position of PIN27 field.

◆ GPIO_OUTSET_PIN27_Set

#define GPIO_OUTSET_PIN27_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN28_High

#define GPIO_OUTSET_PIN28_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN28_Low

#define GPIO_OUTSET_PIN28_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN28_Msk

#define GPIO_OUTSET_PIN28_Msk   (0x1UL << GPIO_OUTSET_PIN28_Pos)

Bit mask of PIN28 field.

◆ GPIO_OUTSET_PIN28_Pos

#define GPIO_OUTSET_PIN28_Pos   (28UL)

Position of PIN28 field.

◆ GPIO_OUTSET_PIN28_Set

#define GPIO_OUTSET_PIN28_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN29_High

#define GPIO_OUTSET_PIN29_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN29_Low

#define GPIO_OUTSET_PIN29_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN29_Msk

#define GPIO_OUTSET_PIN29_Msk   (0x1UL << GPIO_OUTSET_PIN29_Pos)

Bit mask of PIN29 field.

◆ GPIO_OUTSET_PIN29_Pos

#define GPIO_OUTSET_PIN29_Pos   (29UL)

Position of PIN29 field.

◆ GPIO_OUTSET_PIN29_Set

#define GPIO_OUTSET_PIN29_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN2_High

#define GPIO_OUTSET_PIN2_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN2_Low

#define GPIO_OUTSET_PIN2_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN2_Msk

#define GPIO_OUTSET_PIN2_Msk   (0x1UL << GPIO_OUTSET_PIN2_Pos)

Bit mask of PIN2 field.

◆ GPIO_OUTSET_PIN2_Pos

#define GPIO_OUTSET_PIN2_Pos   (2UL)

Position of PIN2 field.

◆ GPIO_OUTSET_PIN2_Set

#define GPIO_OUTSET_PIN2_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN30_High

#define GPIO_OUTSET_PIN30_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN30_Low

#define GPIO_OUTSET_PIN30_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN30_Msk

#define GPIO_OUTSET_PIN30_Msk   (0x1UL << GPIO_OUTSET_PIN30_Pos)

Bit mask of PIN30 field.

◆ GPIO_OUTSET_PIN30_Pos

#define GPIO_OUTSET_PIN30_Pos   (30UL)

Position of PIN30 field.

◆ GPIO_OUTSET_PIN30_Set

#define GPIO_OUTSET_PIN30_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN31_High

#define GPIO_OUTSET_PIN31_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN31_Low

#define GPIO_OUTSET_PIN31_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN31_Msk

#define GPIO_OUTSET_PIN31_Msk   (0x1UL << GPIO_OUTSET_PIN31_Pos)

Bit mask of PIN31 field.

◆ GPIO_OUTSET_PIN31_Pos

#define GPIO_OUTSET_PIN31_Pos   (31UL)

Position of PIN31 field.

◆ GPIO_OUTSET_PIN31_Set

#define GPIO_OUTSET_PIN31_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN3_High

#define GPIO_OUTSET_PIN3_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN3_Low

#define GPIO_OUTSET_PIN3_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN3_Msk

#define GPIO_OUTSET_PIN3_Msk   (0x1UL << GPIO_OUTSET_PIN3_Pos)

Bit mask of PIN3 field.

◆ GPIO_OUTSET_PIN3_Pos

#define GPIO_OUTSET_PIN3_Pos   (3UL)

Position of PIN3 field.

◆ GPIO_OUTSET_PIN3_Set

#define GPIO_OUTSET_PIN3_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN4_High

#define GPIO_OUTSET_PIN4_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN4_Low

#define GPIO_OUTSET_PIN4_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN4_Msk

#define GPIO_OUTSET_PIN4_Msk   (0x1UL << GPIO_OUTSET_PIN4_Pos)

Bit mask of PIN4 field.

◆ GPIO_OUTSET_PIN4_Pos

#define GPIO_OUTSET_PIN4_Pos   (4UL)

Position of PIN4 field.

◆ GPIO_OUTSET_PIN4_Set

#define GPIO_OUTSET_PIN4_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN5_High

#define GPIO_OUTSET_PIN5_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN5_Low

#define GPIO_OUTSET_PIN5_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN5_Msk

#define GPIO_OUTSET_PIN5_Msk   (0x1UL << GPIO_OUTSET_PIN5_Pos)

Bit mask of PIN5 field.

◆ GPIO_OUTSET_PIN5_Pos

#define GPIO_OUTSET_PIN5_Pos   (5UL)

Position of PIN5 field.

◆ GPIO_OUTSET_PIN5_Set

#define GPIO_OUTSET_PIN5_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN6_High

#define GPIO_OUTSET_PIN6_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN6_Low

#define GPIO_OUTSET_PIN6_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN6_Msk

#define GPIO_OUTSET_PIN6_Msk   (0x1UL << GPIO_OUTSET_PIN6_Pos)

Bit mask of PIN6 field.

◆ GPIO_OUTSET_PIN6_Pos

#define GPIO_OUTSET_PIN6_Pos   (6UL)

Position of PIN6 field.

◆ GPIO_OUTSET_PIN6_Set

#define GPIO_OUTSET_PIN6_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN7_High

#define GPIO_OUTSET_PIN7_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN7_Low

#define GPIO_OUTSET_PIN7_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN7_Msk

#define GPIO_OUTSET_PIN7_Msk   (0x1UL << GPIO_OUTSET_PIN7_Pos)

Bit mask of PIN7 field.

◆ GPIO_OUTSET_PIN7_Pos

#define GPIO_OUTSET_PIN7_Pos   (7UL)

Position of PIN7 field.

◆ GPIO_OUTSET_PIN7_Set

#define GPIO_OUTSET_PIN7_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN8_High

#define GPIO_OUTSET_PIN8_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN8_Low

#define GPIO_OUTSET_PIN8_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN8_Msk

#define GPIO_OUTSET_PIN8_Msk   (0x1UL << GPIO_OUTSET_PIN8_Pos)

Bit mask of PIN8 field.

◆ GPIO_OUTSET_PIN8_Pos

#define GPIO_OUTSET_PIN8_Pos   (8UL)

Position of PIN8 field.

◆ GPIO_OUTSET_PIN8_Set

#define GPIO_OUTSET_PIN8_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_OUTSET_PIN9_High

#define GPIO_OUTSET_PIN9_High   (1UL)

Read: pin driver is high

◆ GPIO_OUTSET_PIN9_Low

#define GPIO_OUTSET_PIN9_Low   (0UL)

Read: pin driver is low

◆ GPIO_OUTSET_PIN9_Msk

#define GPIO_OUTSET_PIN9_Msk   (0x1UL << GPIO_OUTSET_PIN9_Pos)

Bit mask of PIN9 field.

◆ GPIO_OUTSET_PIN9_Pos

#define GPIO_OUTSET_PIN9_Pos   (9UL)

Position of PIN9 field.

◆ GPIO_OUTSET_PIN9_Set

#define GPIO_OUTSET_PIN9_Set   (1UL)

Write: writing a '1' sets the pin high; writing a '0' has no effect

◆ GPIO_PIN_CNF_DIR_Input

#define GPIO_PIN_CNF_DIR_Input   (0UL)

Configure pin as an input pin

◆ GPIO_PIN_CNF_DIR_Msk

#define GPIO_PIN_CNF_DIR_Msk   (0x1UL << GPIO_PIN_CNF_DIR_Pos)

Bit mask of DIR field.

◆ GPIO_PIN_CNF_DIR_Output

#define GPIO_PIN_CNF_DIR_Output   (1UL)

Configure pin as an output pin

◆ GPIO_PIN_CNF_DIR_Pos

#define GPIO_PIN_CNF_DIR_Pos   (0UL)

Position of DIR field.

◆ GPIO_PIN_CNF_DRIVE_D0H1

#define GPIO_PIN_CNF_DRIVE_D0H1   (5UL)

Disconnect '0', high drive '1' (normally used for wired-or connections)

◆ GPIO_PIN_CNF_DRIVE_D0S1

#define GPIO_PIN_CNF_DRIVE_D0S1   (4UL)

Disconnect '0' standard '1' (normally used for wired-or connections)

◆ GPIO_PIN_CNF_DRIVE_H0D1

#define GPIO_PIN_CNF_DRIVE_H0D1   (7UL)

High drive '0', disconnect '1' (normally used for wired-and connections)

◆ GPIO_PIN_CNF_DRIVE_H0H1

#define GPIO_PIN_CNF_DRIVE_H0H1   (3UL)

High drive '0', high 'drive '1''

◆ GPIO_PIN_CNF_DRIVE_H0S1

#define GPIO_PIN_CNF_DRIVE_H0S1   (1UL)

High drive '0', standard '1'

◆ GPIO_PIN_CNF_DRIVE_Msk

#define GPIO_PIN_CNF_DRIVE_Msk   (0x7UL << GPIO_PIN_CNF_DRIVE_Pos)

Bit mask of DRIVE field.

◆ GPIO_PIN_CNF_DRIVE_Pos

#define GPIO_PIN_CNF_DRIVE_Pos   (8UL)

Position of DRIVE field.

◆ GPIO_PIN_CNF_DRIVE_S0D1

#define GPIO_PIN_CNF_DRIVE_S0D1   (6UL)

Standard '0'. disconnect '1' (normally used for wired-and connections)

◆ GPIO_PIN_CNF_DRIVE_S0H1

#define GPIO_PIN_CNF_DRIVE_S0H1   (2UL)

Standard '0', high drive '1'

◆ GPIO_PIN_CNF_DRIVE_S0S1

#define GPIO_PIN_CNF_DRIVE_S0S1   (0UL)

Standard '0', standard '1'

◆ GPIO_PIN_CNF_INPUT_Connect

#define GPIO_PIN_CNF_INPUT_Connect   (0UL)

Connect input buffer

◆ GPIO_PIN_CNF_INPUT_Disconnect

#define GPIO_PIN_CNF_INPUT_Disconnect   (1UL)

Disconnect input buffer

◆ GPIO_PIN_CNF_INPUT_Msk

#define GPIO_PIN_CNF_INPUT_Msk   (0x1UL << GPIO_PIN_CNF_INPUT_Pos)

Bit mask of INPUT field.

◆ GPIO_PIN_CNF_INPUT_Pos

#define GPIO_PIN_CNF_INPUT_Pos   (1UL)

Position of INPUT field.

◆ GPIO_PIN_CNF_PULL_Disabled

#define GPIO_PIN_CNF_PULL_Disabled   (0UL)

No pull

◆ GPIO_PIN_CNF_PULL_Msk

#define GPIO_PIN_CNF_PULL_Msk   (0x3UL << GPIO_PIN_CNF_PULL_Pos)

Bit mask of PULL field.

◆ GPIO_PIN_CNF_PULL_Pos

#define GPIO_PIN_CNF_PULL_Pos   (2UL)

Position of PULL field.

◆ GPIO_PIN_CNF_PULL_Pulldown

#define GPIO_PIN_CNF_PULL_Pulldown   (1UL)

Pull down on pin

◆ GPIO_PIN_CNF_PULL_Pullup

#define GPIO_PIN_CNF_PULL_Pullup   (3UL)

Pull up on pin

◆ GPIO_PIN_CNF_SENSE_Disabled

#define GPIO_PIN_CNF_SENSE_Disabled   (0UL)

Disabled

◆ GPIO_PIN_CNF_SENSE_High

#define GPIO_PIN_CNF_SENSE_High   (2UL)

Sense for high level

◆ GPIO_PIN_CNF_SENSE_Low

#define GPIO_PIN_CNF_SENSE_Low   (3UL)

Sense for low level

◆ GPIO_PIN_CNF_SENSE_Msk

#define GPIO_PIN_CNF_SENSE_Msk   (0x3UL << GPIO_PIN_CNF_SENSE_Pos)

Bit mask of SENSE field.

◆ GPIO_PIN_CNF_SENSE_Pos

#define GPIO_PIN_CNF_SENSE_Pos   (16UL)

Position of SENSE field.

◆ GPIOTE_CONFIG_MODE_Disabled

#define GPIOTE_CONFIG_MODE_Disabled   (0UL)

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

◆ GPIOTE_CONFIG_MODE_Event

#define GPIOTE_CONFIG_MODE_Event   (1UL)

Event mode

◆ GPIOTE_CONFIG_MODE_Msk

#define GPIOTE_CONFIG_MODE_Msk   (0x3UL << GPIOTE_CONFIG_MODE_Pos)

Bit mask of MODE field.

◆ GPIOTE_CONFIG_MODE_Pos

#define GPIOTE_CONFIG_MODE_Pos   (0UL)

Position of MODE field.

◆ GPIOTE_CONFIG_MODE_Task

#define GPIOTE_CONFIG_MODE_Task   (3UL)

Task mode

◆ GPIOTE_CONFIG_OUTINIT_High

#define GPIOTE_CONFIG_OUTINIT_High   (1UL)

Task mode: Initial value of pin before task triggering is high

◆ GPIOTE_CONFIG_OUTINIT_Low

#define GPIOTE_CONFIG_OUTINIT_Low   (0UL)

Task mode: Initial value of pin before task triggering is low

◆ GPIOTE_CONFIG_OUTINIT_Msk

#define GPIOTE_CONFIG_OUTINIT_Msk   (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos)

Bit mask of OUTINIT field.

◆ GPIOTE_CONFIG_OUTINIT_Pos

#define GPIOTE_CONFIG_OUTINIT_Pos   (20UL)

Position of OUTINIT field.

◆ GPIOTE_CONFIG_POLARITY_HiToLo

#define GPIOTE_CONFIG_POLARITY_HiToLo   (2UL)

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

◆ GPIOTE_CONFIG_POLARITY_LoToHi

#define GPIOTE_CONFIG_POLARITY_LoToHi   (1UL)

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

◆ GPIOTE_CONFIG_POLARITY_Msk

#define GPIOTE_CONFIG_POLARITY_Msk   (0x3UL << GPIOTE_CONFIG_POLARITY_Pos)

Bit mask of POLARITY field.

◆ GPIOTE_CONFIG_POLARITY_None

#define GPIOTE_CONFIG_POLARITY_None   (0UL)

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

◆ GPIOTE_CONFIG_POLARITY_Pos

#define GPIOTE_CONFIG_POLARITY_Pos   (16UL)

Position of POLARITY field.

◆ GPIOTE_CONFIG_POLARITY_Toggle

#define GPIOTE_CONFIG_POLARITY_Toggle   (3UL)

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

◆ GPIOTE_CONFIG_PSEL_Msk

#define GPIOTE_CONFIG_PSEL_Msk   (0x1FUL << GPIOTE_CONFIG_PSEL_Pos)

Bit mask of PSEL field.

◆ GPIOTE_CONFIG_PSEL_Pos

#define GPIOTE_CONFIG_PSEL_Pos   (8UL)

Position of PSEL field.

◆ GPIOTE_INTENCLR_IN0_Clear

#define GPIOTE_INTENCLR_IN0_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_IN0_Disabled

#define GPIOTE_INTENCLR_IN0_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_IN0_Enabled

#define GPIOTE_INTENCLR_IN0_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_IN0_Msk

#define GPIOTE_INTENCLR_IN0_Msk   (0x1UL << GPIOTE_INTENCLR_IN0_Pos)

Bit mask of IN0 field.

◆ GPIOTE_INTENCLR_IN0_Pos

#define GPIOTE_INTENCLR_IN0_Pos   (0UL)

Position of IN0 field.

◆ GPIOTE_INTENCLR_IN1_Clear

#define GPIOTE_INTENCLR_IN1_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_IN1_Disabled

#define GPIOTE_INTENCLR_IN1_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_IN1_Enabled

#define GPIOTE_INTENCLR_IN1_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_IN1_Msk

#define GPIOTE_INTENCLR_IN1_Msk   (0x1UL << GPIOTE_INTENCLR_IN1_Pos)

Bit mask of IN1 field.

◆ GPIOTE_INTENCLR_IN1_Pos

#define GPIOTE_INTENCLR_IN1_Pos   (1UL)

Position of IN1 field.

◆ GPIOTE_INTENCLR_IN2_Clear

#define GPIOTE_INTENCLR_IN2_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_IN2_Disabled

#define GPIOTE_INTENCLR_IN2_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_IN2_Enabled

#define GPIOTE_INTENCLR_IN2_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_IN2_Msk

#define GPIOTE_INTENCLR_IN2_Msk   (0x1UL << GPIOTE_INTENCLR_IN2_Pos)

Bit mask of IN2 field.

◆ GPIOTE_INTENCLR_IN2_Pos

#define GPIOTE_INTENCLR_IN2_Pos   (2UL)

Position of IN2 field.

◆ GPIOTE_INTENCLR_IN3_Clear

#define GPIOTE_INTENCLR_IN3_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_IN3_Disabled

#define GPIOTE_INTENCLR_IN3_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_IN3_Enabled

#define GPIOTE_INTENCLR_IN3_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_IN3_Msk

#define GPIOTE_INTENCLR_IN3_Msk   (0x1UL << GPIOTE_INTENCLR_IN3_Pos)

Bit mask of IN3 field.

◆ GPIOTE_INTENCLR_IN3_Pos

#define GPIOTE_INTENCLR_IN3_Pos   (3UL)

Position of IN3 field.

◆ GPIOTE_INTENCLR_IN4_Clear

#define GPIOTE_INTENCLR_IN4_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_IN4_Disabled

#define GPIOTE_INTENCLR_IN4_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_IN4_Enabled

#define GPIOTE_INTENCLR_IN4_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_IN4_Msk

#define GPIOTE_INTENCLR_IN4_Msk   (0x1UL << GPIOTE_INTENCLR_IN4_Pos)

Bit mask of IN4 field.

◆ GPIOTE_INTENCLR_IN4_Pos

#define GPIOTE_INTENCLR_IN4_Pos   (4UL)

Position of IN4 field.

◆ GPIOTE_INTENCLR_IN5_Clear

#define GPIOTE_INTENCLR_IN5_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_IN5_Disabled

#define GPIOTE_INTENCLR_IN5_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_IN5_Enabled

#define GPIOTE_INTENCLR_IN5_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_IN5_Msk

#define GPIOTE_INTENCLR_IN5_Msk   (0x1UL << GPIOTE_INTENCLR_IN5_Pos)

Bit mask of IN5 field.

◆ GPIOTE_INTENCLR_IN5_Pos

#define GPIOTE_INTENCLR_IN5_Pos   (5UL)

Position of IN5 field.

◆ GPIOTE_INTENCLR_IN6_Clear

#define GPIOTE_INTENCLR_IN6_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_IN6_Disabled

#define GPIOTE_INTENCLR_IN6_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_IN6_Enabled

#define GPIOTE_INTENCLR_IN6_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_IN6_Msk

#define GPIOTE_INTENCLR_IN6_Msk   (0x1UL << GPIOTE_INTENCLR_IN6_Pos)

Bit mask of IN6 field.

◆ GPIOTE_INTENCLR_IN6_Pos

#define GPIOTE_INTENCLR_IN6_Pos   (6UL)

Position of IN6 field.

◆ GPIOTE_INTENCLR_IN7_Clear

#define GPIOTE_INTENCLR_IN7_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_IN7_Disabled

#define GPIOTE_INTENCLR_IN7_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_IN7_Enabled

#define GPIOTE_INTENCLR_IN7_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_IN7_Msk

#define GPIOTE_INTENCLR_IN7_Msk   (0x1UL << GPIOTE_INTENCLR_IN7_Pos)

Bit mask of IN7 field.

◆ GPIOTE_INTENCLR_IN7_Pos

#define GPIOTE_INTENCLR_IN7_Pos   (7UL)

Position of IN7 field.

◆ GPIOTE_INTENCLR_PORT_Clear

#define GPIOTE_INTENCLR_PORT_Clear   (1UL)

Disable

◆ GPIOTE_INTENCLR_PORT_Disabled

#define GPIOTE_INTENCLR_PORT_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENCLR_PORT_Enabled

#define GPIOTE_INTENCLR_PORT_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENCLR_PORT_Msk

#define GPIOTE_INTENCLR_PORT_Msk   (0x1UL << GPIOTE_INTENCLR_PORT_Pos)

Bit mask of PORT field.

◆ GPIOTE_INTENCLR_PORT_Pos

#define GPIOTE_INTENCLR_PORT_Pos   (31UL)

Position of PORT field.

◆ GPIOTE_INTENSET_IN0_Disabled

#define GPIOTE_INTENSET_IN0_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_IN0_Enabled

#define GPIOTE_INTENSET_IN0_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_IN0_Msk

#define GPIOTE_INTENSET_IN0_Msk   (0x1UL << GPIOTE_INTENSET_IN0_Pos)

Bit mask of IN0 field.

◆ GPIOTE_INTENSET_IN0_Pos

#define GPIOTE_INTENSET_IN0_Pos   (0UL)

Position of IN0 field.

◆ GPIOTE_INTENSET_IN0_Set

#define GPIOTE_INTENSET_IN0_Set   (1UL)

Enable

◆ GPIOTE_INTENSET_IN1_Disabled

#define GPIOTE_INTENSET_IN1_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_IN1_Enabled

#define GPIOTE_INTENSET_IN1_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_IN1_Msk

#define GPIOTE_INTENSET_IN1_Msk   (0x1UL << GPIOTE_INTENSET_IN1_Pos)

Bit mask of IN1 field.

◆ GPIOTE_INTENSET_IN1_Pos

#define GPIOTE_INTENSET_IN1_Pos   (1UL)

Position of IN1 field.

◆ GPIOTE_INTENSET_IN1_Set

#define GPIOTE_INTENSET_IN1_Set   (1UL)

Enable

◆ GPIOTE_INTENSET_IN2_Disabled

#define GPIOTE_INTENSET_IN2_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_IN2_Enabled

#define GPIOTE_INTENSET_IN2_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_IN2_Msk

#define GPIOTE_INTENSET_IN2_Msk   (0x1UL << GPIOTE_INTENSET_IN2_Pos)

Bit mask of IN2 field.

◆ GPIOTE_INTENSET_IN2_Pos

#define GPIOTE_INTENSET_IN2_Pos   (2UL)

Position of IN2 field.

◆ GPIOTE_INTENSET_IN2_Set

#define GPIOTE_INTENSET_IN2_Set   (1UL)

Enable

◆ GPIOTE_INTENSET_IN3_Disabled

#define GPIOTE_INTENSET_IN3_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_IN3_Enabled

#define GPIOTE_INTENSET_IN3_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_IN3_Msk

#define GPIOTE_INTENSET_IN3_Msk   (0x1UL << GPIOTE_INTENSET_IN3_Pos)

Bit mask of IN3 field.

◆ GPIOTE_INTENSET_IN3_Pos

#define GPIOTE_INTENSET_IN3_Pos   (3UL)

Position of IN3 field.

◆ GPIOTE_INTENSET_IN3_Set

#define GPIOTE_INTENSET_IN3_Set   (1UL)

Enable

◆ GPIOTE_INTENSET_IN4_Disabled

#define GPIOTE_INTENSET_IN4_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_IN4_Enabled

#define GPIOTE_INTENSET_IN4_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_IN4_Msk

#define GPIOTE_INTENSET_IN4_Msk   (0x1UL << GPIOTE_INTENSET_IN4_Pos)

Bit mask of IN4 field.

◆ GPIOTE_INTENSET_IN4_Pos

#define GPIOTE_INTENSET_IN4_Pos   (4UL)

Position of IN4 field.

◆ GPIOTE_INTENSET_IN4_Set

#define GPIOTE_INTENSET_IN4_Set   (1UL)

Enable

◆ GPIOTE_INTENSET_IN5_Disabled

#define GPIOTE_INTENSET_IN5_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_IN5_Enabled

#define GPIOTE_INTENSET_IN5_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_IN5_Msk

#define GPIOTE_INTENSET_IN5_Msk   (0x1UL << GPIOTE_INTENSET_IN5_Pos)

Bit mask of IN5 field.

◆ GPIOTE_INTENSET_IN5_Pos

#define GPIOTE_INTENSET_IN5_Pos   (5UL)

Position of IN5 field.

◆ GPIOTE_INTENSET_IN5_Set

#define GPIOTE_INTENSET_IN5_Set   (1UL)

Enable

◆ GPIOTE_INTENSET_IN6_Disabled

#define GPIOTE_INTENSET_IN6_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_IN6_Enabled

#define GPIOTE_INTENSET_IN6_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_IN6_Msk

#define GPIOTE_INTENSET_IN6_Msk   (0x1UL << GPIOTE_INTENSET_IN6_Pos)

Bit mask of IN6 field.

◆ GPIOTE_INTENSET_IN6_Pos

#define GPIOTE_INTENSET_IN6_Pos   (6UL)

Position of IN6 field.

◆ GPIOTE_INTENSET_IN6_Set

#define GPIOTE_INTENSET_IN6_Set   (1UL)

Enable

◆ GPIOTE_INTENSET_IN7_Disabled

#define GPIOTE_INTENSET_IN7_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_IN7_Enabled

#define GPIOTE_INTENSET_IN7_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_IN7_Msk

#define GPIOTE_INTENSET_IN7_Msk   (0x1UL << GPIOTE_INTENSET_IN7_Pos)

Bit mask of IN7 field.

◆ GPIOTE_INTENSET_IN7_Pos

#define GPIOTE_INTENSET_IN7_Pos   (7UL)

Position of IN7 field.

◆ GPIOTE_INTENSET_IN7_Set

#define GPIOTE_INTENSET_IN7_Set   (1UL)

Enable

◆ GPIOTE_INTENSET_PORT_Disabled

#define GPIOTE_INTENSET_PORT_Disabled   (0UL)

Read: Disabled

◆ GPIOTE_INTENSET_PORT_Enabled

#define GPIOTE_INTENSET_PORT_Enabled   (1UL)

Read: Enabled

◆ GPIOTE_INTENSET_PORT_Msk

#define GPIOTE_INTENSET_PORT_Msk   (0x1UL << GPIOTE_INTENSET_PORT_Pos)

Bit mask of PORT field.

◆ GPIOTE_INTENSET_PORT_Pos

#define GPIOTE_INTENSET_PORT_Pos   (31UL)

Position of PORT field.

◆ GPIOTE_INTENSET_PORT_Set

#define GPIOTE_INTENSET_PORT_Set   (1UL)

Enable

◆ I2S_CONFIG_ALIGN_ALIGN_Left

#define I2S_CONFIG_ALIGN_ALIGN_Left   (0UL)

Left-aligned.

◆ I2S_CONFIG_ALIGN_ALIGN_Msk

#define I2S_CONFIG_ALIGN_ALIGN_Msk   (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos)

Bit mask of ALIGN field.

◆ I2S_CONFIG_ALIGN_ALIGN_Pos

#define I2S_CONFIG_ALIGN_ALIGN_Pos   (0UL)

Position of ALIGN field.

◆ I2S_CONFIG_ALIGN_ALIGN_Right

#define I2S_CONFIG_ALIGN_ALIGN_Right   (1UL)

Right-aligned.

◆ I2S_CONFIG_CHANNELS_CHANNELS_Left

#define I2S_CONFIG_CHANNELS_CHANNELS_Left   (1UL)

Left only.

◆ I2S_CONFIG_CHANNELS_CHANNELS_Msk

#define I2S_CONFIG_CHANNELS_CHANNELS_Msk   (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos)

Bit mask of CHANNELS field.

◆ I2S_CONFIG_CHANNELS_CHANNELS_Pos

#define I2S_CONFIG_CHANNELS_CHANNELS_Pos   (0UL)

Position of CHANNELS field.

◆ I2S_CONFIG_CHANNELS_CHANNELS_Right

#define I2S_CONFIG_CHANNELS_CHANNELS_Right   (2UL)

Right only.

◆ I2S_CONFIG_CHANNELS_CHANNELS_Stereo

#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo   (0UL)

Stereo.

◆ I2S_CONFIG_FORMAT_FORMAT_Aligned

#define I2S_CONFIG_FORMAT_FORMAT_Aligned   (1UL)

Alternate (left- or right-aligned) format.

◆ I2S_CONFIG_FORMAT_FORMAT_I2S

#define I2S_CONFIG_FORMAT_FORMAT_I2S   (0UL)

Original I2S format.

◆ I2S_CONFIG_FORMAT_FORMAT_Msk

#define I2S_CONFIG_FORMAT_FORMAT_Msk   (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos)

Bit mask of FORMAT field.

◆ I2S_CONFIG_FORMAT_FORMAT_Pos

#define I2S_CONFIG_FORMAT_FORMAT_Pos   (0UL)

Position of FORMAT field.

◆ I2S_CONFIG_MCKEN_MCKEN_Disabled

#define I2S_CONFIG_MCKEN_MCKEN_Disabled   (0UL)

Master clock generator disabled and PSEL.MCK not connected(available as GPIO).

◆ I2S_CONFIG_MCKEN_MCKEN_Enabled

#define I2S_CONFIG_MCKEN_MCKEN_Enabled   (1UL)

Master clock generator running and MCK output on PSEL.MCK.

◆ I2S_CONFIG_MCKEN_MCKEN_Msk

#define I2S_CONFIG_MCKEN_MCKEN_Msk   (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos)

Bit mask of MCKEN field.

◆ I2S_CONFIG_MCKEN_MCKEN_Pos

#define I2S_CONFIG_MCKEN_MCKEN_Pos   (0UL)

Position of MCKEN field.

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10   (0x18000000UL)

32 MHz / 10 = 3.2 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11   (0x16000000UL)

32 MHz / 11 = 2.9090909 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125   (0x020C0000UL)

32 MHz / 125 = 0.256 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15   (0x11000000UL)

32 MHz / 15 = 2.1333333 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16   (0x10000000UL)

32 MHz / 16 = 2.0 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2   (0x80000000UL)

32 MHz / 2 = 16.0 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21   (0x0C000000UL)

32 MHz / 21 = 1.5238095

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23   (0x0B000000UL)

32 MHz / 23 = 1.3913043 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3   (0x50000000UL)

32 MHz / 3 = 10.6666667 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30   (0x08800000UL)

32 MHz / 30 = 1.0666667 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31   (0x08400000UL)

32 MHz / 31 = 1.0322581 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32   (0x08000000UL)

32 MHz / 32 = 1.0 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4   (0x40000000UL)

32 MHz / 4 = 8.0 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42   (0x06000000UL)

32 MHz / 42 = 0.7619048 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5   (0x30000000UL)

32 MHz / 5 = 6.4 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6   (0x28000000UL)

32 MHz / 6 = 5.3333333 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63   (0x04100000UL)

32 MHz / 63 = 0.5079365 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8

#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8   (0x20000000UL)

32 MHz / 8 = 4.0 MHz

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_Msk

#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk   (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos)

Bit mask of MCKFREQ field.

◆ I2S_CONFIG_MCKFREQ_MCKFREQ_Pos

#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos   (0UL)

Position of MCKFREQ field.

◆ I2S_CONFIG_MODE_MODE_Master

#define I2S_CONFIG_MODE_MODE_Master   (0UL)

Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx.

◆ I2S_CONFIG_MODE_MODE_Msk

#define I2S_CONFIG_MODE_MODE_Msk   (0x1UL << I2S_CONFIG_MODE_MODE_Pos)

Bit mask of MODE field.

◆ I2S_CONFIG_MODE_MODE_Pos

#define I2S_CONFIG_MODE_MODE_Pos   (0UL)

Position of MODE field.

◆ I2S_CONFIG_MODE_MODE_Slave

#define I2S_CONFIG_MODE_MODE_Slave   (1UL)

Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx

◆ I2S_CONFIG_RATIO_RATIO_128X

#define I2S_CONFIG_RATIO_RATIO_128X   (4UL)

LRCK = MCK / 128

◆ I2S_CONFIG_RATIO_RATIO_192X

#define I2S_CONFIG_RATIO_RATIO_192X   (5UL)

LRCK = MCK / 192

◆ I2S_CONFIG_RATIO_RATIO_256X

#define I2S_CONFIG_RATIO_RATIO_256X   (6UL)

LRCK = MCK / 256

◆ I2S_CONFIG_RATIO_RATIO_32X

#define I2S_CONFIG_RATIO_RATIO_32X   (0UL)

LRCK = MCK / 32

◆ I2S_CONFIG_RATIO_RATIO_384X

#define I2S_CONFIG_RATIO_RATIO_384X   (7UL)

LRCK = MCK / 384

◆ I2S_CONFIG_RATIO_RATIO_48X

#define I2S_CONFIG_RATIO_RATIO_48X   (1UL)

LRCK = MCK / 48

◆ I2S_CONFIG_RATIO_RATIO_512X

#define I2S_CONFIG_RATIO_RATIO_512X   (8UL)

LRCK = MCK / 512

◆ I2S_CONFIG_RATIO_RATIO_64X

#define I2S_CONFIG_RATIO_RATIO_64X   (2UL)

LRCK = MCK / 64

◆ I2S_CONFIG_RATIO_RATIO_96X

#define I2S_CONFIG_RATIO_RATIO_96X   (3UL)

LRCK = MCK / 96

◆ I2S_CONFIG_RATIO_RATIO_Msk

#define I2S_CONFIG_RATIO_RATIO_Msk   (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos)

Bit mask of RATIO field.

◆ I2S_CONFIG_RATIO_RATIO_Pos

#define I2S_CONFIG_RATIO_RATIO_Pos   (0UL)

Position of RATIO field.

◆ I2S_CONFIG_RXEN_RXEN_Disabled

#define I2S_CONFIG_RXEN_RXEN_Disabled   (0UL)

Reception disabled and now data will be written to the RXD.PTR address.

◆ I2S_CONFIG_RXEN_RXEN_Enabled

#define I2S_CONFIG_RXEN_RXEN_Enabled   (1UL)

Reception enabled.

◆ I2S_CONFIG_RXEN_RXEN_Msk

#define I2S_CONFIG_RXEN_RXEN_Msk   (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos)

Bit mask of RXEN field.

◆ I2S_CONFIG_RXEN_RXEN_Pos

#define I2S_CONFIG_RXEN_RXEN_Pos   (0UL)

Position of RXEN field.

◆ I2S_CONFIG_SWIDTH_SWIDTH_16Bit

#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit   (1UL)

16 bit.

◆ I2S_CONFIG_SWIDTH_SWIDTH_24Bit

#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit   (2UL)

24 bit.

◆ I2S_CONFIG_SWIDTH_SWIDTH_8Bit

#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit   (0UL)

8 bit.

◆ I2S_CONFIG_SWIDTH_SWIDTH_Msk

#define I2S_CONFIG_SWIDTH_SWIDTH_Msk   (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos)

Bit mask of SWIDTH field.

◆ I2S_CONFIG_SWIDTH_SWIDTH_Pos

#define I2S_CONFIG_SWIDTH_SWIDTH_Pos   (0UL)

Position of SWIDTH field.

◆ I2S_CONFIG_TXEN_TXEN_Disabled

#define I2S_CONFIG_TXEN_TXEN_Disabled   (0UL)

Transmission disabled and now data will be read from the RXD.TXD address.

◆ I2S_CONFIG_TXEN_TXEN_Enabled

#define I2S_CONFIG_TXEN_TXEN_Enabled   (1UL)

Transmission enabled.

◆ I2S_CONFIG_TXEN_TXEN_Msk

#define I2S_CONFIG_TXEN_TXEN_Msk   (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos)

Bit mask of TXEN field.

◆ I2S_CONFIG_TXEN_TXEN_Pos

#define I2S_CONFIG_TXEN_TXEN_Pos   (0UL)

Position of TXEN field.

◆ I2S_ENABLE_ENABLE_Disabled

#define I2S_ENABLE_ENABLE_Disabled   (0UL)

Disable

◆ I2S_ENABLE_ENABLE_Enabled

#define I2S_ENABLE_ENABLE_Enabled   (1UL)

Enable

◆ I2S_ENABLE_ENABLE_Msk

#define I2S_ENABLE_ENABLE_Msk   (0x1UL << I2S_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ I2S_ENABLE_ENABLE_Pos

#define I2S_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ I2S_INTEN_RXPTRUPD_Disabled

#define I2S_INTEN_RXPTRUPD_Disabled   (0UL)

Disable

◆ I2S_INTEN_RXPTRUPD_Enabled

#define I2S_INTEN_RXPTRUPD_Enabled   (1UL)

Enable

◆ I2S_INTEN_RXPTRUPD_Msk

#define I2S_INTEN_RXPTRUPD_Msk   (0x1UL << I2S_INTEN_RXPTRUPD_Pos)

Bit mask of RXPTRUPD field.

◆ I2S_INTEN_RXPTRUPD_Pos

#define I2S_INTEN_RXPTRUPD_Pos   (1UL)

Position of RXPTRUPD field.

◆ I2S_INTEN_STOPPED_Disabled

#define I2S_INTEN_STOPPED_Disabled   (0UL)

Disable

◆ I2S_INTEN_STOPPED_Enabled

#define I2S_INTEN_STOPPED_Enabled   (1UL)

Enable

◆ I2S_INTEN_STOPPED_Msk

#define I2S_INTEN_STOPPED_Msk   (0x1UL << I2S_INTEN_STOPPED_Pos)

Bit mask of STOPPED field.

◆ I2S_INTEN_STOPPED_Pos

#define I2S_INTEN_STOPPED_Pos   (2UL)

Position of STOPPED field.

◆ I2S_INTEN_TXPTRUPD_Disabled

#define I2S_INTEN_TXPTRUPD_Disabled   (0UL)

Disable

◆ I2S_INTEN_TXPTRUPD_Enabled

#define I2S_INTEN_TXPTRUPD_Enabled   (1UL)

Enable

◆ I2S_INTEN_TXPTRUPD_Msk

#define I2S_INTEN_TXPTRUPD_Msk   (0x1UL << I2S_INTEN_TXPTRUPD_Pos)

Bit mask of TXPTRUPD field.

◆ I2S_INTEN_TXPTRUPD_Pos

#define I2S_INTEN_TXPTRUPD_Pos   (5UL)

Position of TXPTRUPD field.

◆ I2S_INTENCLR_RXPTRUPD_Clear

#define I2S_INTENCLR_RXPTRUPD_Clear   (1UL)

Disable

◆ I2S_INTENCLR_RXPTRUPD_Disabled

#define I2S_INTENCLR_RXPTRUPD_Disabled   (0UL)

Read: Disabled

◆ I2S_INTENCLR_RXPTRUPD_Enabled

#define I2S_INTENCLR_RXPTRUPD_Enabled   (1UL)

Read: Enabled

◆ I2S_INTENCLR_RXPTRUPD_Msk

#define I2S_INTENCLR_RXPTRUPD_Msk   (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos)

Bit mask of RXPTRUPD field.

◆ I2S_INTENCLR_RXPTRUPD_Pos

#define I2S_INTENCLR_RXPTRUPD_Pos   (1UL)

Position of RXPTRUPD field.

◆ I2S_INTENCLR_STOPPED_Clear

#define I2S_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ I2S_INTENCLR_STOPPED_Disabled

#define I2S_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ I2S_INTENCLR_STOPPED_Enabled

#define I2S_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ I2S_INTENCLR_STOPPED_Msk

#define I2S_INTENCLR_STOPPED_Msk   (0x1UL << I2S_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ I2S_INTENCLR_STOPPED_Pos

#define I2S_INTENCLR_STOPPED_Pos   (2UL)

Position of STOPPED field.

◆ I2S_INTENCLR_TXPTRUPD_Clear

#define I2S_INTENCLR_TXPTRUPD_Clear   (1UL)

Disable

◆ I2S_INTENCLR_TXPTRUPD_Disabled

#define I2S_INTENCLR_TXPTRUPD_Disabled   (0UL)

Read: Disabled

◆ I2S_INTENCLR_TXPTRUPD_Enabled

#define I2S_INTENCLR_TXPTRUPD_Enabled   (1UL)

Read: Enabled

◆ I2S_INTENCLR_TXPTRUPD_Msk

#define I2S_INTENCLR_TXPTRUPD_Msk   (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos)

Bit mask of TXPTRUPD field.

◆ I2S_INTENCLR_TXPTRUPD_Pos

#define I2S_INTENCLR_TXPTRUPD_Pos   (5UL)

Position of TXPTRUPD field.

◆ I2S_INTENSET_RXPTRUPD_Disabled

#define I2S_INTENSET_RXPTRUPD_Disabled   (0UL)

Read: Disabled

◆ I2S_INTENSET_RXPTRUPD_Enabled

#define I2S_INTENSET_RXPTRUPD_Enabled   (1UL)

Read: Enabled

◆ I2S_INTENSET_RXPTRUPD_Msk

#define I2S_INTENSET_RXPTRUPD_Msk   (0x1UL << I2S_INTENSET_RXPTRUPD_Pos)

Bit mask of RXPTRUPD field.

◆ I2S_INTENSET_RXPTRUPD_Pos

#define I2S_INTENSET_RXPTRUPD_Pos   (1UL)

Position of RXPTRUPD field.

◆ I2S_INTENSET_RXPTRUPD_Set

#define I2S_INTENSET_RXPTRUPD_Set   (1UL)

Enable

◆ I2S_INTENSET_STOPPED_Disabled

#define I2S_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ I2S_INTENSET_STOPPED_Enabled

#define I2S_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ I2S_INTENSET_STOPPED_Msk

#define I2S_INTENSET_STOPPED_Msk   (0x1UL << I2S_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ I2S_INTENSET_STOPPED_Pos

#define I2S_INTENSET_STOPPED_Pos   (2UL)

Position of STOPPED field.

◆ I2S_INTENSET_STOPPED_Set

#define I2S_INTENSET_STOPPED_Set   (1UL)

Enable

◆ I2S_INTENSET_TXPTRUPD_Disabled

#define I2S_INTENSET_TXPTRUPD_Disabled   (0UL)

Read: Disabled

◆ I2S_INTENSET_TXPTRUPD_Enabled

#define I2S_INTENSET_TXPTRUPD_Enabled   (1UL)

Read: Enabled

◆ I2S_INTENSET_TXPTRUPD_Msk

#define I2S_INTENSET_TXPTRUPD_Msk   (0x1UL << I2S_INTENSET_TXPTRUPD_Pos)

Bit mask of TXPTRUPD field.

◆ I2S_INTENSET_TXPTRUPD_Pos

#define I2S_INTENSET_TXPTRUPD_Pos   (5UL)

Position of TXPTRUPD field.

◆ I2S_INTENSET_TXPTRUPD_Set

#define I2S_INTENSET_TXPTRUPD_Set   (1UL)

Enable

◆ I2S_PSEL_LRCK_CONNECT_Connected

#define I2S_PSEL_LRCK_CONNECT_Connected   (0UL)

Connect

◆ I2S_PSEL_LRCK_CONNECT_Disconnected

#define I2S_PSEL_LRCK_CONNECT_Disconnected   (1UL)

Disconnect

◆ I2S_PSEL_LRCK_CONNECT_Msk

#define I2S_PSEL_LRCK_CONNECT_Msk   (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos)

Bit mask of CONNECT field.

◆ I2S_PSEL_LRCK_CONNECT_Pos

#define I2S_PSEL_LRCK_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ I2S_PSEL_LRCK_PIN_Msk

#define I2S_PSEL_LRCK_PIN_Msk   (0x1FUL << I2S_PSEL_LRCK_PIN_Pos)

Bit mask of PIN field.

◆ I2S_PSEL_LRCK_PIN_Pos

#define I2S_PSEL_LRCK_PIN_Pos   (0UL)

Position of PIN field.

◆ I2S_PSEL_MCK_CONNECT_Connected

#define I2S_PSEL_MCK_CONNECT_Connected   (0UL)

Connect

◆ I2S_PSEL_MCK_CONNECT_Disconnected

#define I2S_PSEL_MCK_CONNECT_Disconnected   (1UL)

Disconnect

◆ I2S_PSEL_MCK_CONNECT_Msk

#define I2S_PSEL_MCK_CONNECT_Msk   (0x1UL << I2S_PSEL_MCK_CONNECT_Pos)

Bit mask of CONNECT field.

◆ I2S_PSEL_MCK_CONNECT_Pos

#define I2S_PSEL_MCK_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ I2S_PSEL_MCK_PIN_Msk

#define I2S_PSEL_MCK_PIN_Msk   (0x1FUL << I2S_PSEL_MCK_PIN_Pos)

Bit mask of PIN field.

◆ I2S_PSEL_MCK_PIN_Pos

#define I2S_PSEL_MCK_PIN_Pos   (0UL)

Position of PIN field.

◆ I2S_PSEL_SCK_CONNECT_Connected

#define I2S_PSEL_SCK_CONNECT_Connected   (0UL)

Connect

◆ I2S_PSEL_SCK_CONNECT_Disconnected

#define I2S_PSEL_SCK_CONNECT_Disconnected   (1UL)

Disconnect

◆ I2S_PSEL_SCK_CONNECT_Msk

#define I2S_PSEL_SCK_CONNECT_Msk   (0x1UL << I2S_PSEL_SCK_CONNECT_Pos)

Bit mask of CONNECT field.

◆ I2S_PSEL_SCK_CONNECT_Pos

#define I2S_PSEL_SCK_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ I2S_PSEL_SCK_PIN_Msk

#define I2S_PSEL_SCK_PIN_Msk   (0x1FUL << I2S_PSEL_SCK_PIN_Pos)

Bit mask of PIN field.

◆ I2S_PSEL_SCK_PIN_Pos

#define I2S_PSEL_SCK_PIN_Pos   (0UL)

Position of PIN field.

◆ I2S_PSEL_SDIN_CONNECT_Connected

#define I2S_PSEL_SDIN_CONNECT_Connected   (0UL)

Connect

◆ I2S_PSEL_SDIN_CONNECT_Disconnected

#define I2S_PSEL_SDIN_CONNECT_Disconnected   (1UL)

Disconnect

◆ I2S_PSEL_SDIN_CONNECT_Msk

#define I2S_PSEL_SDIN_CONNECT_Msk   (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos)

Bit mask of CONNECT field.

◆ I2S_PSEL_SDIN_CONNECT_Pos

#define I2S_PSEL_SDIN_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ I2S_PSEL_SDIN_PIN_Msk

#define I2S_PSEL_SDIN_PIN_Msk   (0x1FUL << I2S_PSEL_SDIN_PIN_Pos)

Bit mask of PIN field.

◆ I2S_PSEL_SDIN_PIN_Pos

#define I2S_PSEL_SDIN_PIN_Pos   (0UL)

Position of PIN field.

◆ I2S_PSEL_SDOUT_CONNECT_Connected

#define I2S_PSEL_SDOUT_CONNECT_Connected   (0UL)

Connect

◆ I2S_PSEL_SDOUT_CONNECT_Disconnected

#define I2S_PSEL_SDOUT_CONNECT_Disconnected   (1UL)

Disconnect

◆ I2S_PSEL_SDOUT_CONNECT_Msk

#define I2S_PSEL_SDOUT_CONNECT_Msk   (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos)

Bit mask of CONNECT field.

◆ I2S_PSEL_SDOUT_CONNECT_Pos

#define I2S_PSEL_SDOUT_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ I2S_PSEL_SDOUT_PIN_Msk

#define I2S_PSEL_SDOUT_PIN_Msk   (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos)

Bit mask of PIN field.

◆ I2S_PSEL_SDOUT_PIN_Pos

#define I2S_PSEL_SDOUT_PIN_Pos   (0UL)

Position of PIN field.

◆ I2S_RXD_PTR_PTR_Msk

#define I2S_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ I2S_RXD_PTR_PTR_Pos

#define I2S_RXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ I2S_RXTXD_MAXCNT_MAXCNT_Msk

#define I2S_RXTXD_MAXCNT_MAXCNT_Msk   (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ I2S_RXTXD_MAXCNT_MAXCNT_Pos

#define I2S_RXTXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ I2S_TXD_PTR_PTR_Msk

#define I2S_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ I2S_TXD_PTR_PTR_Pos

#define I2S_TXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ LPCOMP_ANADETECT_ANADETECT_Cross

#define LPCOMP_ANADETECT_ANADETECT_Cross   (0UL)

Generate ANADETECT on crossing, both upward crossing and downward crossing

◆ LPCOMP_ANADETECT_ANADETECT_Down

#define LPCOMP_ANADETECT_ANADETECT_Down   (2UL)

Generate ANADETECT on downward crossing only

◆ LPCOMP_ANADETECT_ANADETECT_Msk

#define LPCOMP_ANADETECT_ANADETECT_Msk   (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos)

Bit mask of ANADETECT field.

◆ LPCOMP_ANADETECT_ANADETECT_Pos

#define LPCOMP_ANADETECT_ANADETECT_Pos   (0UL)

Position of ANADETECT field.

◆ LPCOMP_ANADETECT_ANADETECT_Up

#define LPCOMP_ANADETECT_ANADETECT_Up   (1UL)

Generate ANADETECT on upward crossing only

◆ LPCOMP_ENABLE_ENABLE_Disabled

#define LPCOMP_ENABLE_ENABLE_Disabled   (0UL)

Disable

◆ LPCOMP_ENABLE_ENABLE_Enabled

#define LPCOMP_ENABLE_ENABLE_Enabled   (1UL)

Enable

◆ LPCOMP_ENABLE_ENABLE_Msk

#define LPCOMP_ENABLE_ENABLE_Msk   (0x3UL << LPCOMP_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ LPCOMP_ENABLE_ENABLE_Pos

#define LPCOMP_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0

#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0   (0UL)

Use AIN0 as external analog reference

◆ LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1

#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1   (1UL)

Use AIN1 as external analog reference

◆ LPCOMP_EXTREFSEL_EXTREFSEL_Msk

#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk   (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos)

Bit mask of EXTREFSEL field.

◆ LPCOMP_EXTREFSEL_EXTREFSEL_Pos

#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos   (0UL)

Position of EXTREFSEL field.

◆ LPCOMP_HYST_HYST_Hyst50mV

#define LPCOMP_HYST_HYST_Hyst50mV   (1UL)

Comparator hysteresis disabled (typ. 50 mV)

◆ LPCOMP_HYST_HYST_Msk

#define LPCOMP_HYST_HYST_Msk   (0x1UL << LPCOMP_HYST_HYST_Pos)

Bit mask of HYST field.

◆ LPCOMP_HYST_HYST_NoHyst

#define LPCOMP_HYST_HYST_NoHyst   (0UL)

Comparator hysteresis disabled

◆ LPCOMP_HYST_HYST_Pos

#define LPCOMP_HYST_HYST_Pos   (0UL)

Position of HYST field.

◆ LPCOMP_INTENCLR_CROSS_Clear

#define LPCOMP_INTENCLR_CROSS_Clear   (1UL)

Disable

◆ LPCOMP_INTENCLR_CROSS_Disabled

#define LPCOMP_INTENCLR_CROSS_Disabled   (0UL)

Read: Disabled

◆ LPCOMP_INTENCLR_CROSS_Enabled

#define LPCOMP_INTENCLR_CROSS_Enabled   (1UL)

Read: Enabled

◆ LPCOMP_INTENCLR_CROSS_Msk

#define LPCOMP_INTENCLR_CROSS_Msk   (0x1UL << LPCOMP_INTENCLR_CROSS_Pos)

Bit mask of CROSS field.

◆ LPCOMP_INTENCLR_CROSS_Pos

#define LPCOMP_INTENCLR_CROSS_Pos   (3UL)

Position of CROSS field.

◆ LPCOMP_INTENCLR_DOWN_Clear

#define LPCOMP_INTENCLR_DOWN_Clear   (1UL)

Disable

◆ LPCOMP_INTENCLR_DOWN_Disabled

#define LPCOMP_INTENCLR_DOWN_Disabled   (0UL)

Read: Disabled

◆ LPCOMP_INTENCLR_DOWN_Enabled

#define LPCOMP_INTENCLR_DOWN_Enabled   (1UL)

Read: Enabled

◆ LPCOMP_INTENCLR_DOWN_Msk

#define LPCOMP_INTENCLR_DOWN_Msk   (0x1UL << LPCOMP_INTENCLR_DOWN_Pos)

Bit mask of DOWN field.

◆ LPCOMP_INTENCLR_DOWN_Pos

#define LPCOMP_INTENCLR_DOWN_Pos   (1UL)

Position of DOWN field.

◆ LPCOMP_INTENCLR_READY_Clear

#define LPCOMP_INTENCLR_READY_Clear   (1UL)

Disable

◆ LPCOMP_INTENCLR_READY_Disabled

#define LPCOMP_INTENCLR_READY_Disabled   (0UL)

Read: Disabled

◆ LPCOMP_INTENCLR_READY_Enabled

#define LPCOMP_INTENCLR_READY_Enabled   (1UL)

Read: Enabled

◆ LPCOMP_INTENCLR_READY_Msk

#define LPCOMP_INTENCLR_READY_Msk   (0x1UL << LPCOMP_INTENCLR_READY_Pos)

Bit mask of READY field.

◆ LPCOMP_INTENCLR_READY_Pos

#define LPCOMP_INTENCLR_READY_Pos   (0UL)

Position of READY field.

◆ LPCOMP_INTENCLR_UP_Clear

#define LPCOMP_INTENCLR_UP_Clear   (1UL)

Disable

◆ LPCOMP_INTENCLR_UP_Disabled

#define LPCOMP_INTENCLR_UP_Disabled   (0UL)

Read: Disabled

◆ LPCOMP_INTENCLR_UP_Enabled

#define LPCOMP_INTENCLR_UP_Enabled   (1UL)

Read: Enabled

◆ LPCOMP_INTENCLR_UP_Msk

#define LPCOMP_INTENCLR_UP_Msk   (0x1UL << LPCOMP_INTENCLR_UP_Pos)

Bit mask of UP field.

◆ LPCOMP_INTENCLR_UP_Pos

#define LPCOMP_INTENCLR_UP_Pos   (2UL)

Position of UP field.

◆ LPCOMP_INTENSET_CROSS_Disabled

#define LPCOMP_INTENSET_CROSS_Disabled   (0UL)

Read: Disabled

◆ LPCOMP_INTENSET_CROSS_Enabled

#define LPCOMP_INTENSET_CROSS_Enabled   (1UL)

Read: Enabled

◆ LPCOMP_INTENSET_CROSS_Msk

#define LPCOMP_INTENSET_CROSS_Msk   (0x1UL << LPCOMP_INTENSET_CROSS_Pos)

Bit mask of CROSS field.

◆ LPCOMP_INTENSET_CROSS_Pos

#define LPCOMP_INTENSET_CROSS_Pos   (3UL)

Position of CROSS field.

◆ LPCOMP_INTENSET_CROSS_Set

#define LPCOMP_INTENSET_CROSS_Set   (1UL)

Enable

◆ LPCOMP_INTENSET_DOWN_Disabled

#define LPCOMP_INTENSET_DOWN_Disabled   (0UL)

Read: Disabled

◆ LPCOMP_INTENSET_DOWN_Enabled

#define LPCOMP_INTENSET_DOWN_Enabled   (1UL)

Read: Enabled

◆ LPCOMP_INTENSET_DOWN_Msk

#define LPCOMP_INTENSET_DOWN_Msk   (0x1UL << LPCOMP_INTENSET_DOWN_Pos)

Bit mask of DOWN field.

◆ LPCOMP_INTENSET_DOWN_Pos

#define LPCOMP_INTENSET_DOWN_Pos   (1UL)

Position of DOWN field.

◆ LPCOMP_INTENSET_DOWN_Set

#define LPCOMP_INTENSET_DOWN_Set   (1UL)

Enable

◆ LPCOMP_INTENSET_READY_Disabled

#define LPCOMP_INTENSET_READY_Disabled   (0UL)

Read: Disabled

◆ LPCOMP_INTENSET_READY_Enabled

#define LPCOMP_INTENSET_READY_Enabled   (1UL)

Read: Enabled

◆ LPCOMP_INTENSET_READY_Msk

#define LPCOMP_INTENSET_READY_Msk   (0x1UL << LPCOMP_INTENSET_READY_Pos)

Bit mask of READY field.

◆ LPCOMP_INTENSET_READY_Pos

#define LPCOMP_INTENSET_READY_Pos   (0UL)

Position of READY field.

◆ LPCOMP_INTENSET_READY_Set

#define LPCOMP_INTENSET_READY_Set   (1UL)

Enable

◆ LPCOMP_INTENSET_UP_Disabled

#define LPCOMP_INTENSET_UP_Disabled   (0UL)

Read: Disabled

◆ LPCOMP_INTENSET_UP_Enabled

#define LPCOMP_INTENSET_UP_Enabled   (1UL)

Read: Enabled

◆ LPCOMP_INTENSET_UP_Msk

#define LPCOMP_INTENSET_UP_Msk   (0x1UL << LPCOMP_INTENSET_UP_Pos)

Bit mask of UP field.

◆ LPCOMP_INTENSET_UP_Pos

#define LPCOMP_INTENSET_UP_Pos   (2UL)

Position of UP field.

◆ LPCOMP_INTENSET_UP_Set

#define LPCOMP_INTENSET_UP_Set   (1UL)

Enable

◆ LPCOMP_PSEL_PSEL_AnalogInput0

#define LPCOMP_PSEL_PSEL_AnalogInput0   (0UL)

AIN0 selected as analog input

◆ LPCOMP_PSEL_PSEL_AnalogInput1

#define LPCOMP_PSEL_PSEL_AnalogInput1   (1UL)

AIN1 selected as analog input

◆ LPCOMP_PSEL_PSEL_AnalogInput2

#define LPCOMP_PSEL_PSEL_AnalogInput2   (2UL)

AIN2 selected as analog input

◆ LPCOMP_PSEL_PSEL_AnalogInput3

#define LPCOMP_PSEL_PSEL_AnalogInput3   (3UL)

AIN3 selected as analog input

◆ LPCOMP_PSEL_PSEL_AnalogInput4

#define LPCOMP_PSEL_PSEL_AnalogInput4   (4UL)

AIN4 selected as analog input

◆ LPCOMP_PSEL_PSEL_AnalogInput5

#define LPCOMP_PSEL_PSEL_AnalogInput5   (5UL)

AIN5 selected as analog input

◆ LPCOMP_PSEL_PSEL_AnalogInput6

#define LPCOMP_PSEL_PSEL_AnalogInput6   (6UL)

AIN6 selected as analog input

◆ LPCOMP_PSEL_PSEL_AnalogInput7

#define LPCOMP_PSEL_PSEL_AnalogInput7   (7UL)

AIN7 selected as analog input

◆ LPCOMP_PSEL_PSEL_Msk

#define LPCOMP_PSEL_PSEL_Msk   (0x7UL << LPCOMP_PSEL_PSEL_Pos)

Bit mask of PSEL field.

◆ LPCOMP_PSEL_PSEL_Pos

#define LPCOMP_PSEL_PSEL_Pos   (0UL)

Position of PSEL field.

◆ LPCOMP_REFSEL_REFSEL_ARef

#define LPCOMP_REFSEL_REFSEL_ARef   (7UL)

External analog reference selected

◆ LPCOMP_REFSEL_REFSEL_Msk

#define LPCOMP_REFSEL_REFSEL_Msk   (0xFUL << LPCOMP_REFSEL_REFSEL_Pos)

Bit mask of REFSEL field.

◆ LPCOMP_REFSEL_REFSEL_Pos

#define LPCOMP_REFSEL_REFSEL_Pos   (0UL)

Position of REFSEL field.

◆ LPCOMP_REFSEL_REFSEL_Ref11_16Vdd

#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd   (13UL)

VDD * 11/16 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref13_16Vdd

#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd   (14UL)

VDD * 13/16 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref15_16Vdd

#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd   (15UL)

VDD * 15/16 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref1_16Vdd

#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd   (8UL)

VDD * 1/16 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref1_8Vdd

#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd   (0UL)

VDD * 1/8 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref2_8Vdd

#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd   (1UL)

VDD * 2/8 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref3_16Vdd

#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd   (9UL)

VDD * 3/16 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref3_8Vdd

#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd   (2UL)

VDD * 3/8 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref4_8Vdd

#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd   (3UL)

VDD * 4/8 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref5_16Vdd

#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd   (10UL)

VDD * 5/16 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref5_8Vdd

#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd   (4UL)

VDD * 5/8 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref6_8Vdd

#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd   (5UL)

VDD * 6/8 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref7_16Vdd

#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd   (11UL)

VDD * 7/16 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref7_8Vdd

#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd   (6UL)

VDD * 7/8 selected as reference

◆ LPCOMP_REFSEL_REFSEL_Ref9_16Vdd

#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd   (12UL)

VDD * 9/16 selected as reference

◆ LPCOMP_RESULT_RESULT_Above

#define LPCOMP_RESULT_RESULT_Above   (1UL)

Input voltage is above the reference threshold (VIN+ > VIN-).

◆ LPCOMP_RESULT_RESULT_Below

#define LPCOMP_RESULT_RESULT_Below   (0UL)

Input voltage is below the reference threshold (VIN+ < VIN-).

◆ LPCOMP_RESULT_RESULT_Msk

#define LPCOMP_RESULT_RESULT_Msk   (0x1UL << LPCOMP_RESULT_RESULT_Pos)

Bit mask of RESULT field.

◆ LPCOMP_RESULT_RESULT_Pos

#define LPCOMP_RESULT_RESULT_Pos   (0UL)

Position of RESULT field.

◆ LPCOMP_SHORTS_CROSS_STOP_Disabled

#define LPCOMP_SHORTS_CROSS_STOP_Disabled   (0UL)

Disable shortcut

◆ LPCOMP_SHORTS_CROSS_STOP_Enabled

#define LPCOMP_SHORTS_CROSS_STOP_Enabled   (1UL)

Enable shortcut

◆ LPCOMP_SHORTS_CROSS_STOP_Msk

#define LPCOMP_SHORTS_CROSS_STOP_Msk   (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos)

Bit mask of CROSS_STOP field.

◆ LPCOMP_SHORTS_CROSS_STOP_Pos

#define LPCOMP_SHORTS_CROSS_STOP_Pos   (4UL)

Position of CROSS_STOP field.

◆ LPCOMP_SHORTS_DOWN_STOP_Disabled

#define LPCOMP_SHORTS_DOWN_STOP_Disabled   (0UL)

Disable shortcut

◆ LPCOMP_SHORTS_DOWN_STOP_Enabled

#define LPCOMP_SHORTS_DOWN_STOP_Enabled   (1UL)

Enable shortcut

◆ LPCOMP_SHORTS_DOWN_STOP_Msk

#define LPCOMP_SHORTS_DOWN_STOP_Msk   (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos)

Bit mask of DOWN_STOP field.

◆ LPCOMP_SHORTS_DOWN_STOP_Pos

#define LPCOMP_SHORTS_DOWN_STOP_Pos   (2UL)

Position of DOWN_STOP field.

◆ LPCOMP_SHORTS_READY_SAMPLE_Disabled

#define LPCOMP_SHORTS_READY_SAMPLE_Disabled   (0UL)

Disable shortcut

◆ LPCOMP_SHORTS_READY_SAMPLE_Enabled

#define LPCOMP_SHORTS_READY_SAMPLE_Enabled   (1UL)

Enable shortcut

◆ LPCOMP_SHORTS_READY_SAMPLE_Msk

#define LPCOMP_SHORTS_READY_SAMPLE_Msk   (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos)

Bit mask of READY_SAMPLE field.

◆ LPCOMP_SHORTS_READY_SAMPLE_Pos

#define LPCOMP_SHORTS_READY_SAMPLE_Pos   (0UL)

Position of READY_SAMPLE field.

◆ LPCOMP_SHORTS_READY_STOP_Disabled

#define LPCOMP_SHORTS_READY_STOP_Disabled   (0UL)

Disable shortcut

◆ LPCOMP_SHORTS_READY_STOP_Enabled

#define LPCOMP_SHORTS_READY_STOP_Enabled   (1UL)

Enable shortcut

◆ LPCOMP_SHORTS_READY_STOP_Msk

#define LPCOMP_SHORTS_READY_STOP_Msk   (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos)

Bit mask of READY_STOP field.

◆ LPCOMP_SHORTS_READY_STOP_Pos

#define LPCOMP_SHORTS_READY_STOP_Pos   (1UL)

Position of READY_STOP field.

◆ LPCOMP_SHORTS_UP_STOP_Disabled

#define LPCOMP_SHORTS_UP_STOP_Disabled   (0UL)

Disable shortcut

◆ LPCOMP_SHORTS_UP_STOP_Enabled

#define LPCOMP_SHORTS_UP_STOP_Enabled   (1UL)

Enable shortcut

◆ LPCOMP_SHORTS_UP_STOP_Msk

#define LPCOMP_SHORTS_UP_STOP_Msk   (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos)

Bit mask of UP_STOP field.

◆ LPCOMP_SHORTS_UP_STOP_Pos

#define LPCOMP_SHORTS_UP_STOP_Pos   (3UL)

Position of UP_STOP field.

◆ MWU_INTEN_PREGION0RA_Disabled

#define MWU_INTEN_PREGION0RA_Disabled   (0UL)

Disable

◆ MWU_INTEN_PREGION0RA_Enabled

#define MWU_INTEN_PREGION0RA_Enabled   (1UL)

Enable

◆ MWU_INTEN_PREGION0RA_Msk

#define MWU_INTEN_PREGION0RA_Msk   (0x1UL << MWU_INTEN_PREGION0RA_Pos)

Bit mask of PREGION0RA field.

◆ MWU_INTEN_PREGION0RA_Pos

#define MWU_INTEN_PREGION0RA_Pos   (25UL)

Position of PREGION0RA field.

◆ MWU_INTEN_PREGION0WA_Disabled

#define MWU_INTEN_PREGION0WA_Disabled   (0UL)

Disable

◆ MWU_INTEN_PREGION0WA_Enabled

#define MWU_INTEN_PREGION0WA_Enabled   (1UL)

Enable

◆ MWU_INTEN_PREGION0WA_Msk

#define MWU_INTEN_PREGION0WA_Msk   (0x1UL << MWU_INTEN_PREGION0WA_Pos)

Bit mask of PREGION0WA field.

◆ MWU_INTEN_PREGION0WA_Pos

#define MWU_INTEN_PREGION0WA_Pos   (24UL)

Position of PREGION0WA field.

◆ MWU_INTEN_PREGION1RA_Disabled

#define MWU_INTEN_PREGION1RA_Disabled   (0UL)

Disable

◆ MWU_INTEN_PREGION1RA_Enabled

#define MWU_INTEN_PREGION1RA_Enabled   (1UL)

Enable

◆ MWU_INTEN_PREGION1RA_Msk

#define MWU_INTEN_PREGION1RA_Msk   (0x1UL << MWU_INTEN_PREGION1RA_Pos)

Bit mask of PREGION1RA field.

◆ MWU_INTEN_PREGION1RA_Pos

#define MWU_INTEN_PREGION1RA_Pos   (27UL)

Position of PREGION1RA field.

◆ MWU_INTEN_PREGION1WA_Disabled

#define MWU_INTEN_PREGION1WA_Disabled   (0UL)

Disable

◆ MWU_INTEN_PREGION1WA_Enabled

#define MWU_INTEN_PREGION1WA_Enabled   (1UL)

Enable

◆ MWU_INTEN_PREGION1WA_Msk

#define MWU_INTEN_PREGION1WA_Msk   (0x1UL << MWU_INTEN_PREGION1WA_Pos)

Bit mask of PREGION1WA field.

◆ MWU_INTEN_PREGION1WA_Pos

#define MWU_INTEN_PREGION1WA_Pos   (26UL)

Position of PREGION1WA field.

◆ MWU_INTEN_REGION0RA_Disabled

#define MWU_INTEN_REGION0RA_Disabled   (0UL)

Disable

◆ MWU_INTEN_REGION0RA_Enabled

#define MWU_INTEN_REGION0RA_Enabled   (1UL)

Enable

◆ MWU_INTEN_REGION0RA_Msk

#define MWU_INTEN_REGION0RA_Msk   (0x1UL << MWU_INTEN_REGION0RA_Pos)

Bit mask of REGION0RA field.

◆ MWU_INTEN_REGION0RA_Pos

#define MWU_INTEN_REGION0RA_Pos   (1UL)

Position of REGION0RA field.

◆ MWU_INTEN_REGION0WA_Disabled

#define MWU_INTEN_REGION0WA_Disabled   (0UL)

Disable

◆ MWU_INTEN_REGION0WA_Enabled

#define MWU_INTEN_REGION0WA_Enabled   (1UL)

Enable

◆ MWU_INTEN_REGION0WA_Msk

#define MWU_INTEN_REGION0WA_Msk   (0x1UL << MWU_INTEN_REGION0WA_Pos)

Bit mask of REGION0WA field.

◆ MWU_INTEN_REGION0WA_Pos

#define MWU_INTEN_REGION0WA_Pos   (0UL)

Position of REGION0WA field.

◆ MWU_INTEN_REGION1RA_Disabled

#define MWU_INTEN_REGION1RA_Disabled   (0UL)

Disable

◆ MWU_INTEN_REGION1RA_Enabled

#define MWU_INTEN_REGION1RA_Enabled   (1UL)

Enable

◆ MWU_INTEN_REGION1RA_Msk

#define MWU_INTEN_REGION1RA_Msk   (0x1UL << MWU_INTEN_REGION1RA_Pos)

Bit mask of REGION1RA field.

◆ MWU_INTEN_REGION1RA_Pos

#define MWU_INTEN_REGION1RA_Pos   (3UL)

Position of REGION1RA field.

◆ MWU_INTEN_REGION1WA_Disabled

#define MWU_INTEN_REGION1WA_Disabled   (0UL)

Disable

◆ MWU_INTEN_REGION1WA_Enabled

#define MWU_INTEN_REGION1WA_Enabled   (1UL)

Enable

◆ MWU_INTEN_REGION1WA_Msk

#define MWU_INTEN_REGION1WA_Msk   (0x1UL << MWU_INTEN_REGION1WA_Pos)

Bit mask of REGION1WA field.

◆ MWU_INTEN_REGION1WA_Pos

#define MWU_INTEN_REGION1WA_Pos   (2UL)

Position of REGION1WA field.

◆ MWU_INTEN_REGION2RA_Disabled

#define MWU_INTEN_REGION2RA_Disabled   (0UL)

Disable

◆ MWU_INTEN_REGION2RA_Enabled

#define MWU_INTEN_REGION2RA_Enabled   (1UL)

Enable

◆ MWU_INTEN_REGION2RA_Msk

#define MWU_INTEN_REGION2RA_Msk   (0x1UL << MWU_INTEN_REGION2RA_Pos)

Bit mask of REGION2RA field.

◆ MWU_INTEN_REGION2RA_Pos

#define MWU_INTEN_REGION2RA_Pos   (5UL)

Position of REGION2RA field.

◆ MWU_INTEN_REGION2WA_Disabled

#define MWU_INTEN_REGION2WA_Disabled   (0UL)

Disable

◆ MWU_INTEN_REGION2WA_Enabled

#define MWU_INTEN_REGION2WA_Enabled   (1UL)

Enable

◆ MWU_INTEN_REGION2WA_Msk

#define MWU_INTEN_REGION2WA_Msk   (0x1UL << MWU_INTEN_REGION2WA_Pos)

Bit mask of REGION2WA field.

◆ MWU_INTEN_REGION2WA_Pos

#define MWU_INTEN_REGION2WA_Pos   (4UL)

Position of REGION2WA field.

◆ MWU_INTEN_REGION3RA_Disabled

#define MWU_INTEN_REGION3RA_Disabled   (0UL)

Disable

◆ MWU_INTEN_REGION3RA_Enabled

#define MWU_INTEN_REGION3RA_Enabled   (1UL)

Enable

◆ MWU_INTEN_REGION3RA_Msk

#define MWU_INTEN_REGION3RA_Msk   (0x1UL << MWU_INTEN_REGION3RA_Pos)

Bit mask of REGION3RA field.

◆ MWU_INTEN_REGION3RA_Pos

#define MWU_INTEN_REGION3RA_Pos   (7UL)

Position of REGION3RA field.

◆ MWU_INTEN_REGION3WA_Disabled

#define MWU_INTEN_REGION3WA_Disabled   (0UL)

Disable

◆ MWU_INTEN_REGION3WA_Enabled

#define MWU_INTEN_REGION3WA_Enabled   (1UL)

Enable

◆ MWU_INTEN_REGION3WA_Msk

#define MWU_INTEN_REGION3WA_Msk   (0x1UL << MWU_INTEN_REGION3WA_Pos)

Bit mask of REGION3WA field.

◆ MWU_INTEN_REGION3WA_Pos

#define MWU_INTEN_REGION3WA_Pos   (6UL)

Position of REGION3WA field.

◆ MWU_INTENCLR_PREGION0RA_Clear

#define MWU_INTENCLR_PREGION0RA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_PREGION0RA_Disabled

#define MWU_INTENCLR_PREGION0RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_PREGION0RA_Enabled

#define MWU_INTENCLR_PREGION0RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_PREGION0RA_Msk

#define MWU_INTENCLR_PREGION0RA_Msk   (0x1UL << MWU_INTENCLR_PREGION0RA_Pos)

Bit mask of PREGION0RA field.

◆ MWU_INTENCLR_PREGION0RA_Pos

#define MWU_INTENCLR_PREGION0RA_Pos   (25UL)

Position of PREGION0RA field.

◆ MWU_INTENCLR_PREGION0WA_Clear

#define MWU_INTENCLR_PREGION0WA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_PREGION0WA_Disabled

#define MWU_INTENCLR_PREGION0WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_PREGION0WA_Enabled

#define MWU_INTENCLR_PREGION0WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_PREGION0WA_Msk

#define MWU_INTENCLR_PREGION0WA_Msk   (0x1UL << MWU_INTENCLR_PREGION0WA_Pos)

Bit mask of PREGION0WA field.

◆ MWU_INTENCLR_PREGION0WA_Pos

#define MWU_INTENCLR_PREGION0WA_Pos   (24UL)

Position of PREGION0WA field.

◆ MWU_INTENCLR_PREGION1RA_Clear

#define MWU_INTENCLR_PREGION1RA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_PREGION1RA_Disabled

#define MWU_INTENCLR_PREGION1RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_PREGION1RA_Enabled

#define MWU_INTENCLR_PREGION1RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_PREGION1RA_Msk

#define MWU_INTENCLR_PREGION1RA_Msk   (0x1UL << MWU_INTENCLR_PREGION1RA_Pos)

Bit mask of PREGION1RA field.

◆ MWU_INTENCLR_PREGION1RA_Pos

#define MWU_INTENCLR_PREGION1RA_Pos   (27UL)

Position of PREGION1RA field.

◆ MWU_INTENCLR_PREGION1WA_Clear

#define MWU_INTENCLR_PREGION1WA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_PREGION1WA_Disabled

#define MWU_INTENCLR_PREGION1WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_PREGION1WA_Enabled

#define MWU_INTENCLR_PREGION1WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_PREGION1WA_Msk

#define MWU_INTENCLR_PREGION1WA_Msk   (0x1UL << MWU_INTENCLR_PREGION1WA_Pos)

Bit mask of PREGION1WA field.

◆ MWU_INTENCLR_PREGION1WA_Pos

#define MWU_INTENCLR_PREGION1WA_Pos   (26UL)

Position of PREGION1WA field.

◆ MWU_INTENCLR_REGION0RA_Clear

#define MWU_INTENCLR_REGION0RA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_REGION0RA_Disabled

#define MWU_INTENCLR_REGION0RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_REGION0RA_Enabled

#define MWU_INTENCLR_REGION0RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_REGION0RA_Msk

#define MWU_INTENCLR_REGION0RA_Msk   (0x1UL << MWU_INTENCLR_REGION0RA_Pos)

Bit mask of REGION0RA field.

◆ MWU_INTENCLR_REGION0RA_Pos

#define MWU_INTENCLR_REGION0RA_Pos   (1UL)

Position of REGION0RA field.

◆ MWU_INTENCLR_REGION0WA_Clear

#define MWU_INTENCLR_REGION0WA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_REGION0WA_Disabled

#define MWU_INTENCLR_REGION0WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_REGION0WA_Enabled

#define MWU_INTENCLR_REGION0WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_REGION0WA_Msk

#define MWU_INTENCLR_REGION0WA_Msk   (0x1UL << MWU_INTENCLR_REGION0WA_Pos)

Bit mask of REGION0WA field.

◆ MWU_INTENCLR_REGION0WA_Pos

#define MWU_INTENCLR_REGION0WA_Pos   (0UL)

Position of REGION0WA field.

◆ MWU_INTENCLR_REGION1RA_Clear

#define MWU_INTENCLR_REGION1RA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_REGION1RA_Disabled

#define MWU_INTENCLR_REGION1RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_REGION1RA_Enabled

#define MWU_INTENCLR_REGION1RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_REGION1RA_Msk

#define MWU_INTENCLR_REGION1RA_Msk   (0x1UL << MWU_INTENCLR_REGION1RA_Pos)

Bit mask of REGION1RA field.

◆ MWU_INTENCLR_REGION1RA_Pos

#define MWU_INTENCLR_REGION1RA_Pos   (3UL)

Position of REGION1RA field.

◆ MWU_INTENCLR_REGION1WA_Clear

#define MWU_INTENCLR_REGION1WA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_REGION1WA_Disabled

#define MWU_INTENCLR_REGION1WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_REGION1WA_Enabled

#define MWU_INTENCLR_REGION1WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_REGION1WA_Msk

#define MWU_INTENCLR_REGION1WA_Msk   (0x1UL << MWU_INTENCLR_REGION1WA_Pos)

Bit mask of REGION1WA field.

◆ MWU_INTENCLR_REGION1WA_Pos

#define MWU_INTENCLR_REGION1WA_Pos   (2UL)

Position of REGION1WA field.

◆ MWU_INTENCLR_REGION2RA_Clear

#define MWU_INTENCLR_REGION2RA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_REGION2RA_Disabled

#define MWU_INTENCLR_REGION2RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_REGION2RA_Enabled

#define MWU_INTENCLR_REGION2RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_REGION2RA_Msk

#define MWU_INTENCLR_REGION2RA_Msk   (0x1UL << MWU_INTENCLR_REGION2RA_Pos)

Bit mask of REGION2RA field.

◆ MWU_INTENCLR_REGION2RA_Pos

#define MWU_INTENCLR_REGION2RA_Pos   (5UL)

Position of REGION2RA field.

◆ MWU_INTENCLR_REGION2WA_Clear

#define MWU_INTENCLR_REGION2WA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_REGION2WA_Disabled

#define MWU_INTENCLR_REGION2WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_REGION2WA_Enabled

#define MWU_INTENCLR_REGION2WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_REGION2WA_Msk

#define MWU_INTENCLR_REGION2WA_Msk   (0x1UL << MWU_INTENCLR_REGION2WA_Pos)

Bit mask of REGION2WA field.

◆ MWU_INTENCLR_REGION2WA_Pos

#define MWU_INTENCLR_REGION2WA_Pos   (4UL)

Position of REGION2WA field.

◆ MWU_INTENCLR_REGION3RA_Clear

#define MWU_INTENCLR_REGION3RA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_REGION3RA_Disabled

#define MWU_INTENCLR_REGION3RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_REGION3RA_Enabled

#define MWU_INTENCLR_REGION3RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_REGION3RA_Msk

#define MWU_INTENCLR_REGION3RA_Msk   (0x1UL << MWU_INTENCLR_REGION3RA_Pos)

Bit mask of REGION3RA field.

◆ MWU_INTENCLR_REGION3RA_Pos

#define MWU_INTENCLR_REGION3RA_Pos   (7UL)

Position of REGION3RA field.

◆ MWU_INTENCLR_REGION3WA_Clear

#define MWU_INTENCLR_REGION3WA_Clear   (1UL)

Disable

◆ MWU_INTENCLR_REGION3WA_Disabled

#define MWU_INTENCLR_REGION3WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENCLR_REGION3WA_Enabled

#define MWU_INTENCLR_REGION3WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENCLR_REGION3WA_Msk

#define MWU_INTENCLR_REGION3WA_Msk   (0x1UL << MWU_INTENCLR_REGION3WA_Pos)

Bit mask of REGION3WA field.

◆ MWU_INTENCLR_REGION3WA_Pos

#define MWU_INTENCLR_REGION3WA_Pos   (6UL)

Position of REGION3WA field.

◆ MWU_INTENSET_PREGION0RA_Disabled

#define MWU_INTENSET_PREGION0RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_PREGION0RA_Enabled

#define MWU_INTENSET_PREGION0RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_PREGION0RA_Msk

#define MWU_INTENSET_PREGION0RA_Msk   (0x1UL << MWU_INTENSET_PREGION0RA_Pos)

Bit mask of PREGION0RA field.

◆ MWU_INTENSET_PREGION0RA_Pos

#define MWU_INTENSET_PREGION0RA_Pos   (25UL)

Position of PREGION0RA field.

◆ MWU_INTENSET_PREGION0RA_Set

#define MWU_INTENSET_PREGION0RA_Set   (1UL)

Enable

◆ MWU_INTENSET_PREGION0WA_Disabled

#define MWU_INTENSET_PREGION0WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_PREGION0WA_Enabled

#define MWU_INTENSET_PREGION0WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_PREGION0WA_Msk

#define MWU_INTENSET_PREGION0WA_Msk   (0x1UL << MWU_INTENSET_PREGION0WA_Pos)

Bit mask of PREGION0WA field.

◆ MWU_INTENSET_PREGION0WA_Pos

#define MWU_INTENSET_PREGION0WA_Pos   (24UL)

Position of PREGION0WA field.

◆ MWU_INTENSET_PREGION0WA_Set

#define MWU_INTENSET_PREGION0WA_Set   (1UL)

Enable

◆ MWU_INTENSET_PREGION1RA_Disabled

#define MWU_INTENSET_PREGION1RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_PREGION1RA_Enabled

#define MWU_INTENSET_PREGION1RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_PREGION1RA_Msk

#define MWU_INTENSET_PREGION1RA_Msk   (0x1UL << MWU_INTENSET_PREGION1RA_Pos)

Bit mask of PREGION1RA field.

◆ MWU_INTENSET_PREGION1RA_Pos

#define MWU_INTENSET_PREGION1RA_Pos   (27UL)

Position of PREGION1RA field.

◆ MWU_INTENSET_PREGION1RA_Set

#define MWU_INTENSET_PREGION1RA_Set   (1UL)

Enable

◆ MWU_INTENSET_PREGION1WA_Disabled

#define MWU_INTENSET_PREGION1WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_PREGION1WA_Enabled

#define MWU_INTENSET_PREGION1WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_PREGION1WA_Msk

#define MWU_INTENSET_PREGION1WA_Msk   (0x1UL << MWU_INTENSET_PREGION1WA_Pos)

Bit mask of PREGION1WA field.

◆ MWU_INTENSET_PREGION1WA_Pos

#define MWU_INTENSET_PREGION1WA_Pos   (26UL)

Position of PREGION1WA field.

◆ MWU_INTENSET_PREGION1WA_Set

#define MWU_INTENSET_PREGION1WA_Set   (1UL)

Enable

◆ MWU_INTENSET_REGION0RA_Disabled

#define MWU_INTENSET_REGION0RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_REGION0RA_Enabled

#define MWU_INTENSET_REGION0RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_REGION0RA_Msk

#define MWU_INTENSET_REGION0RA_Msk   (0x1UL << MWU_INTENSET_REGION0RA_Pos)

Bit mask of REGION0RA field.

◆ MWU_INTENSET_REGION0RA_Pos

#define MWU_INTENSET_REGION0RA_Pos   (1UL)

Position of REGION0RA field.

◆ MWU_INTENSET_REGION0RA_Set

#define MWU_INTENSET_REGION0RA_Set   (1UL)

Enable

◆ MWU_INTENSET_REGION0WA_Disabled

#define MWU_INTENSET_REGION0WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_REGION0WA_Enabled

#define MWU_INTENSET_REGION0WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_REGION0WA_Msk

#define MWU_INTENSET_REGION0WA_Msk   (0x1UL << MWU_INTENSET_REGION0WA_Pos)

Bit mask of REGION0WA field.

◆ MWU_INTENSET_REGION0WA_Pos

#define MWU_INTENSET_REGION0WA_Pos   (0UL)

Position of REGION0WA field.

◆ MWU_INTENSET_REGION0WA_Set

#define MWU_INTENSET_REGION0WA_Set   (1UL)

Enable

◆ MWU_INTENSET_REGION1RA_Disabled

#define MWU_INTENSET_REGION1RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_REGION1RA_Enabled

#define MWU_INTENSET_REGION1RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_REGION1RA_Msk

#define MWU_INTENSET_REGION1RA_Msk   (0x1UL << MWU_INTENSET_REGION1RA_Pos)

Bit mask of REGION1RA field.

◆ MWU_INTENSET_REGION1RA_Pos

#define MWU_INTENSET_REGION1RA_Pos   (3UL)

Position of REGION1RA field.

◆ MWU_INTENSET_REGION1RA_Set

#define MWU_INTENSET_REGION1RA_Set   (1UL)

Enable

◆ MWU_INTENSET_REGION1WA_Disabled

#define MWU_INTENSET_REGION1WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_REGION1WA_Enabled

#define MWU_INTENSET_REGION1WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_REGION1WA_Msk

#define MWU_INTENSET_REGION1WA_Msk   (0x1UL << MWU_INTENSET_REGION1WA_Pos)

Bit mask of REGION1WA field.

◆ MWU_INTENSET_REGION1WA_Pos

#define MWU_INTENSET_REGION1WA_Pos   (2UL)

Position of REGION1WA field.

◆ MWU_INTENSET_REGION1WA_Set

#define MWU_INTENSET_REGION1WA_Set   (1UL)

Enable

◆ MWU_INTENSET_REGION2RA_Disabled

#define MWU_INTENSET_REGION2RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_REGION2RA_Enabled

#define MWU_INTENSET_REGION2RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_REGION2RA_Msk

#define MWU_INTENSET_REGION2RA_Msk   (0x1UL << MWU_INTENSET_REGION2RA_Pos)

Bit mask of REGION2RA field.

◆ MWU_INTENSET_REGION2RA_Pos

#define MWU_INTENSET_REGION2RA_Pos   (5UL)

Position of REGION2RA field.

◆ MWU_INTENSET_REGION2RA_Set

#define MWU_INTENSET_REGION2RA_Set   (1UL)

Enable

◆ MWU_INTENSET_REGION2WA_Disabled

#define MWU_INTENSET_REGION2WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_REGION2WA_Enabled

#define MWU_INTENSET_REGION2WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_REGION2WA_Msk

#define MWU_INTENSET_REGION2WA_Msk   (0x1UL << MWU_INTENSET_REGION2WA_Pos)

Bit mask of REGION2WA field.

◆ MWU_INTENSET_REGION2WA_Pos

#define MWU_INTENSET_REGION2WA_Pos   (4UL)

Position of REGION2WA field.

◆ MWU_INTENSET_REGION2WA_Set

#define MWU_INTENSET_REGION2WA_Set   (1UL)

Enable

◆ MWU_INTENSET_REGION3RA_Disabled

#define MWU_INTENSET_REGION3RA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_REGION3RA_Enabled

#define MWU_INTENSET_REGION3RA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_REGION3RA_Msk

#define MWU_INTENSET_REGION3RA_Msk   (0x1UL << MWU_INTENSET_REGION3RA_Pos)

Bit mask of REGION3RA field.

◆ MWU_INTENSET_REGION3RA_Pos

#define MWU_INTENSET_REGION3RA_Pos   (7UL)

Position of REGION3RA field.

◆ MWU_INTENSET_REGION3RA_Set

#define MWU_INTENSET_REGION3RA_Set   (1UL)

Enable

◆ MWU_INTENSET_REGION3WA_Disabled

#define MWU_INTENSET_REGION3WA_Disabled   (0UL)

Read: Disabled

◆ MWU_INTENSET_REGION3WA_Enabled

#define MWU_INTENSET_REGION3WA_Enabled   (1UL)

Read: Enabled

◆ MWU_INTENSET_REGION3WA_Msk

#define MWU_INTENSET_REGION3WA_Msk   (0x1UL << MWU_INTENSET_REGION3WA_Pos)

Bit mask of REGION3WA field.

◆ MWU_INTENSET_REGION3WA_Pos

#define MWU_INTENSET_REGION3WA_Pos   (6UL)

Position of REGION3WA field.

◆ MWU_INTENSET_REGION3WA_Set

#define MWU_INTENSET_REGION3WA_Set   (1UL)

Enable

◆ MWU_NMIEN_PREGION0RA_Disabled

#define MWU_NMIEN_PREGION0RA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_PREGION0RA_Enabled

#define MWU_NMIEN_PREGION0RA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_PREGION0RA_Msk

#define MWU_NMIEN_PREGION0RA_Msk   (0x1UL << MWU_NMIEN_PREGION0RA_Pos)

Bit mask of PREGION0RA field.

◆ MWU_NMIEN_PREGION0RA_Pos

#define MWU_NMIEN_PREGION0RA_Pos   (25UL)

Position of PREGION0RA field.

◆ MWU_NMIEN_PREGION0WA_Disabled

#define MWU_NMIEN_PREGION0WA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_PREGION0WA_Enabled

#define MWU_NMIEN_PREGION0WA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_PREGION0WA_Msk

#define MWU_NMIEN_PREGION0WA_Msk   (0x1UL << MWU_NMIEN_PREGION0WA_Pos)

Bit mask of PREGION0WA field.

◆ MWU_NMIEN_PREGION0WA_Pos

#define MWU_NMIEN_PREGION0WA_Pos   (24UL)

Position of PREGION0WA field.

◆ MWU_NMIEN_PREGION1RA_Disabled

#define MWU_NMIEN_PREGION1RA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_PREGION1RA_Enabled

#define MWU_NMIEN_PREGION1RA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_PREGION1RA_Msk

#define MWU_NMIEN_PREGION1RA_Msk   (0x1UL << MWU_NMIEN_PREGION1RA_Pos)

Bit mask of PREGION1RA field.

◆ MWU_NMIEN_PREGION1RA_Pos

#define MWU_NMIEN_PREGION1RA_Pos   (27UL)

Position of PREGION1RA field.

◆ MWU_NMIEN_PREGION1WA_Disabled

#define MWU_NMIEN_PREGION1WA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_PREGION1WA_Enabled

#define MWU_NMIEN_PREGION1WA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_PREGION1WA_Msk

#define MWU_NMIEN_PREGION1WA_Msk   (0x1UL << MWU_NMIEN_PREGION1WA_Pos)

Bit mask of PREGION1WA field.

◆ MWU_NMIEN_PREGION1WA_Pos

#define MWU_NMIEN_PREGION1WA_Pos   (26UL)

Position of PREGION1WA field.

◆ MWU_NMIEN_REGION0RA_Disabled

#define MWU_NMIEN_REGION0RA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_REGION0RA_Enabled

#define MWU_NMIEN_REGION0RA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_REGION0RA_Msk

#define MWU_NMIEN_REGION0RA_Msk   (0x1UL << MWU_NMIEN_REGION0RA_Pos)

Bit mask of REGION0RA field.

◆ MWU_NMIEN_REGION0RA_Pos

#define MWU_NMIEN_REGION0RA_Pos   (1UL)

Position of REGION0RA field.

◆ MWU_NMIEN_REGION0WA_Disabled

#define MWU_NMIEN_REGION0WA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_REGION0WA_Enabled

#define MWU_NMIEN_REGION0WA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_REGION0WA_Msk

#define MWU_NMIEN_REGION0WA_Msk   (0x1UL << MWU_NMIEN_REGION0WA_Pos)

Bit mask of REGION0WA field.

◆ MWU_NMIEN_REGION0WA_Pos

#define MWU_NMIEN_REGION0WA_Pos   (0UL)

Position of REGION0WA field.

◆ MWU_NMIEN_REGION1RA_Disabled

#define MWU_NMIEN_REGION1RA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_REGION1RA_Enabled

#define MWU_NMIEN_REGION1RA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_REGION1RA_Msk

#define MWU_NMIEN_REGION1RA_Msk   (0x1UL << MWU_NMIEN_REGION1RA_Pos)

Bit mask of REGION1RA field.

◆ MWU_NMIEN_REGION1RA_Pos

#define MWU_NMIEN_REGION1RA_Pos   (3UL)

Position of REGION1RA field.

◆ MWU_NMIEN_REGION1WA_Disabled

#define MWU_NMIEN_REGION1WA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_REGION1WA_Enabled

#define MWU_NMIEN_REGION1WA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_REGION1WA_Msk

#define MWU_NMIEN_REGION1WA_Msk   (0x1UL << MWU_NMIEN_REGION1WA_Pos)

Bit mask of REGION1WA field.

◆ MWU_NMIEN_REGION1WA_Pos

#define MWU_NMIEN_REGION1WA_Pos   (2UL)

Position of REGION1WA field.

◆ MWU_NMIEN_REGION2RA_Disabled

#define MWU_NMIEN_REGION2RA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_REGION2RA_Enabled

#define MWU_NMIEN_REGION2RA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_REGION2RA_Msk

#define MWU_NMIEN_REGION2RA_Msk   (0x1UL << MWU_NMIEN_REGION2RA_Pos)

Bit mask of REGION2RA field.

◆ MWU_NMIEN_REGION2RA_Pos

#define MWU_NMIEN_REGION2RA_Pos   (5UL)

Position of REGION2RA field.

◆ MWU_NMIEN_REGION2WA_Disabled

#define MWU_NMIEN_REGION2WA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_REGION2WA_Enabled

#define MWU_NMIEN_REGION2WA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_REGION2WA_Msk

#define MWU_NMIEN_REGION2WA_Msk   (0x1UL << MWU_NMIEN_REGION2WA_Pos)

Bit mask of REGION2WA field.

◆ MWU_NMIEN_REGION2WA_Pos

#define MWU_NMIEN_REGION2WA_Pos   (4UL)

Position of REGION2WA field.

◆ MWU_NMIEN_REGION3RA_Disabled

#define MWU_NMIEN_REGION3RA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_REGION3RA_Enabled

#define MWU_NMIEN_REGION3RA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_REGION3RA_Msk

#define MWU_NMIEN_REGION3RA_Msk   (0x1UL << MWU_NMIEN_REGION3RA_Pos)

Bit mask of REGION3RA field.

◆ MWU_NMIEN_REGION3RA_Pos

#define MWU_NMIEN_REGION3RA_Pos   (7UL)

Position of REGION3RA field.

◆ MWU_NMIEN_REGION3WA_Disabled

#define MWU_NMIEN_REGION3WA_Disabled   (0UL)

Disable

◆ MWU_NMIEN_REGION3WA_Enabled

#define MWU_NMIEN_REGION3WA_Enabled   (1UL)

Enable

◆ MWU_NMIEN_REGION3WA_Msk

#define MWU_NMIEN_REGION3WA_Msk   (0x1UL << MWU_NMIEN_REGION3WA_Pos)

Bit mask of REGION3WA field.

◆ MWU_NMIEN_REGION3WA_Pos

#define MWU_NMIEN_REGION3WA_Pos   (6UL)

Position of REGION3WA field.

◆ MWU_NMIENCLR_PREGION0RA_Clear

#define MWU_NMIENCLR_PREGION0RA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_PREGION0RA_Disabled

#define MWU_NMIENCLR_PREGION0RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_PREGION0RA_Enabled

#define MWU_NMIENCLR_PREGION0RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_PREGION0RA_Msk

#define MWU_NMIENCLR_PREGION0RA_Msk   (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos)

Bit mask of PREGION0RA field.

◆ MWU_NMIENCLR_PREGION0RA_Pos

#define MWU_NMIENCLR_PREGION0RA_Pos   (25UL)

Position of PREGION0RA field.

◆ MWU_NMIENCLR_PREGION0WA_Clear

#define MWU_NMIENCLR_PREGION0WA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_PREGION0WA_Disabled

#define MWU_NMIENCLR_PREGION0WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_PREGION0WA_Enabled

#define MWU_NMIENCLR_PREGION0WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_PREGION0WA_Msk

#define MWU_NMIENCLR_PREGION0WA_Msk   (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos)

Bit mask of PREGION0WA field.

◆ MWU_NMIENCLR_PREGION0WA_Pos

#define MWU_NMIENCLR_PREGION0WA_Pos   (24UL)

Position of PREGION0WA field.

◆ MWU_NMIENCLR_PREGION1RA_Clear

#define MWU_NMIENCLR_PREGION1RA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_PREGION1RA_Disabled

#define MWU_NMIENCLR_PREGION1RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_PREGION1RA_Enabled

#define MWU_NMIENCLR_PREGION1RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_PREGION1RA_Msk

#define MWU_NMIENCLR_PREGION1RA_Msk   (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos)

Bit mask of PREGION1RA field.

◆ MWU_NMIENCLR_PREGION1RA_Pos

#define MWU_NMIENCLR_PREGION1RA_Pos   (27UL)

Position of PREGION1RA field.

◆ MWU_NMIENCLR_PREGION1WA_Clear

#define MWU_NMIENCLR_PREGION1WA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_PREGION1WA_Disabled

#define MWU_NMIENCLR_PREGION1WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_PREGION1WA_Enabled

#define MWU_NMIENCLR_PREGION1WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_PREGION1WA_Msk

#define MWU_NMIENCLR_PREGION1WA_Msk   (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos)

Bit mask of PREGION1WA field.

◆ MWU_NMIENCLR_PREGION1WA_Pos

#define MWU_NMIENCLR_PREGION1WA_Pos   (26UL)

Position of PREGION1WA field.

◆ MWU_NMIENCLR_REGION0RA_Clear

#define MWU_NMIENCLR_REGION0RA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_REGION0RA_Disabled

#define MWU_NMIENCLR_REGION0RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_REGION0RA_Enabled

#define MWU_NMIENCLR_REGION0RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_REGION0RA_Msk

#define MWU_NMIENCLR_REGION0RA_Msk   (0x1UL << MWU_NMIENCLR_REGION0RA_Pos)

Bit mask of REGION0RA field.

◆ MWU_NMIENCLR_REGION0RA_Pos

#define MWU_NMIENCLR_REGION0RA_Pos   (1UL)

Position of REGION0RA field.

◆ MWU_NMIENCLR_REGION0WA_Clear

#define MWU_NMIENCLR_REGION0WA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_REGION0WA_Disabled

#define MWU_NMIENCLR_REGION0WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_REGION0WA_Enabled

#define MWU_NMIENCLR_REGION0WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_REGION0WA_Msk

#define MWU_NMIENCLR_REGION0WA_Msk   (0x1UL << MWU_NMIENCLR_REGION0WA_Pos)

Bit mask of REGION0WA field.

◆ MWU_NMIENCLR_REGION0WA_Pos

#define MWU_NMIENCLR_REGION0WA_Pos   (0UL)

Position of REGION0WA field.

◆ MWU_NMIENCLR_REGION1RA_Clear

#define MWU_NMIENCLR_REGION1RA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_REGION1RA_Disabled

#define MWU_NMIENCLR_REGION1RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_REGION1RA_Enabled

#define MWU_NMIENCLR_REGION1RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_REGION1RA_Msk

#define MWU_NMIENCLR_REGION1RA_Msk   (0x1UL << MWU_NMIENCLR_REGION1RA_Pos)

Bit mask of REGION1RA field.

◆ MWU_NMIENCLR_REGION1RA_Pos

#define MWU_NMIENCLR_REGION1RA_Pos   (3UL)

Position of REGION1RA field.

◆ MWU_NMIENCLR_REGION1WA_Clear

#define MWU_NMIENCLR_REGION1WA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_REGION1WA_Disabled

#define MWU_NMIENCLR_REGION1WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_REGION1WA_Enabled

#define MWU_NMIENCLR_REGION1WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_REGION1WA_Msk

#define MWU_NMIENCLR_REGION1WA_Msk   (0x1UL << MWU_NMIENCLR_REGION1WA_Pos)

Bit mask of REGION1WA field.

◆ MWU_NMIENCLR_REGION1WA_Pos

#define MWU_NMIENCLR_REGION1WA_Pos   (2UL)

Position of REGION1WA field.

◆ MWU_NMIENCLR_REGION2RA_Clear

#define MWU_NMIENCLR_REGION2RA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_REGION2RA_Disabled

#define MWU_NMIENCLR_REGION2RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_REGION2RA_Enabled

#define MWU_NMIENCLR_REGION2RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_REGION2RA_Msk

#define MWU_NMIENCLR_REGION2RA_Msk   (0x1UL << MWU_NMIENCLR_REGION2RA_Pos)

Bit mask of REGION2RA field.

◆ MWU_NMIENCLR_REGION2RA_Pos

#define MWU_NMIENCLR_REGION2RA_Pos   (5UL)

Position of REGION2RA field.

◆ MWU_NMIENCLR_REGION2WA_Clear

#define MWU_NMIENCLR_REGION2WA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_REGION2WA_Disabled

#define MWU_NMIENCLR_REGION2WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_REGION2WA_Enabled

#define MWU_NMIENCLR_REGION2WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_REGION2WA_Msk

#define MWU_NMIENCLR_REGION2WA_Msk   (0x1UL << MWU_NMIENCLR_REGION2WA_Pos)

Bit mask of REGION2WA field.

◆ MWU_NMIENCLR_REGION2WA_Pos

#define MWU_NMIENCLR_REGION2WA_Pos   (4UL)

Position of REGION2WA field.

◆ MWU_NMIENCLR_REGION3RA_Clear

#define MWU_NMIENCLR_REGION3RA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_REGION3RA_Disabled

#define MWU_NMIENCLR_REGION3RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_REGION3RA_Enabled

#define MWU_NMIENCLR_REGION3RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_REGION3RA_Msk

#define MWU_NMIENCLR_REGION3RA_Msk   (0x1UL << MWU_NMIENCLR_REGION3RA_Pos)

Bit mask of REGION3RA field.

◆ MWU_NMIENCLR_REGION3RA_Pos

#define MWU_NMIENCLR_REGION3RA_Pos   (7UL)

Position of REGION3RA field.

◆ MWU_NMIENCLR_REGION3WA_Clear

#define MWU_NMIENCLR_REGION3WA_Clear   (1UL)

Disable

◆ MWU_NMIENCLR_REGION3WA_Disabled

#define MWU_NMIENCLR_REGION3WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENCLR_REGION3WA_Enabled

#define MWU_NMIENCLR_REGION3WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENCLR_REGION3WA_Msk

#define MWU_NMIENCLR_REGION3WA_Msk   (0x1UL << MWU_NMIENCLR_REGION3WA_Pos)

Bit mask of REGION3WA field.

◆ MWU_NMIENCLR_REGION3WA_Pos

#define MWU_NMIENCLR_REGION3WA_Pos   (6UL)

Position of REGION3WA field.

◆ MWU_NMIENSET_PREGION0RA_Disabled

#define MWU_NMIENSET_PREGION0RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_PREGION0RA_Enabled

#define MWU_NMIENSET_PREGION0RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_PREGION0RA_Msk

#define MWU_NMIENSET_PREGION0RA_Msk   (0x1UL << MWU_NMIENSET_PREGION0RA_Pos)

Bit mask of PREGION0RA field.

◆ MWU_NMIENSET_PREGION0RA_Pos

#define MWU_NMIENSET_PREGION0RA_Pos   (25UL)

Position of PREGION0RA field.

◆ MWU_NMIENSET_PREGION0RA_Set

#define MWU_NMIENSET_PREGION0RA_Set   (1UL)

Enable

◆ MWU_NMIENSET_PREGION0WA_Disabled

#define MWU_NMIENSET_PREGION0WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_PREGION0WA_Enabled

#define MWU_NMIENSET_PREGION0WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_PREGION0WA_Msk

#define MWU_NMIENSET_PREGION0WA_Msk   (0x1UL << MWU_NMIENSET_PREGION0WA_Pos)

Bit mask of PREGION0WA field.

◆ MWU_NMIENSET_PREGION0WA_Pos

#define MWU_NMIENSET_PREGION0WA_Pos   (24UL)

Position of PREGION0WA field.

◆ MWU_NMIENSET_PREGION0WA_Set

#define MWU_NMIENSET_PREGION0WA_Set   (1UL)

Enable

◆ MWU_NMIENSET_PREGION1RA_Disabled

#define MWU_NMIENSET_PREGION1RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_PREGION1RA_Enabled

#define MWU_NMIENSET_PREGION1RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_PREGION1RA_Msk

#define MWU_NMIENSET_PREGION1RA_Msk   (0x1UL << MWU_NMIENSET_PREGION1RA_Pos)

Bit mask of PREGION1RA field.

◆ MWU_NMIENSET_PREGION1RA_Pos

#define MWU_NMIENSET_PREGION1RA_Pos   (27UL)

Position of PREGION1RA field.

◆ MWU_NMIENSET_PREGION1RA_Set

#define MWU_NMIENSET_PREGION1RA_Set   (1UL)

Enable

◆ MWU_NMIENSET_PREGION1WA_Disabled

#define MWU_NMIENSET_PREGION1WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_PREGION1WA_Enabled

#define MWU_NMIENSET_PREGION1WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_PREGION1WA_Msk

#define MWU_NMIENSET_PREGION1WA_Msk   (0x1UL << MWU_NMIENSET_PREGION1WA_Pos)

Bit mask of PREGION1WA field.

◆ MWU_NMIENSET_PREGION1WA_Pos

#define MWU_NMIENSET_PREGION1WA_Pos   (26UL)

Position of PREGION1WA field.

◆ MWU_NMIENSET_PREGION1WA_Set

#define MWU_NMIENSET_PREGION1WA_Set   (1UL)

Enable

◆ MWU_NMIENSET_REGION0RA_Disabled

#define MWU_NMIENSET_REGION0RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_REGION0RA_Enabled

#define MWU_NMIENSET_REGION0RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_REGION0RA_Msk

#define MWU_NMIENSET_REGION0RA_Msk   (0x1UL << MWU_NMIENSET_REGION0RA_Pos)

Bit mask of REGION0RA field.

◆ MWU_NMIENSET_REGION0RA_Pos

#define MWU_NMIENSET_REGION0RA_Pos   (1UL)

Position of REGION0RA field.

◆ MWU_NMIENSET_REGION0RA_Set

#define MWU_NMIENSET_REGION0RA_Set   (1UL)

Enable

◆ MWU_NMIENSET_REGION0WA_Disabled

#define MWU_NMIENSET_REGION0WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_REGION0WA_Enabled

#define MWU_NMIENSET_REGION0WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_REGION0WA_Msk

#define MWU_NMIENSET_REGION0WA_Msk   (0x1UL << MWU_NMIENSET_REGION0WA_Pos)

Bit mask of REGION0WA field.

◆ MWU_NMIENSET_REGION0WA_Pos

#define MWU_NMIENSET_REGION0WA_Pos   (0UL)

Position of REGION0WA field.

◆ MWU_NMIENSET_REGION0WA_Set

#define MWU_NMIENSET_REGION0WA_Set   (1UL)

Enable

◆ MWU_NMIENSET_REGION1RA_Disabled

#define MWU_NMIENSET_REGION1RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_REGION1RA_Enabled

#define MWU_NMIENSET_REGION1RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_REGION1RA_Msk

#define MWU_NMIENSET_REGION1RA_Msk   (0x1UL << MWU_NMIENSET_REGION1RA_Pos)

Bit mask of REGION1RA field.

◆ MWU_NMIENSET_REGION1RA_Pos

#define MWU_NMIENSET_REGION1RA_Pos   (3UL)

Position of REGION1RA field.

◆ MWU_NMIENSET_REGION1RA_Set

#define MWU_NMIENSET_REGION1RA_Set   (1UL)

Enable

◆ MWU_NMIENSET_REGION1WA_Disabled

#define MWU_NMIENSET_REGION1WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_REGION1WA_Enabled

#define MWU_NMIENSET_REGION1WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_REGION1WA_Msk

#define MWU_NMIENSET_REGION1WA_Msk   (0x1UL << MWU_NMIENSET_REGION1WA_Pos)

Bit mask of REGION1WA field.

◆ MWU_NMIENSET_REGION1WA_Pos

#define MWU_NMIENSET_REGION1WA_Pos   (2UL)

Position of REGION1WA field.

◆ MWU_NMIENSET_REGION1WA_Set

#define MWU_NMIENSET_REGION1WA_Set   (1UL)

Enable

◆ MWU_NMIENSET_REGION2RA_Disabled

#define MWU_NMIENSET_REGION2RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_REGION2RA_Enabled

#define MWU_NMIENSET_REGION2RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_REGION2RA_Msk

#define MWU_NMIENSET_REGION2RA_Msk   (0x1UL << MWU_NMIENSET_REGION2RA_Pos)

Bit mask of REGION2RA field.

◆ MWU_NMIENSET_REGION2RA_Pos

#define MWU_NMIENSET_REGION2RA_Pos   (5UL)

Position of REGION2RA field.

◆ MWU_NMIENSET_REGION2RA_Set

#define MWU_NMIENSET_REGION2RA_Set   (1UL)

Enable

◆ MWU_NMIENSET_REGION2WA_Disabled

#define MWU_NMIENSET_REGION2WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_REGION2WA_Enabled

#define MWU_NMIENSET_REGION2WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_REGION2WA_Msk

#define MWU_NMIENSET_REGION2WA_Msk   (0x1UL << MWU_NMIENSET_REGION2WA_Pos)

Bit mask of REGION2WA field.

◆ MWU_NMIENSET_REGION2WA_Pos

#define MWU_NMIENSET_REGION2WA_Pos   (4UL)

Position of REGION2WA field.

◆ MWU_NMIENSET_REGION2WA_Set

#define MWU_NMIENSET_REGION2WA_Set   (1UL)

Enable

◆ MWU_NMIENSET_REGION3RA_Disabled

#define MWU_NMIENSET_REGION3RA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_REGION3RA_Enabled

#define MWU_NMIENSET_REGION3RA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_REGION3RA_Msk

#define MWU_NMIENSET_REGION3RA_Msk   (0x1UL << MWU_NMIENSET_REGION3RA_Pos)

Bit mask of REGION3RA field.

◆ MWU_NMIENSET_REGION3RA_Pos

#define MWU_NMIENSET_REGION3RA_Pos   (7UL)

Position of REGION3RA field.

◆ MWU_NMIENSET_REGION3RA_Set

#define MWU_NMIENSET_REGION3RA_Set   (1UL)

Enable

◆ MWU_NMIENSET_REGION3WA_Disabled

#define MWU_NMIENSET_REGION3WA_Disabled   (0UL)

Read: Disabled

◆ MWU_NMIENSET_REGION3WA_Enabled

#define MWU_NMIENSET_REGION3WA_Enabled   (1UL)

Read: Enabled

◆ MWU_NMIENSET_REGION3WA_Msk

#define MWU_NMIENSET_REGION3WA_Msk   (0x1UL << MWU_NMIENSET_REGION3WA_Pos)

Bit mask of REGION3WA field.

◆ MWU_NMIENSET_REGION3WA_Pos

#define MWU_NMIENSET_REGION3WA_Pos   (6UL)

Position of REGION3WA field.

◆ MWU_NMIENSET_REGION3WA_Set

#define MWU_NMIENSET_REGION3WA_Set   (1UL)

Enable

◆ MWU_PERREGION_SUBSTATRA_SR0_Access

#define MWU_PERREGION_SUBSTATRA_SR0_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR0_Msk

#define MWU_PERREGION_SUBSTATRA_SR0_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos)

Bit mask of SR0 field.

◆ MWU_PERREGION_SUBSTATRA_SR0_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR0_Pos

#define MWU_PERREGION_SUBSTATRA_SR0_Pos   (0UL)

Position of SR0 field.

◆ MWU_PERREGION_SUBSTATRA_SR10_Access

#define MWU_PERREGION_SUBSTATRA_SR10_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR10_Msk

#define MWU_PERREGION_SUBSTATRA_SR10_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos)

Bit mask of SR10 field.

◆ MWU_PERREGION_SUBSTATRA_SR10_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR10_Pos

#define MWU_PERREGION_SUBSTATRA_SR10_Pos   (10UL)

Position of SR10 field.

◆ MWU_PERREGION_SUBSTATRA_SR11_Access

#define MWU_PERREGION_SUBSTATRA_SR11_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR11_Msk

#define MWU_PERREGION_SUBSTATRA_SR11_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos)

Bit mask of SR11 field.

◆ MWU_PERREGION_SUBSTATRA_SR11_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR11_Pos

#define MWU_PERREGION_SUBSTATRA_SR11_Pos   (11UL)

Position of SR11 field.

◆ MWU_PERREGION_SUBSTATRA_SR12_Access

#define MWU_PERREGION_SUBSTATRA_SR12_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR12_Msk

#define MWU_PERREGION_SUBSTATRA_SR12_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos)

Bit mask of SR12 field.

◆ MWU_PERREGION_SUBSTATRA_SR12_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR12_Pos

#define MWU_PERREGION_SUBSTATRA_SR12_Pos   (12UL)

Position of SR12 field.

◆ MWU_PERREGION_SUBSTATRA_SR13_Access

#define MWU_PERREGION_SUBSTATRA_SR13_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR13_Msk

#define MWU_PERREGION_SUBSTATRA_SR13_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos)

Bit mask of SR13 field.

◆ MWU_PERREGION_SUBSTATRA_SR13_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR13_Pos

#define MWU_PERREGION_SUBSTATRA_SR13_Pos   (13UL)

Position of SR13 field.

◆ MWU_PERREGION_SUBSTATRA_SR14_Access

#define MWU_PERREGION_SUBSTATRA_SR14_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR14_Msk

#define MWU_PERREGION_SUBSTATRA_SR14_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos)

Bit mask of SR14 field.

◆ MWU_PERREGION_SUBSTATRA_SR14_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR14_Pos

#define MWU_PERREGION_SUBSTATRA_SR14_Pos   (14UL)

Position of SR14 field.

◆ MWU_PERREGION_SUBSTATRA_SR15_Access

#define MWU_PERREGION_SUBSTATRA_SR15_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR15_Msk

#define MWU_PERREGION_SUBSTATRA_SR15_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos)

Bit mask of SR15 field.

◆ MWU_PERREGION_SUBSTATRA_SR15_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR15_Pos

#define MWU_PERREGION_SUBSTATRA_SR15_Pos   (15UL)

Position of SR15 field.

◆ MWU_PERREGION_SUBSTATRA_SR16_Access

#define MWU_PERREGION_SUBSTATRA_SR16_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR16_Msk

#define MWU_PERREGION_SUBSTATRA_SR16_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos)

Bit mask of SR16 field.

◆ MWU_PERREGION_SUBSTATRA_SR16_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR16_Pos

#define MWU_PERREGION_SUBSTATRA_SR16_Pos   (16UL)

Position of SR16 field.

◆ MWU_PERREGION_SUBSTATRA_SR17_Access

#define MWU_PERREGION_SUBSTATRA_SR17_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR17_Msk

#define MWU_PERREGION_SUBSTATRA_SR17_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos)

Bit mask of SR17 field.

◆ MWU_PERREGION_SUBSTATRA_SR17_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR17_Pos

#define MWU_PERREGION_SUBSTATRA_SR17_Pos   (17UL)

Position of SR17 field.

◆ MWU_PERREGION_SUBSTATRA_SR18_Access

#define MWU_PERREGION_SUBSTATRA_SR18_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR18_Msk

#define MWU_PERREGION_SUBSTATRA_SR18_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos)

Bit mask of SR18 field.

◆ MWU_PERREGION_SUBSTATRA_SR18_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR18_Pos

#define MWU_PERREGION_SUBSTATRA_SR18_Pos   (18UL)

Position of SR18 field.

◆ MWU_PERREGION_SUBSTATRA_SR19_Access

#define MWU_PERREGION_SUBSTATRA_SR19_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR19_Msk

#define MWU_PERREGION_SUBSTATRA_SR19_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos)

Bit mask of SR19 field.

◆ MWU_PERREGION_SUBSTATRA_SR19_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR19_Pos

#define MWU_PERREGION_SUBSTATRA_SR19_Pos   (19UL)

Position of SR19 field.

◆ MWU_PERREGION_SUBSTATRA_SR1_Access

#define MWU_PERREGION_SUBSTATRA_SR1_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR1_Msk

#define MWU_PERREGION_SUBSTATRA_SR1_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos)

Bit mask of SR1 field.

◆ MWU_PERREGION_SUBSTATRA_SR1_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR1_Pos

#define MWU_PERREGION_SUBSTATRA_SR1_Pos   (1UL)

Position of SR1 field.

◆ MWU_PERREGION_SUBSTATRA_SR20_Access

#define MWU_PERREGION_SUBSTATRA_SR20_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR20_Msk

#define MWU_PERREGION_SUBSTATRA_SR20_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos)

Bit mask of SR20 field.

◆ MWU_PERREGION_SUBSTATRA_SR20_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR20_Pos

#define MWU_PERREGION_SUBSTATRA_SR20_Pos   (20UL)

Position of SR20 field.

◆ MWU_PERREGION_SUBSTATRA_SR21_Access

#define MWU_PERREGION_SUBSTATRA_SR21_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR21_Msk

#define MWU_PERREGION_SUBSTATRA_SR21_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos)

Bit mask of SR21 field.

◆ MWU_PERREGION_SUBSTATRA_SR21_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR21_Pos

#define MWU_PERREGION_SUBSTATRA_SR21_Pos   (21UL)

Position of SR21 field.

◆ MWU_PERREGION_SUBSTATRA_SR22_Access

#define MWU_PERREGION_SUBSTATRA_SR22_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR22_Msk

#define MWU_PERREGION_SUBSTATRA_SR22_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos)

Bit mask of SR22 field.

◆ MWU_PERREGION_SUBSTATRA_SR22_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR22_Pos

#define MWU_PERREGION_SUBSTATRA_SR22_Pos   (22UL)

Position of SR22 field.

◆ MWU_PERREGION_SUBSTATRA_SR23_Access

#define MWU_PERREGION_SUBSTATRA_SR23_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR23_Msk

#define MWU_PERREGION_SUBSTATRA_SR23_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos)

Bit mask of SR23 field.

◆ MWU_PERREGION_SUBSTATRA_SR23_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR23_Pos

#define MWU_PERREGION_SUBSTATRA_SR23_Pos   (23UL)

Position of SR23 field.

◆ MWU_PERREGION_SUBSTATRA_SR24_Access

#define MWU_PERREGION_SUBSTATRA_SR24_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR24_Msk

#define MWU_PERREGION_SUBSTATRA_SR24_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos)

Bit mask of SR24 field.

◆ MWU_PERREGION_SUBSTATRA_SR24_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR24_Pos

#define MWU_PERREGION_SUBSTATRA_SR24_Pos   (24UL)

Position of SR24 field.

◆ MWU_PERREGION_SUBSTATRA_SR25_Access

#define MWU_PERREGION_SUBSTATRA_SR25_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR25_Msk

#define MWU_PERREGION_SUBSTATRA_SR25_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos)

Bit mask of SR25 field.

◆ MWU_PERREGION_SUBSTATRA_SR25_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR25_Pos

#define MWU_PERREGION_SUBSTATRA_SR25_Pos   (25UL)

Position of SR25 field.

◆ MWU_PERREGION_SUBSTATRA_SR26_Access

#define MWU_PERREGION_SUBSTATRA_SR26_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR26_Msk

#define MWU_PERREGION_SUBSTATRA_SR26_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos)

Bit mask of SR26 field.

◆ MWU_PERREGION_SUBSTATRA_SR26_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR26_Pos

#define MWU_PERREGION_SUBSTATRA_SR26_Pos   (26UL)

Position of SR26 field.

◆ MWU_PERREGION_SUBSTATRA_SR27_Access

#define MWU_PERREGION_SUBSTATRA_SR27_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR27_Msk

#define MWU_PERREGION_SUBSTATRA_SR27_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos)

Bit mask of SR27 field.

◆ MWU_PERREGION_SUBSTATRA_SR27_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR27_Pos

#define MWU_PERREGION_SUBSTATRA_SR27_Pos   (27UL)

Position of SR27 field.

◆ MWU_PERREGION_SUBSTATRA_SR28_Access

#define MWU_PERREGION_SUBSTATRA_SR28_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR28_Msk

#define MWU_PERREGION_SUBSTATRA_SR28_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos)

Bit mask of SR28 field.

◆ MWU_PERREGION_SUBSTATRA_SR28_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR28_Pos

#define MWU_PERREGION_SUBSTATRA_SR28_Pos   (28UL)

Position of SR28 field.

◆ MWU_PERREGION_SUBSTATRA_SR29_Access

#define MWU_PERREGION_SUBSTATRA_SR29_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR29_Msk

#define MWU_PERREGION_SUBSTATRA_SR29_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos)

Bit mask of SR29 field.

◆ MWU_PERREGION_SUBSTATRA_SR29_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR29_Pos

#define MWU_PERREGION_SUBSTATRA_SR29_Pos   (29UL)

Position of SR29 field.

◆ MWU_PERREGION_SUBSTATRA_SR2_Access

#define MWU_PERREGION_SUBSTATRA_SR2_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR2_Msk

#define MWU_PERREGION_SUBSTATRA_SR2_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos)

Bit mask of SR2 field.

◆ MWU_PERREGION_SUBSTATRA_SR2_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR2_Pos

#define MWU_PERREGION_SUBSTATRA_SR2_Pos   (2UL)

Position of SR2 field.

◆ MWU_PERREGION_SUBSTATRA_SR30_Access

#define MWU_PERREGION_SUBSTATRA_SR30_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR30_Msk

#define MWU_PERREGION_SUBSTATRA_SR30_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos)

Bit mask of SR30 field.

◆ MWU_PERREGION_SUBSTATRA_SR30_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR30_Pos

#define MWU_PERREGION_SUBSTATRA_SR30_Pos   (30UL)

Position of SR30 field.

◆ MWU_PERREGION_SUBSTATRA_SR31_Access

#define MWU_PERREGION_SUBSTATRA_SR31_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR31_Msk

#define MWU_PERREGION_SUBSTATRA_SR31_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos)

Bit mask of SR31 field.

◆ MWU_PERREGION_SUBSTATRA_SR31_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR31_Pos

#define MWU_PERREGION_SUBSTATRA_SR31_Pos   (31UL)

Position of SR31 field.

◆ MWU_PERREGION_SUBSTATRA_SR3_Access

#define MWU_PERREGION_SUBSTATRA_SR3_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR3_Msk

#define MWU_PERREGION_SUBSTATRA_SR3_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos)

Bit mask of SR3 field.

◆ MWU_PERREGION_SUBSTATRA_SR3_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR3_Pos

#define MWU_PERREGION_SUBSTATRA_SR3_Pos   (3UL)

Position of SR3 field.

◆ MWU_PERREGION_SUBSTATRA_SR4_Access

#define MWU_PERREGION_SUBSTATRA_SR4_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR4_Msk

#define MWU_PERREGION_SUBSTATRA_SR4_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos)

Bit mask of SR4 field.

◆ MWU_PERREGION_SUBSTATRA_SR4_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR4_Pos

#define MWU_PERREGION_SUBSTATRA_SR4_Pos   (4UL)

Position of SR4 field.

◆ MWU_PERREGION_SUBSTATRA_SR5_Access

#define MWU_PERREGION_SUBSTATRA_SR5_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR5_Msk

#define MWU_PERREGION_SUBSTATRA_SR5_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos)

Bit mask of SR5 field.

◆ MWU_PERREGION_SUBSTATRA_SR5_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR5_Pos

#define MWU_PERREGION_SUBSTATRA_SR5_Pos   (5UL)

Position of SR5 field.

◆ MWU_PERREGION_SUBSTATRA_SR6_Access

#define MWU_PERREGION_SUBSTATRA_SR6_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR6_Msk

#define MWU_PERREGION_SUBSTATRA_SR6_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos)

Bit mask of SR6 field.

◆ MWU_PERREGION_SUBSTATRA_SR6_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR6_Pos

#define MWU_PERREGION_SUBSTATRA_SR6_Pos   (6UL)

Position of SR6 field.

◆ MWU_PERREGION_SUBSTATRA_SR7_Access

#define MWU_PERREGION_SUBSTATRA_SR7_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR7_Msk

#define MWU_PERREGION_SUBSTATRA_SR7_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos)

Bit mask of SR7 field.

◆ MWU_PERREGION_SUBSTATRA_SR7_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR7_Pos

#define MWU_PERREGION_SUBSTATRA_SR7_Pos   (7UL)

Position of SR7 field.

◆ MWU_PERREGION_SUBSTATRA_SR8_Access

#define MWU_PERREGION_SUBSTATRA_SR8_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR8_Msk

#define MWU_PERREGION_SUBSTATRA_SR8_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos)

Bit mask of SR8 field.

◆ MWU_PERREGION_SUBSTATRA_SR8_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR8_Pos

#define MWU_PERREGION_SUBSTATRA_SR8_Pos   (8UL)

Position of SR8 field.

◆ MWU_PERREGION_SUBSTATRA_SR9_Access

#define MWU_PERREGION_SUBSTATRA_SR9_Access   (1UL)

Read access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR9_Msk

#define MWU_PERREGION_SUBSTATRA_SR9_Msk   (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos)

Bit mask of SR9 field.

◆ MWU_PERREGION_SUBSTATRA_SR9_NoAccess

#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess   (0UL)

No read access occurred in this subregion

◆ MWU_PERREGION_SUBSTATRA_SR9_Pos

#define MWU_PERREGION_SUBSTATRA_SR9_Pos   (9UL)

Position of SR9 field.

◆ MWU_PERREGION_SUBSTATWA_SR0_Access

#define MWU_PERREGION_SUBSTATWA_SR0_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR0_Msk

#define MWU_PERREGION_SUBSTATWA_SR0_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos)

Bit mask of SR0 field.

◆ MWU_PERREGION_SUBSTATWA_SR0_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR0_Pos

#define MWU_PERREGION_SUBSTATWA_SR0_Pos   (0UL)

Position of SR0 field.

◆ MWU_PERREGION_SUBSTATWA_SR10_Access

#define MWU_PERREGION_SUBSTATWA_SR10_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR10_Msk

#define MWU_PERREGION_SUBSTATWA_SR10_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos)

Bit mask of SR10 field.

◆ MWU_PERREGION_SUBSTATWA_SR10_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR10_Pos

#define MWU_PERREGION_SUBSTATWA_SR10_Pos   (10UL)

Position of SR10 field.

◆ MWU_PERREGION_SUBSTATWA_SR11_Access

#define MWU_PERREGION_SUBSTATWA_SR11_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR11_Msk

#define MWU_PERREGION_SUBSTATWA_SR11_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos)

Bit mask of SR11 field.

◆ MWU_PERREGION_SUBSTATWA_SR11_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR11_Pos

#define MWU_PERREGION_SUBSTATWA_SR11_Pos   (11UL)

Position of SR11 field.

◆ MWU_PERREGION_SUBSTATWA_SR12_Access

#define MWU_PERREGION_SUBSTATWA_SR12_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR12_Msk

#define MWU_PERREGION_SUBSTATWA_SR12_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos)

Bit mask of SR12 field.

◆ MWU_PERREGION_SUBSTATWA_SR12_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR12_Pos

#define MWU_PERREGION_SUBSTATWA_SR12_Pos   (12UL)

Position of SR12 field.

◆ MWU_PERREGION_SUBSTATWA_SR13_Access

#define MWU_PERREGION_SUBSTATWA_SR13_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR13_Msk

#define MWU_PERREGION_SUBSTATWA_SR13_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos)

Bit mask of SR13 field.

◆ MWU_PERREGION_SUBSTATWA_SR13_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR13_Pos

#define MWU_PERREGION_SUBSTATWA_SR13_Pos   (13UL)

Position of SR13 field.

◆ MWU_PERREGION_SUBSTATWA_SR14_Access

#define MWU_PERREGION_SUBSTATWA_SR14_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR14_Msk

#define MWU_PERREGION_SUBSTATWA_SR14_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos)

Bit mask of SR14 field.

◆ MWU_PERREGION_SUBSTATWA_SR14_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR14_Pos

#define MWU_PERREGION_SUBSTATWA_SR14_Pos   (14UL)

Position of SR14 field.

◆ MWU_PERREGION_SUBSTATWA_SR15_Access

#define MWU_PERREGION_SUBSTATWA_SR15_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR15_Msk

#define MWU_PERREGION_SUBSTATWA_SR15_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos)

Bit mask of SR15 field.

◆ MWU_PERREGION_SUBSTATWA_SR15_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR15_Pos

#define MWU_PERREGION_SUBSTATWA_SR15_Pos   (15UL)

Position of SR15 field.

◆ MWU_PERREGION_SUBSTATWA_SR16_Access

#define MWU_PERREGION_SUBSTATWA_SR16_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR16_Msk

#define MWU_PERREGION_SUBSTATWA_SR16_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos)

Bit mask of SR16 field.

◆ MWU_PERREGION_SUBSTATWA_SR16_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR16_Pos

#define MWU_PERREGION_SUBSTATWA_SR16_Pos   (16UL)

Position of SR16 field.

◆ MWU_PERREGION_SUBSTATWA_SR17_Access

#define MWU_PERREGION_SUBSTATWA_SR17_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR17_Msk

#define MWU_PERREGION_SUBSTATWA_SR17_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos)

Bit mask of SR17 field.

◆ MWU_PERREGION_SUBSTATWA_SR17_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR17_Pos

#define MWU_PERREGION_SUBSTATWA_SR17_Pos   (17UL)

Position of SR17 field.

◆ MWU_PERREGION_SUBSTATWA_SR18_Access

#define MWU_PERREGION_SUBSTATWA_SR18_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR18_Msk

#define MWU_PERREGION_SUBSTATWA_SR18_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos)

Bit mask of SR18 field.

◆ MWU_PERREGION_SUBSTATWA_SR18_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR18_Pos

#define MWU_PERREGION_SUBSTATWA_SR18_Pos   (18UL)

Position of SR18 field.

◆ MWU_PERREGION_SUBSTATWA_SR19_Access

#define MWU_PERREGION_SUBSTATWA_SR19_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR19_Msk

#define MWU_PERREGION_SUBSTATWA_SR19_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos)

Bit mask of SR19 field.

◆ MWU_PERREGION_SUBSTATWA_SR19_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR19_Pos

#define MWU_PERREGION_SUBSTATWA_SR19_Pos   (19UL)

Position of SR19 field.

◆ MWU_PERREGION_SUBSTATWA_SR1_Access

#define MWU_PERREGION_SUBSTATWA_SR1_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR1_Msk

#define MWU_PERREGION_SUBSTATWA_SR1_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos)

Bit mask of SR1 field.

◆ MWU_PERREGION_SUBSTATWA_SR1_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR1_Pos

#define MWU_PERREGION_SUBSTATWA_SR1_Pos   (1UL)

Position of SR1 field.

◆ MWU_PERREGION_SUBSTATWA_SR20_Access

#define MWU_PERREGION_SUBSTATWA_SR20_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR20_Msk

#define MWU_PERREGION_SUBSTATWA_SR20_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos)

Bit mask of SR20 field.

◆ MWU_PERREGION_SUBSTATWA_SR20_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR20_Pos

#define MWU_PERREGION_SUBSTATWA_SR20_Pos   (20UL)

Position of SR20 field.

◆ MWU_PERREGION_SUBSTATWA_SR21_Access

#define MWU_PERREGION_SUBSTATWA_SR21_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR21_Msk

#define MWU_PERREGION_SUBSTATWA_SR21_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos)

Bit mask of SR21 field.

◆ MWU_PERREGION_SUBSTATWA_SR21_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR21_Pos

#define MWU_PERREGION_SUBSTATWA_SR21_Pos   (21UL)

Position of SR21 field.

◆ MWU_PERREGION_SUBSTATWA_SR22_Access

#define MWU_PERREGION_SUBSTATWA_SR22_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR22_Msk

#define MWU_PERREGION_SUBSTATWA_SR22_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos)

Bit mask of SR22 field.

◆ MWU_PERREGION_SUBSTATWA_SR22_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR22_Pos

#define MWU_PERREGION_SUBSTATWA_SR22_Pos   (22UL)

Position of SR22 field.

◆ MWU_PERREGION_SUBSTATWA_SR23_Access

#define MWU_PERREGION_SUBSTATWA_SR23_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR23_Msk

#define MWU_PERREGION_SUBSTATWA_SR23_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos)

Bit mask of SR23 field.

◆ MWU_PERREGION_SUBSTATWA_SR23_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR23_Pos

#define MWU_PERREGION_SUBSTATWA_SR23_Pos   (23UL)

Position of SR23 field.

◆ MWU_PERREGION_SUBSTATWA_SR24_Access

#define MWU_PERREGION_SUBSTATWA_SR24_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR24_Msk

#define MWU_PERREGION_SUBSTATWA_SR24_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos)

Bit mask of SR24 field.

◆ MWU_PERREGION_SUBSTATWA_SR24_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR24_Pos

#define MWU_PERREGION_SUBSTATWA_SR24_Pos   (24UL)

Position of SR24 field.

◆ MWU_PERREGION_SUBSTATWA_SR25_Access

#define MWU_PERREGION_SUBSTATWA_SR25_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR25_Msk

#define MWU_PERREGION_SUBSTATWA_SR25_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos)

Bit mask of SR25 field.

◆ MWU_PERREGION_SUBSTATWA_SR25_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR25_Pos

#define MWU_PERREGION_SUBSTATWA_SR25_Pos   (25UL)

Position of SR25 field.

◆ MWU_PERREGION_SUBSTATWA_SR26_Access

#define MWU_PERREGION_SUBSTATWA_SR26_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR26_Msk

#define MWU_PERREGION_SUBSTATWA_SR26_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos)

Bit mask of SR26 field.

◆ MWU_PERREGION_SUBSTATWA_SR26_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR26_Pos

#define MWU_PERREGION_SUBSTATWA_SR26_Pos   (26UL)

Position of SR26 field.

◆ MWU_PERREGION_SUBSTATWA_SR27_Access

#define MWU_PERREGION_SUBSTATWA_SR27_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR27_Msk

#define MWU_PERREGION_SUBSTATWA_SR27_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos)

Bit mask of SR27 field.

◆ MWU_PERREGION_SUBSTATWA_SR27_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR27_Pos

#define MWU_PERREGION_SUBSTATWA_SR27_Pos   (27UL)

Position of SR27 field.

◆ MWU_PERREGION_SUBSTATWA_SR28_Access

#define MWU_PERREGION_SUBSTATWA_SR28_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR28_Msk

#define MWU_PERREGION_SUBSTATWA_SR28_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos)

Bit mask of SR28 field.

◆ MWU_PERREGION_SUBSTATWA_SR28_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR28_Pos

#define MWU_PERREGION_SUBSTATWA_SR28_Pos   (28UL)

Position of SR28 field.

◆ MWU_PERREGION_SUBSTATWA_SR29_Access

#define MWU_PERREGION_SUBSTATWA_SR29_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR29_Msk

#define MWU_PERREGION_SUBSTATWA_SR29_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos)

Bit mask of SR29 field.

◆ MWU_PERREGION_SUBSTATWA_SR29_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR29_Pos

#define MWU_PERREGION_SUBSTATWA_SR29_Pos   (29UL)

Position of SR29 field.

◆ MWU_PERREGION_SUBSTATWA_SR2_Access

#define MWU_PERREGION_SUBSTATWA_SR2_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR2_Msk

#define MWU_PERREGION_SUBSTATWA_SR2_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos)

Bit mask of SR2 field.

◆ MWU_PERREGION_SUBSTATWA_SR2_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR2_Pos

#define MWU_PERREGION_SUBSTATWA_SR2_Pos   (2UL)

Position of SR2 field.

◆ MWU_PERREGION_SUBSTATWA_SR30_Access

#define MWU_PERREGION_SUBSTATWA_SR30_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR30_Msk

#define MWU_PERREGION_SUBSTATWA_SR30_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos)

Bit mask of SR30 field.

◆ MWU_PERREGION_SUBSTATWA_SR30_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR30_Pos

#define MWU_PERREGION_SUBSTATWA_SR30_Pos   (30UL)

Position of SR30 field.

◆ MWU_PERREGION_SUBSTATWA_SR31_Access

#define MWU_PERREGION_SUBSTATWA_SR31_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR31_Msk

#define MWU_PERREGION_SUBSTATWA_SR31_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos)

Bit mask of SR31 field.

◆ MWU_PERREGION_SUBSTATWA_SR31_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR31_Pos

#define MWU_PERREGION_SUBSTATWA_SR31_Pos   (31UL)

Position of SR31 field.

◆ MWU_PERREGION_SUBSTATWA_SR3_Access

#define MWU_PERREGION_SUBSTATWA_SR3_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR3_Msk

#define MWU_PERREGION_SUBSTATWA_SR3_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos)

Bit mask of SR3 field.

◆ MWU_PERREGION_SUBSTATWA_SR3_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR3_Pos

#define MWU_PERREGION_SUBSTATWA_SR3_Pos   (3UL)

Position of SR3 field.

◆ MWU_PERREGION_SUBSTATWA_SR4_Access

#define MWU_PERREGION_SUBSTATWA_SR4_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR4_Msk

#define MWU_PERREGION_SUBSTATWA_SR4_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos)

Bit mask of SR4 field.

◆ MWU_PERREGION_SUBSTATWA_SR4_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR4_Pos

#define MWU_PERREGION_SUBSTATWA_SR4_Pos   (4UL)

Position of SR4 field.

◆ MWU_PERREGION_SUBSTATWA_SR5_Access

#define MWU_PERREGION_SUBSTATWA_SR5_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR5_Msk

#define MWU_PERREGION_SUBSTATWA_SR5_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos)

Bit mask of SR5 field.

◆ MWU_PERREGION_SUBSTATWA_SR5_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR5_Pos

#define MWU_PERREGION_SUBSTATWA_SR5_Pos   (5UL)

Position of SR5 field.

◆ MWU_PERREGION_SUBSTATWA_SR6_Access

#define MWU_PERREGION_SUBSTATWA_SR6_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR6_Msk

#define MWU_PERREGION_SUBSTATWA_SR6_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos)

Bit mask of SR6 field.

◆ MWU_PERREGION_SUBSTATWA_SR6_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR6_Pos

#define MWU_PERREGION_SUBSTATWA_SR6_Pos   (6UL)

Position of SR6 field.

◆ MWU_PERREGION_SUBSTATWA_SR7_Access

#define MWU_PERREGION_SUBSTATWA_SR7_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR7_Msk

#define MWU_PERREGION_SUBSTATWA_SR7_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos)

Bit mask of SR7 field.

◆ MWU_PERREGION_SUBSTATWA_SR7_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR7_Pos

#define MWU_PERREGION_SUBSTATWA_SR7_Pos   (7UL)

Position of SR7 field.

◆ MWU_PERREGION_SUBSTATWA_SR8_Access

#define MWU_PERREGION_SUBSTATWA_SR8_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR8_Msk

#define MWU_PERREGION_SUBSTATWA_SR8_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos)

Bit mask of SR8 field.

◆ MWU_PERREGION_SUBSTATWA_SR8_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR8_Pos

#define MWU_PERREGION_SUBSTATWA_SR8_Pos   (8UL)

Position of SR8 field.

◆ MWU_PERREGION_SUBSTATWA_SR9_Access

#define MWU_PERREGION_SUBSTATWA_SR9_Access   (1UL)

Write access(es) occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR9_Msk

#define MWU_PERREGION_SUBSTATWA_SR9_Msk   (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos)

Bit mask of SR9 field.

◆ MWU_PERREGION_SUBSTATWA_SR9_NoAccess

#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess   (0UL)

No write access occurred in this subregion

◆ MWU_PERREGION_SUBSTATWA_SR9_Pos

#define MWU_PERREGION_SUBSTATWA_SR9_Pos   (9UL)

Position of SR9 field.

◆ MWU_PREGION_END_END_Msk

#define MWU_PREGION_END_END_Msk   (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos)

Bit mask of END field.

◆ MWU_PREGION_END_END_Pos

#define MWU_PREGION_END_END_Pos   (0UL)

Position of END field.

◆ MWU_PREGION_START_START_Msk

#define MWU_PREGION_START_START_Msk   (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos)

Bit mask of START field.

◆ MWU_PREGION_START_START_Pos

#define MWU_PREGION_START_START_Pos   (0UL)

Position of START field.

◆ MWU_PREGION_SUBS_SR0_Exclude

#define MWU_PREGION_SUBS_SR0_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR0_Include

#define MWU_PREGION_SUBS_SR0_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR0_Msk

#define MWU_PREGION_SUBS_SR0_Msk   (0x1UL << MWU_PREGION_SUBS_SR0_Pos)

Bit mask of SR0 field.

◆ MWU_PREGION_SUBS_SR0_Pos

#define MWU_PREGION_SUBS_SR0_Pos   (0UL)

Position of SR0 field.

◆ MWU_PREGION_SUBS_SR10_Exclude

#define MWU_PREGION_SUBS_SR10_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR10_Include

#define MWU_PREGION_SUBS_SR10_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR10_Msk

#define MWU_PREGION_SUBS_SR10_Msk   (0x1UL << MWU_PREGION_SUBS_SR10_Pos)

Bit mask of SR10 field.

◆ MWU_PREGION_SUBS_SR10_Pos

#define MWU_PREGION_SUBS_SR10_Pos   (10UL)

Position of SR10 field.

◆ MWU_PREGION_SUBS_SR11_Exclude

#define MWU_PREGION_SUBS_SR11_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR11_Include

#define MWU_PREGION_SUBS_SR11_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR11_Msk

#define MWU_PREGION_SUBS_SR11_Msk   (0x1UL << MWU_PREGION_SUBS_SR11_Pos)

Bit mask of SR11 field.

◆ MWU_PREGION_SUBS_SR11_Pos

#define MWU_PREGION_SUBS_SR11_Pos   (11UL)

Position of SR11 field.

◆ MWU_PREGION_SUBS_SR12_Exclude

#define MWU_PREGION_SUBS_SR12_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR12_Include

#define MWU_PREGION_SUBS_SR12_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR12_Msk

#define MWU_PREGION_SUBS_SR12_Msk   (0x1UL << MWU_PREGION_SUBS_SR12_Pos)

Bit mask of SR12 field.

◆ MWU_PREGION_SUBS_SR12_Pos

#define MWU_PREGION_SUBS_SR12_Pos   (12UL)

Position of SR12 field.

◆ MWU_PREGION_SUBS_SR13_Exclude

#define MWU_PREGION_SUBS_SR13_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR13_Include

#define MWU_PREGION_SUBS_SR13_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR13_Msk

#define MWU_PREGION_SUBS_SR13_Msk   (0x1UL << MWU_PREGION_SUBS_SR13_Pos)

Bit mask of SR13 field.

◆ MWU_PREGION_SUBS_SR13_Pos

#define MWU_PREGION_SUBS_SR13_Pos   (13UL)

Position of SR13 field.

◆ MWU_PREGION_SUBS_SR14_Exclude

#define MWU_PREGION_SUBS_SR14_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR14_Include

#define MWU_PREGION_SUBS_SR14_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR14_Msk

#define MWU_PREGION_SUBS_SR14_Msk   (0x1UL << MWU_PREGION_SUBS_SR14_Pos)

Bit mask of SR14 field.

◆ MWU_PREGION_SUBS_SR14_Pos

#define MWU_PREGION_SUBS_SR14_Pos   (14UL)

Position of SR14 field.

◆ MWU_PREGION_SUBS_SR15_Exclude

#define MWU_PREGION_SUBS_SR15_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR15_Include

#define MWU_PREGION_SUBS_SR15_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR15_Msk

#define MWU_PREGION_SUBS_SR15_Msk   (0x1UL << MWU_PREGION_SUBS_SR15_Pos)

Bit mask of SR15 field.

◆ MWU_PREGION_SUBS_SR15_Pos

#define MWU_PREGION_SUBS_SR15_Pos   (15UL)

Position of SR15 field.

◆ MWU_PREGION_SUBS_SR16_Exclude

#define MWU_PREGION_SUBS_SR16_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR16_Include

#define MWU_PREGION_SUBS_SR16_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR16_Msk

#define MWU_PREGION_SUBS_SR16_Msk   (0x1UL << MWU_PREGION_SUBS_SR16_Pos)

Bit mask of SR16 field.

◆ MWU_PREGION_SUBS_SR16_Pos

#define MWU_PREGION_SUBS_SR16_Pos   (16UL)

Position of SR16 field.

◆ MWU_PREGION_SUBS_SR17_Exclude

#define MWU_PREGION_SUBS_SR17_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR17_Include

#define MWU_PREGION_SUBS_SR17_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR17_Msk

#define MWU_PREGION_SUBS_SR17_Msk   (0x1UL << MWU_PREGION_SUBS_SR17_Pos)

Bit mask of SR17 field.

◆ MWU_PREGION_SUBS_SR17_Pos

#define MWU_PREGION_SUBS_SR17_Pos   (17UL)

Position of SR17 field.

◆ MWU_PREGION_SUBS_SR18_Exclude

#define MWU_PREGION_SUBS_SR18_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR18_Include

#define MWU_PREGION_SUBS_SR18_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR18_Msk

#define MWU_PREGION_SUBS_SR18_Msk   (0x1UL << MWU_PREGION_SUBS_SR18_Pos)

Bit mask of SR18 field.

◆ MWU_PREGION_SUBS_SR18_Pos

#define MWU_PREGION_SUBS_SR18_Pos   (18UL)

Position of SR18 field.

◆ MWU_PREGION_SUBS_SR19_Exclude

#define MWU_PREGION_SUBS_SR19_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR19_Include

#define MWU_PREGION_SUBS_SR19_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR19_Msk

#define MWU_PREGION_SUBS_SR19_Msk   (0x1UL << MWU_PREGION_SUBS_SR19_Pos)

Bit mask of SR19 field.

◆ MWU_PREGION_SUBS_SR19_Pos

#define MWU_PREGION_SUBS_SR19_Pos   (19UL)

Position of SR19 field.

◆ MWU_PREGION_SUBS_SR1_Exclude

#define MWU_PREGION_SUBS_SR1_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR1_Include

#define MWU_PREGION_SUBS_SR1_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR1_Msk

#define MWU_PREGION_SUBS_SR1_Msk   (0x1UL << MWU_PREGION_SUBS_SR1_Pos)

Bit mask of SR1 field.

◆ MWU_PREGION_SUBS_SR1_Pos

#define MWU_PREGION_SUBS_SR1_Pos   (1UL)

Position of SR1 field.

◆ MWU_PREGION_SUBS_SR20_Exclude

#define MWU_PREGION_SUBS_SR20_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR20_Include

#define MWU_PREGION_SUBS_SR20_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR20_Msk

#define MWU_PREGION_SUBS_SR20_Msk   (0x1UL << MWU_PREGION_SUBS_SR20_Pos)

Bit mask of SR20 field.

◆ MWU_PREGION_SUBS_SR20_Pos

#define MWU_PREGION_SUBS_SR20_Pos   (20UL)

Position of SR20 field.

◆ MWU_PREGION_SUBS_SR21_Exclude

#define MWU_PREGION_SUBS_SR21_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR21_Include

#define MWU_PREGION_SUBS_SR21_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR21_Msk

#define MWU_PREGION_SUBS_SR21_Msk   (0x1UL << MWU_PREGION_SUBS_SR21_Pos)

Bit mask of SR21 field.

◆ MWU_PREGION_SUBS_SR21_Pos

#define MWU_PREGION_SUBS_SR21_Pos   (21UL)

Position of SR21 field.

◆ MWU_PREGION_SUBS_SR22_Exclude

#define MWU_PREGION_SUBS_SR22_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR22_Include

#define MWU_PREGION_SUBS_SR22_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR22_Msk

#define MWU_PREGION_SUBS_SR22_Msk   (0x1UL << MWU_PREGION_SUBS_SR22_Pos)

Bit mask of SR22 field.

◆ MWU_PREGION_SUBS_SR22_Pos

#define MWU_PREGION_SUBS_SR22_Pos   (22UL)

Position of SR22 field.

◆ MWU_PREGION_SUBS_SR23_Exclude

#define MWU_PREGION_SUBS_SR23_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR23_Include

#define MWU_PREGION_SUBS_SR23_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR23_Msk

#define MWU_PREGION_SUBS_SR23_Msk   (0x1UL << MWU_PREGION_SUBS_SR23_Pos)

Bit mask of SR23 field.

◆ MWU_PREGION_SUBS_SR23_Pos

#define MWU_PREGION_SUBS_SR23_Pos   (23UL)

Position of SR23 field.

◆ MWU_PREGION_SUBS_SR24_Exclude

#define MWU_PREGION_SUBS_SR24_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR24_Include

#define MWU_PREGION_SUBS_SR24_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR24_Msk

#define MWU_PREGION_SUBS_SR24_Msk   (0x1UL << MWU_PREGION_SUBS_SR24_Pos)

Bit mask of SR24 field.

◆ MWU_PREGION_SUBS_SR24_Pos

#define MWU_PREGION_SUBS_SR24_Pos   (24UL)

Position of SR24 field.

◆ MWU_PREGION_SUBS_SR25_Exclude

#define MWU_PREGION_SUBS_SR25_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR25_Include

#define MWU_PREGION_SUBS_SR25_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR25_Msk

#define MWU_PREGION_SUBS_SR25_Msk   (0x1UL << MWU_PREGION_SUBS_SR25_Pos)

Bit mask of SR25 field.

◆ MWU_PREGION_SUBS_SR25_Pos

#define MWU_PREGION_SUBS_SR25_Pos   (25UL)

Position of SR25 field.

◆ MWU_PREGION_SUBS_SR26_Exclude

#define MWU_PREGION_SUBS_SR26_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR26_Include

#define MWU_PREGION_SUBS_SR26_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR26_Msk

#define MWU_PREGION_SUBS_SR26_Msk   (0x1UL << MWU_PREGION_SUBS_SR26_Pos)

Bit mask of SR26 field.

◆ MWU_PREGION_SUBS_SR26_Pos

#define MWU_PREGION_SUBS_SR26_Pos   (26UL)

Position of SR26 field.

◆ MWU_PREGION_SUBS_SR27_Exclude

#define MWU_PREGION_SUBS_SR27_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR27_Include

#define MWU_PREGION_SUBS_SR27_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR27_Msk

#define MWU_PREGION_SUBS_SR27_Msk   (0x1UL << MWU_PREGION_SUBS_SR27_Pos)

Bit mask of SR27 field.

◆ MWU_PREGION_SUBS_SR27_Pos

#define MWU_PREGION_SUBS_SR27_Pos   (27UL)

Position of SR27 field.

◆ MWU_PREGION_SUBS_SR28_Exclude

#define MWU_PREGION_SUBS_SR28_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR28_Include

#define MWU_PREGION_SUBS_SR28_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR28_Msk

#define MWU_PREGION_SUBS_SR28_Msk   (0x1UL << MWU_PREGION_SUBS_SR28_Pos)

Bit mask of SR28 field.

◆ MWU_PREGION_SUBS_SR28_Pos

#define MWU_PREGION_SUBS_SR28_Pos   (28UL)

Position of SR28 field.

◆ MWU_PREGION_SUBS_SR29_Exclude

#define MWU_PREGION_SUBS_SR29_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR29_Include

#define MWU_PREGION_SUBS_SR29_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR29_Msk

#define MWU_PREGION_SUBS_SR29_Msk   (0x1UL << MWU_PREGION_SUBS_SR29_Pos)

Bit mask of SR29 field.

◆ MWU_PREGION_SUBS_SR29_Pos

#define MWU_PREGION_SUBS_SR29_Pos   (29UL)

Position of SR29 field.

◆ MWU_PREGION_SUBS_SR2_Exclude

#define MWU_PREGION_SUBS_SR2_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR2_Include

#define MWU_PREGION_SUBS_SR2_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR2_Msk

#define MWU_PREGION_SUBS_SR2_Msk   (0x1UL << MWU_PREGION_SUBS_SR2_Pos)

Bit mask of SR2 field.

◆ MWU_PREGION_SUBS_SR2_Pos

#define MWU_PREGION_SUBS_SR2_Pos   (2UL)

Position of SR2 field.

◆ MWU_PREGION_SUBS_SR30_Exclude

#define MWU_PREGION_SUBS_SR30_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR30_Include

#define MWU_PREGION_SUBS_SR30_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR30_Msk

#define MWU_PREGION_SUBS_SR30_Msk   (0x1UL << MWU_PREGION_SUBS_SR30_Pos)

Bit mask of SR30 field.

◆ MWU_PREGION_SUBS_SR30_Pos

#define MWU_PREGION_SUBS_SR30_Pos   (30UL)

Position of SR30 field.

◆ MWU_PREGION_SUBS_SR31_Exclude

#define MWU_PREGION_SUBS_SR31_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR31_Include

#define MWU_PREGION_SUBS_SR31_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR31_Msk

#define MWU_PREGION_SUBS_SR31_Msk   (0x1UL << MWU_PREGION_SUBS_SR31_Pos)

Bit mask of SR31 field.

◆ MWU_PREGION_SUBS_SR31_Pos

#define MWU_PREGION_SUBS_SR31_Pos   (31UL)

Position of SR31 field.

◆ MWU_PREGION_SUBS_SR3_Exclude

#define MWU_PREGION_SUBS_SR3_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR3_Include

#define MWU_PREGION_SUBS_SR3_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR3_Msk

#define MWU_PREGION_SUBS_SR3_Msk   (0x1UL << MWU_PREGION_SUBS_SR3_Pos)

Bit mask of SR3 field.

◆ MWU_PREGION_SUBS_SR3_Pos

#define MWU_PREGION_SUBS_SR3_Pos   (3UL)

Position of SR3 field.

◆ MWU_PREGION_SUBS_SR4_Exclude

#define MWU_PREGION_SUBS_SR4_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR4_Include

#define MWU_PREGION_SUBS_SR4_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR4_Msk

#define MWU_PREGION_SUBS_SR4_Msk   (0x1UL << MWU_PREGION_SUBS_SR4_Pos)

Bit mask of SR4 field.

◆ MWU_PREGION_SUBS_SR4_Pos

#define MWU_PREGION_SUBS_SR4_Pos   (4UL)

Position of SR4 field.

◆ MWU_PREGION_SUBS_SR5_Exclude

#define MWU_PREGION_SUBS_SR5_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR5_Include

#define MWU_PREGION_SUBS_SR5_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR5_Msk

#define MWU_PREGION_SUBS_SR5_Msk   (0x1UL << MWU_PREGION_SUBS_SR5_Pos)

Bit mask of SR5 field.

◆ MWU_PREGION_SUBS_SR5_Pos

#define MWU_PREGION_SUBS_SR5_Pos   (5UL)

Position of SR5 field.

◆ MWU_PREGION_SUBS_SR6_Exclude

#define MWU_PREGION_SUBS_SR6_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR6_Include

#define MWU_PREGION_SUBS_SR6_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR6_Msk

#define MWU_PREGION_SUBS_SR6_Msk   (0x1UL << MWU_PREGION_SUBS_SR6_Pos)

Bit mask of SR6 field.

◆ MWU_PREGION_SUBS_SR6_Pos

#define MWU_PREGION_SUBS_SR6_Pos   (6UL)

Position of SR6 field.

◆ MWU_PREGION_SUBS_SR7_Exclude

#define MWU_PREGION_SUBS_SR7_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR7_Include

#define MWU_PREGION_SUBS_SR7_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR7_Msk

#define MWU_PREGION_SUBS_SR7_Msk   (0x1UL << MWU_PREGION_SUBS_SR7_Pos)

Bit mask of SR7 field.

◆ MWU_PREGION_SUBS_SR7_Pos

#define MWU_PREGION_SUBS_SR7_Pos   (7UL)

Position of SR7 field.

◆ MWU_PREGION_SUBS_SR8_Exclude

#define MWU_PREGION_SUBS_SR8_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR8_Include

#define MWU_PREGION_SUBS_SR8_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR8_Msk

#define MWU_PREGION_SUBS_SR8_Msk   (0x1UL << MWU_PREGION_SUBS_SR8_Pos)

Bit mask of SR8 field.

◆ MWU_PREGION_SUBS_SR8_Pos

#define MWU_PREGION_SUBS_SR8_Pos   (8UL)

Position of SR8 field.

◆ MWU_PREGION_SUBS_SR9_Exclude

#define MWU_PREGION_SUBS_SR9_Exclude   (0UL)

Exclude

◆ MWU_PREGION_SUBS_SR9_Include

#define MWU_PREGION_SUBS_SR9_Include   (1UL)

Include

◆ MWU_PREGION_SUBS_SR9_Msk

#define MWU_PREGION_SUBS_SR9_Msk   (0x1UL << MWU_PREGION_SUBS_SR9_Pos)

Bit mask of SR9 field.

◆ MWU_PREGION_SUBS_SR9_Pos

#define MWU_PREGION_SUBS_SR9_Pos   (9UL)

Position of SR9 field.

◆ MWU_REGION_END_END_Msk

#define MWU_REGION_END_END_Msk   (0xFFFFFFFFUL << MWU_REGION_END_END_Pos)

Bit mask of END field.

◆ MWU_REGION_END_END_Pos

#define MWU_REGION_END_END_Pos   (0UL)

Position of END field.

◆ MWU_REGION_START_START_Msk

#define MWU_REGION_START_START_Msk   (0xFFFFFFFFUL << MWU_REGION_START_START_Pos)

Bit mask of START field.

◆ MWU_REGION_START_START_Pos

#define MWU_REGION_START_START_Pos   (0UL)

Position of START field.

◆ MWU_REGIONEN_PRGN0RA_Disable

#define MWU_REGIONEN_PRGN0RA_Disable   (0UL)

Disable read access watch in this PREGION

◆ MWU_REGIONEN_PRGN0RA_Enable

#define MWU_REGIONEN_PRGN0RA_Enable   (1UL)

Enable read access watch in this PREGION

◆ MWU_REGIONEN_PRGN0RA_Msk

#define MWU_REGIONEN_PRGN0RA_Msk   (0x1UL << MWU_REGIONEN_PRGN0RA_Pos)

Bit mask of PRGN0RA field.

◆ MWU_REGIONEN_PRGN0RA_Pos

#define MWU_REGIONEN_PRGN0RA_Pos   (25UL)

Position of PRGN0RA field.

◆ MWU_REGIONEN_PRGN0WA_Disable

#define MWU_REGIONEN_PRGN0WA_Disable   (0UL)

Disable write access watch in this PREGION

◆ MWU_REGIONEN_PRGN0WA_Enable

#define MWU_REGIONEN_PRGN0WA_Enable   (1UL)

Enable write access watch in this PREGION

◆ MWU_REGIONEN_PRGN0WA_Msk

#define MWU_REGIONEN_PRGN0WA_Msk   (0x1UL << MWU_REGIONEN_PRGN0WA_Pos)

Bit mask of PRGN0WA field.

◆ MWU_REGIONEN_PRGN0WA_Pos

#define MWU_REGIONEN_PRGN0WA_Pos   (24UL)

Position of PRGN0WA field.

◆ MWU_REGIONEN_PRGN1RA_Disable

#define MWU_REGIONEN_PRGN1RA_Disable   (0UL)

Disable read access watch in this PREGION

◆ MWU_REGIONEN_PRGN1RA_Enable

#define MWU_REGIONEN_PRGN1RA_Enable   (1UL)

Enable read access watch in this PREGION

◆ MWU_REGIONEN_PRGN1RA_Msk

#define MWU_REGIONEN_PRGN1RA_Msk   (0x1UL << MWU_REGIONEN_PRGN1RA_Pos)

Bit mask of PRGN1RA field.

◆ MWU_REGIONEN_PRGN1RA_Pos

#define MWU_REGIONEN_PRGN1RA_Pos   (27UL)

Position of PRGN1RA field.

◆ MWU_REGIONEN_PRGN1WA_Disable

#define MWU_REGIONEN_PRGN1WA_Disable   (0UL)

Disable write access watch in this PREGION

◆ MWU_REGIONEN_PRGN1WA_Enable

#define MWU_REGIONEN_PRGN1WA_Enable   (1UL)

Enable write access watch in this PREGION

◆ MWU_REGIONEN_PRGN1WA_Msk

#define MWU_REGIONEN_PRGN1WA_Msk   (0x1UL << MWU_REGIONEN_PRGN1WA_Pos)

Bit mask of PRGN1WA field.

◆ MWU_REGIONEN_PRGN1WA_Pos

#define MWU_REGIONEN_PRGN1WA_Pos   (26UL)

Position of PRGN1WA field.

◆ MWU_REGIONEN_RGN0RA_Disable

#define MWU_REGIONEN_RGN0RA_Disable   (0UL)

Disable read access watch in this region

◆ MWU_REGIONEN_RGN0RA_Enable

#define MWU_REGIONEN_RGN0RA_Enable   (1UL)

Enable read access watch in this region

◆ MWU_REGIONEN_RGN0RA_Msk

#define MWU_REGIONEN_RGN0RA_Msk   (0x1UL << MWU_REGIONEN_RGN0RA_Pos)

Bit mask of RGN0RA field.

◆ MWU_REGIONEN_RGN0RA_Pos

#define MWU_REGIONEN_RGN0RA_Pos   (1UL)

Position of RGN0RA field.

◆ MWU_REGIONEN_RGN0WA_Disable

#define MWU_REGIONEN_RGN0WA_Disable   (0UL)

Disable write access watch in this region

◆ MWU_REGIONEN_RGN0WA_Enable

#define MWU_REGIONEN_RGN0WA_Enable   (1UL)

Enable write access watch in this region

◆ MWU_REGIONEN_RGN0WA_Msk

#define MWU_REGIONEN_RGN0WA_Msk   (0x1UL << MWU_REGIONEN_RGN0WA_Pos)

Bit mask of RGN0WA field.

◆ MWU_REGIONEN_RGN0WA_Pos

#define MWU_REGIONEN_RGN0WA_Pos   (0UL)

Position of RGN0WA field.

◆ MWU_REGIONEN_RGN1RA_Disable

#define MWU_REGIONEN_RGN1RA_Disable   (0UL)

Disable read access watch in this region

◆ MWU_REGIONEN_RGN1RA_Enable

#define MWU_REGIONEN_RGN1RA_Enable   (1UL)

Enable read access watch in this region

◆ MWU_REGIONEN_RGN1RA_Msk

#define MWU_REGIONEN_RGN1RA_Msk   (0x1UL << MWU_REGIONEN_RGN1RA_Pos)

Bit mask of RGN1RA field.

◆ MWU_REGIONEN_RGN1RA_Pos

#define MWU_REGIONEN_RGN1RA_Pos   (3UL)

Position of RGN1RA field.

◆ MWU_REGIONEN_RGN1WA_Disable

#define MWU_REGIONEN_RGN1WA_Disable   (0UL)

Disable write access watch in this region

◆ MWU_REGIONEN_RGN1WA_Enable

#define MWU_REGIONEN_RGN1WA_Enable   (1UL)

Enable write access watch in this region

◆ MWU_REGIONEN_RGN1WA_Msk

#define MWU_REGIONEN_RGN1WA_Msk   (0x1UL << MWU_REGIONEN_RGN1WA_Pos)

Bit mask of RGN1WA field.

◆ MWU_REGIONEN_RGN1WA_Pos

#define MWU_REGIONEN_RGN1WA_Pos   (2UL)

Position of RGN1WA field.

◆ MWU_REGIONEN_RGN2RA_Disable

#define MWU_REGIONEN_RGN2RA_Disable   (0UL)

Disable read access watch in this region

◆ MWU_REGIONEN_RGN2RA_Enable

#define MWU_REGIONEN_RGN2RA_Enable   (1UL)

Enable read access watch in this region

◆ MWU_REGIONEN_RGN2RA_Msk

#define MWU_REGIONEN_RGN2RA_Msk   (0x1UL << MWU_REGIONEN_RGN2RA_Pos)

Bit mask of RGN2RA field.

◆ MWU_REGIONEN_RGN2RA_Pos

#define MWU_REGIONEN_RGN2RA_Pos   (5UL)

Position of RGN2RA field.

◆ MWU_REGIONEN_RGN2WA_Disable

#define MWU_REGIONEN_RGN2WA_Disable   (0UL)

Disable write access watch in this region

◆ MWU_REGIONEN_RGN2WA_Enable

#define MWU_REGIONEN_RGN2WA_Enable   (1UL)

Enable write access watch in this region

◆ MWU_REGIONEN_RGN2WA_Msk

#define MWU_REGIONEN_RGN2WA_Msk   (0x1UL << MWU_REGIONEN_RGN2WA_Pos)

Bit mask of RGN2WA field.

◆ MWU_REGIONEN_RGN2WA_Pos

#define MWU_REGIONEN_RGN2WA_Pos   (4UL)

Position of RGN2WA field.

◆ MWU_REGIONEN_RGN3RA_Disable

#define MWU_REGIONEN_RGN3RA_Disable   (0UL)

Disable read access watch in this region

◆ MWU_REGIONEN_RGN3RA_Enable

#define MWU_REGIONEN_RGN3RA_Enable   (1UL)

Enable read access watch in this region

◆ MWU_REGIONEN_RGN3RA_Msk

#define MWU_REGIONEN_RGN3RA_Msk   (0x1UL << MWU_REGIONEN_RGN3RA_Pos)

Bit mask of RGN3RA field.

◆ MWU_REGIONEN_RGN3RA_Pos

#define MWU_REGIONEN_RGN3RA_Pos   (7UL)

Position of RGN3RA field.

◆ MWU_REGIONEN_RGN3WA_Disable

#define MWU_REGIONEN_RGN3WA_Disable   (0UL)

Disable write access watch in this region

◆ MWU_REGIONEN_RGN3WA_Enable

#define MWU_REGIONEN_RGN3WA_Enable   (1UL)

Enable write access watch in this region

◆ MWU_REGIONEN_RGN3WA_Msk

#define MWU_REGIONEN_RGN3WA_Msk   (0x1UL << MWU_REGIONEN_RGN3WA_Pos)

Bit mask of RGN3WA field.

◆ MWU_REGIONEN_RGN3WA_Pos

#define MWU_REGIONEN_RGN3WA_Pos   (6UL)

Position of RGN3WA field.

◆ MWU_REGIONENCLR_PRGN0RA_Clear

#define MWU_REGIONENCLR_PRGN0RA_Clear   (1UL)

Disable read access watch in this PREGION

◆ MWU_REGIONENCLR_PRGN0RA_Disabled

#define MWU_REGIONENCLR_PRGN0RA_Disabled   (0UL)

Read access watch in this PREGION is disabled

◆ MWU_REGIONENCLR_PRGN0RA_Enabled

#define MWU_REGIONENCLR_PRGN0RA_Enabled   (1UL)

Read access watch in this PREGION is enabled

◆ MWU_REGIONENCLR_PRGN0RA_Msk

#define MWU_REGIONENCLR_PRGN0RA_Msk   (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos)

Bit mask of PRGN0RA field.

◆ MWU_REGIONENCLR_PRGN0RA_Pos

#define MWU_REGIONENCLR_PRGN0RA_Pos   (25UL)

Position of PRGN0RA field.

◆ MWU_REGIONENCLR_PRGN0WA_Clear

#define MWU_REGIONENCLR_PRGN0WA_Clear   (1UL)

Disable write access watch in this PREGION

◆ MWU_REGIONENCLR_PRGN0WA_Disabled

#define MWU_REGIONENCLR_PRGN0WA_Disabled   (0UL)

Write access watch in this PREGION is disabled

◆ MWU_REGIONENCLR_PRGN0WA_Enabled

#define MWU_REGIONENCLR_PRGN0WA_Enabled   (1UL)

Write access watch in this PREGION is enabled

◆ MWU_REGIONENCLR_PRGN0WA_Msk

#define MWU_REGIONENCLR_PRGN0WA_Msk   (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos)

Bit mask of PRGN0WA field.

◆ MWU_REGIONENCLR_PRGN0WA_Pos

#define MWU_REGIONENCLR_PRGN0WA_Pos   (24UL)

Position of PRGN0WA field.

◆ MWU_REGIONENCLR_PRGN1RA_Clear

#define MWU_REGIONENCLR_PRGN1RA_Clear   (1UL)

Disable read access watch in this PREGION

◆ MWU_REGIONENCLR_PRGN1RA_Disabled

#define MWU_REGIONENCLR_PRGN1RA_Disabled   (0UL)

Read access watch in this PREGION is disabled

◆ MWU_REGIONENCLR_PRGN1RA_Enabled

#define MWU_REGIONENCLR_PRGN1RA_Enabled   (1UL)

Read access watch in this PREGION is enabled

◆ MWU_REGIONENCLR_PRGN1RA_Msk

#define MWU_REGIONENCLR_PRGN1RA_Msk   (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos)

Bit mask of PRGN1RA field.

◆ MWU_REGIONENCLR_PRGN1RA_Pos

#define MWU_REGIONENCLR_PRGN1RA_Pos   (27UL)

Position of PRGN1RA field.

◆ MWU_REGIONENCLR_PRGN1WA_Clear

#define MWU_REGIONENCLR_PRGN1WA_Clear   (1UL)

Disable write access watch in this PREGION

◆ MWU_REGIONENCLR_PRGN1WA_Disabled

#define MWU_REGIONENCLR_PRGN1WA_Disabled   (0UL)

Write access watch in this PREGION is disabled

◆ MWU_REGIONENCLR_PRGN1WA_Enabled

#define MWU_REGIONENCLR_PRGN1WA_Enabled   (1UL)

Write access watch in this PREGION is enabled

◆ MWU_REGIONENCLR_PRGN1WA_Msk

#define MWU_REGIONENCLR_PRGN1WA_Msk   (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos)

Bit mask of PRGN1WA field.

◆ MWU_REGIONENCLR_PRGN1WA_Pos

#define MWU_REGIONENCLR_PRGN1WA_Pos   (26UL)

Position of PRGN1WA field.

◆ MWU_REGIONENCLR_RGN0RA_Clear

#define MWU_REGIONENCLR_RGN0RA_Clear   (1UL)

Disable read access watch in this region

◆ MWU_REGIONENCLR_RGN0RA_Disabled

#define MWU_REGIONENCLR_RGN0RA_Disabled   (0UL)

Read access watch in this region is disabled

◆ MWU_REGIONENCLR_RGN0RA_Enabled

#define MWU_REGIONENCLR_RGN0RA_Enabled   (1UL)

Read access watch in this region is enabled

◆ MWU_REGIONENCLR_RGN0RA_Msk

#define MWU_REGIONENCLR_RGN0RA_Msk   (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos)

Bit mask of RGN0RA field.

◆ MWU_REGIONENCLR_RGN0RA_Pos

#define MWU_REGIONENCLR_RGN0RA_Pos   (1UL)

Position of RGN0RA field.

◆ MWU_REGIONENCLR_RGN0WA_Clear

#define MWU_REGIONENCLR_RGN0WA_Clear   (1UL)

Disable write access watch in this region

◆ MWU_REGIONENCLR_RGN0WA_Disabled

#define MWU_REGIONENCLR_RGN0WA_Disabled   (0UL)

Write access watch in this region is disabled

◆ MWU_REGIONENCLR_RGN0WA_Enabled

#define MWU_REGIONENCLR_RGN0WA_Enabled   (1UL)

Write access watch in this region is enabled

◆ MWU_REGIONENCLR_RGN0WA_Msk

#define MWU_REGIONENCLR_RGN0WA_Msk   (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos)

Bit mask of RGN0WA field.

◆ MWU_REGIONENCLR_RGN0WA_Pos

#define MWU_REGIONENCLR_RGN0WA_Pos   (0UL)

Position of RGN0WA field.

◆ MWU_REGIONENCLR_RGN1RA_Clear

#define MWU_REGIONENCLR_RGN1RA_Clear   (1UL)

Disable read access watch in this region

◆ MWU_REGIONENCLR_RGN1RA_Disabled

#define MWU_REGIONENCLR_RGN1RA_Disabled   (0UL)

Read access watch in this region is disabled

◆ MWU_REGIONENCLR_RGN1RA_Enabled

#define MWU_REGIONENCLR_RGN1RA_Enabled   (1UL)

Read access watch in this region is enabled

◆ MWU_REGIONENCLR_RGN1RA_Msk

#define MWU_REGIONENCLR_RGN1RA_Msk   (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos)

Bit mask of RGN1RA field.

◆ MWU_REGIONENCLR_RGN1RA_Pos

#define MWU_REGIONENCLR_RGN1RA_Pos   (3UL)

Position of RGN1RA field.

◆ MWU_REGIONENCLR_RGN1WA_Clear

#define MWU_REGIONENCLR_RGN1WA_Clear   (1UL)

Disable write access watch in this region

◆ MWU_REGIONENCLR_RGN1WA_Disabled

#define MWU_REGIONENCLR_RGN1WA_Disabled   (0UL)

Write access watch in this region is disabled

◆ MWU_REGIONENCLR_RGN1WA_Enabled

#define MWU_REGIONENCLR_RGN1WA_Enabled   (1UL)

Write access watch in this region is enabled

◆ MWU_REGIONENCLR_RGN1WA_Msk

#define MWU_REGIONENCLR_RGN1WA_Msk   (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos)

Bit mask of RGN1WA field.

◆ MWU_REGIONENCLR_RGN1WA_Pos

#define MWU_REGIONENCLR_RGN1WA_Pos   (2UL)

Position of RGN1WA field.

◆ MWU_REGIONENCLR_RGN2RA_Clear

#define MWU_REGIONENCLR_RGN2RA_Clear   (1UL)

Disable read access watch in this region

◆ MWU_REGIONENCLR_RGN2RA_Disabled

#define MWU_REGIONENCLR_RGN2RA_Disabled   (0UL)

Read access watch in this region is disabled

◆ MWU_REGIONENCLR_RGN2RA_Enabled

#define MWU_REGIONENCLR_RGN2RA_Enabled   (1UL)

Read access watch in this region is enabled

◆ MWU_REGIONENCLR_RGN2RA_Msk

#define MWU_REGIONENCLR_RGN2RA_Msk   (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos)

Bit mask of RGN2RA field.

◆ MWU_REGIONENCLR_RGN2RA_Pos

#define MWU_REGIONENCLR_RGN2RA_Pos   (5UL)

Position of RGN2RA field.

◆ MWU_REGIONENCLR_RGN2WA_Clear

#define MWU_REGIONENCLR_RGN2WA_Clear   (1UL)

Disable write access watch in this region

◆ MWU_REGIONENCLR_RGN2WA_Disabled

#define MWU_REGIONENCLR_RGN2WA_Disabled   (0UL)

Write access watch in this region is disabled

◆ MWU_REGIONENCLR_RGN2WA_Enabled

#define MWU_REGIONENCLR_RGN2WA_Enabled   (1UL)

Write access watch in this region is enabled

◆ MWU_REGIONENCLR_RGN2WA_Msk

#define MWU_REGIONENCLR_RGN2WA_Msk   (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos)

Bit mask of RGN2WA field.

◆ MWU_REGIONENCLR_RGN2WA_Pos

#define MWU_REGIONENCLR_RGN2WA_Pos   (4UL)

Position of RGN2WA field.

◆ MWU_REGIONENCLR_RGN3RA_Clear

#define MWU_REGIONENCLR_RGN3RA_Clear   (1UL)

Disable read access watch in this region

◆ MWU_REGIONENCLR_RGN3RA_Disabled

#define MWU_REGIONENCLR_RGN3RA_Disabled   (0UL)

Read access watch in this region is disabled

◆ MWU_REGIONENCLR_RGN3RA_Enabled

#define MWU_REGIONENCLR_RGN3RA_Enabled   (1UL)

Read access watch in this region is enabled

◆ MWU_REGIONENCLR_RGN3RA_Msk

#define MWU_REGIONENCLR_RGN3RA_Msk   (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos)

Bit mask of RGN3RA field.

◆ MWU_REGIONENCLR_RGN3RA_Pos

#define MWU_REGIONENCLR_RGN3RA_Pos   (7UL)

Position of RGN3RA field.

◆ MWU_REGIONENCLR_RGN3WA_Clear

#define MWU_REGIONENCLR_RGN3WA_Clear   (1UL)

Disable write access watch in this region

◆ MWU_REGIONENCLR_RGN3WA_Disabled

#define MWU_REGIONENCLR_RGN3WA_Disabled   (0UL)

Write access watch in this region is disabled

◆ MWU_REGIONENCLR_RGN3WA_Enabled

#define MWU_REGIONENCLR_RGN3WA_Enabled   (1UL)

Write access watch in this region is enabled

◆ MWU_REGIONENCLR_RGN3WA_Msk

#define MWU_REGIONENCLR_RGN3WA_Msk   (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos)

Bit mask of RGN3WA field.

◆ MWU_REGIONENCLR_RGN3WA_Pos

#define MWU_REGIONENCLR_RGN3WA_Pos   (6UL)

Position of RGN3WA field.

◆ MWU_REGIONENSET_PRGN0RA_Disabled

#define MWU_REGIONENSET_PRGN0RA_Disabled   (0UL)

Read access watch in this PREGION is disabled

◆ MWU_REGIONENSET_PRGN0RA_Enabled

#define MWU_REGIONENSET_PRGN0RA_Enabled   (1UL)

Read access watch in this PREGION is enabled

◆ MWU_REGIONENSET_PRGN0RA_Msk

#define MWU_REGIONENSET_PRGN0RA_Msk   (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos)

Bit mask of PRGN0RA field.

◆ MWU_REGIONENSET_PRGN0RA_Pos

#define MWU_REGIONENSET_PRGN0RA_Pos   (25UL)

Position of PRGN0RA field.

◆ MWU_REGIONENSET_PRGN0RA_Set

#define MWU_REGIONENSET_PRGN0RA_Set   (1UL)

Enable read access watch in this PREGION

◆ MWU_REGIONENSET_PRGN0WA_Disabled

#define MWU_REGIONENSET_PRGN0WA_Disabled   (0UL)

Write access watch in this PREGION is disabled

◆ MWU_REGIONENSET_PRGN0WA_Enabled

#define MWU_REGIONENSET_PRGN0WA_Enabled   (1UL)

Write access watch in this PREGION is enabled

◆ MWU_REGIONENSET_PRGN0WA_Msk

#define MWU_REGIONENSET_PRGN0WA_Msk   (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos)

Bit mask of PRGN0WA field.

◆ MWU_REGIONENSET_PRGN0WA_Pos

#define MWU_REGIONENSET_PRGN0WA_Pos   (24UL)

Position of PRGN0WA field.

◆ MWU_REGIONENSET_PRGN0WA_Set

#define MWU_REGIONENSET_PRGN0WA_Set   (1UL)

Enable write access watch in this PREGION

◆ MWU_REGIONENSET_PRGN1RA_Disabled

#define MWU_REGIONENSET_PRGN1RA_Disabled   (0UL)

Read access watch in this PREGION is disabled

◆ MWU_REGIONENSET_PRGN1RA_Enabled

#define MWU_REGIONENSET_PRGN1RA_Enabled   (1UL)

Read access watch in this PREGION is enabled

◆ MWU_REGIONENSET_PRGN1RA_Msk

#define MWU_REGIONENSET_PRGN1RA_Msk   (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos)

Bit mask of PRGN1RA field.

◆ MWU_REGIONENSET_PRGN1RA_Pos

#define MWU_REGIONENSET_PRGN1RA_Pos   (27UL)

Position of PRGN1RA field.

◆ MWU_REGIONENSET_PRGN1RA_Set

#define MWU_REGIONENSET_PRGN1RA_Set   (1UL)

Enable read access watch in this PREGION

◆ MWU_REGIONENSET_PRGN1WA_Disabled

#define MWU_REGIONENSET_PRGN1WA_Disabled   (0UL)

Write access watch in this PREGION is disabled

◆ MWU_REGIONENSET_PRGN1WA_Enabled

#define MWU_REGIONENSET_PRGN1WA_Enabled   (1UL)

Write access watch in this PREGION is enabled

◆ MWU_REGIONENSET_PRGN1WA_Msk

#define MWU_REGIONENSET_PRGN1WA_Msk   (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos)

Bit mask of PRGN1WA field.

◆ MWU_REGIONENSET_PRGN1WA_Pos

#define MWU_REGIONENSET_PRGN1WA_Pos   (26UL)

Position of PRGN1WA field.

◆ MWU_REGIONENSET_PRGN1WA_Set

#define MWU_REGIONENSET_PRGN1WA_Set   (1UL)

Enable write access watch in this PREGION

◆ MWU_REGIONENSET_RGN0RA_Disabled

#define MWU_REGIONENSET_RGN0RA_Disabled   (0UL)

Read access watch in this region is disabled

◆ MWU_REGIONENSET_RGN0RA_Enabled

#define MWU_REGIONENSET_RGN0RA_Enabled   (1UL)

Read access watch in this region is enabled

◆ MWU_REGIONENSET_RGN0RA_Msk

#define MWU_REGIONENSET_RGN0RA_Msk   (0x1UL << MWU_REGIONENSET_RGN0RA_Pos)

Bit mask of RGN0RA field.

◆ MWU_REGIONENSET_RGN0RA_Pos

#define MWU_REGIONENSET_RGN0RA_Pos   (1UL)

Position of RGN0RA field.

◆ MWU_REGIONENSET_RGN0RA_Set

#define MWU_REGIONENSET_RGN0RA_Set   (1UL)

Enable read access watch in this region

◆ MWU_REGIONENSET_RGN0WA_Disabled

#define MWU_REGIONENSET_RGN0WA_Disabled   (0UL)

Write access watch in this region is disabled

◆ MWU_REGIONENSET_RGN0WA_Enabled

#define MWU_REGIONENSET_RGN0WA_Enabled   (1UL)

Write access watch in this region is enabled

◆ MWU_REGIONENSET_RGN0WA_Msk

#define MWU_REGIONENSET_RGN0WA_Msk   (0x1UL << MWU_REGIONENSET_RGN0WA_Pos)

Bit mask of RGN0WA field.

◆ MWU_REGIONENSET_RGN0WA_Pos

#define MWU_REGIONENSET_RGN0WA_Pos   (0UL)

Position of RGN0WA field.

◆ MWU_REGIONENSET_RGN0WA_Set

#define MWU_REGIONENSET_RGN0WA_Set   (1UL)

Enable write access watch in this region

◆ MWU_REGIONENSET_RGN1RA_Disabled

#define MWU_REGIONENSET_RGN1RA_Disabled   (0UL)

Read access watch in this region is disabled

◆ MWU_REGIONENSET_RGN1RA_Enabled

#define MWU_REGIONENSET_RGN1RA_Enabled   (1UL)

Read access watch in this region is enabled

◆ MWU_REGIONENSET_RGN1RA_Msk

#define MWU_REGIONENSET_RGN1RA_Msk   (0x1UL << MWU_REGIONENSET_RGN1RA_Pos)

Bit mask of RGN1RA field.

◆ MWU_REGIONENSET_RGN1RA_Pos

#define MWU_REGIONENSET_RGN1RA_Pos   (3UL)

Position of RGN1RA field.

◆ MWU_REGIONENSET_RGN1RA_Set

#define MWU_REGIONENSET_RGN1RA_Set   (1UL)

Enable read access watch in this region

◆ MWU_REGIONENSET_RGN1WA_Disabled

#define MWU_REGIONENSET_RGN1WA_Disabled   (0UL)

Write access watch in this region is disabled

◆ MWU_REGIONENSET_RGN1WA_Enabled

#define MWU_REGIONENSET_RGN1WA_Enabled   (1UL)

Write access watch in this region is enabled

◆ MWU_REGIONENSET_RGN1WA_Msk

#define MWU_REGIONENSET_RGN1WA_Msk   (0x1UL << MWU_REGIONENSET_RGN1WA_Pos)

Bit mask of RGN1WA field.

◆ MWU_REGIONENSET_RGN1WA_Pos

#define MWU_REGIONENSET_RGN1WA_Pos   (2UL)

Position of RGN1WA field.

◆ MWU_REGIONENSET_RGN1WA_Set

#define MWU_REGIONENSET_RGN1WA_Set   (1UL)

Enable write access watch in this region

◆ MWU_REGIONENSET_RGN2RA_Disabled

#define MWU_REGIONENSET_RGN2RA_Disabled   (0UL)

Read access watch in this region is disabled

◆ MWU_REGIONENSET_RGN2RA_Enabled

#define MWU_REGIONENSET_RGN2RA_Enabled   (1UL)

Read access watch in this region is enabled

◆ MWU_REGIONENSET_RGN2RA_Msk

#define MWU_REGIONENSET_RGN2RA_Msk   (0x1UL << MWU_REGIONENSET_RGN2RA_Pos)

Bit mask of RGN2RA field.

◆ MWU_REGIONENSET_RGN2RA_Pos

#define MWU_REGIONENSET_RGN2RA_Pos   (5UL)

Position of RGN2RA field.

◆ MWU_REGIONENSET_RGN2RA_Set

#define MWU_REGIONENSET_RGN2RA_Set   (1UL)

Enable read access watch in this region

◆ MWU_REGIONENSET_RGN2WA_Disabled

#define MWU_REGIONENSET_RGN2WA_Disabled   (0UL)

Write access watch in this region is disabled

◆ MWU_REGIONENSET_RGN2WA_Enabled

#define MWU_REGIONENSET_RGN2WA_Enabled   (1UL)

Write access watch in this region is enabled

◆ MWU_REGIONENSET_RGN2WA_Msk

#define MWU_REGIONENSET_RGN2WA_Msk   (0x1UL << MWU_REGIONENSET_RGN2WA_Pos)

Bit mask of RGN2WA field.

◆ MWU_REGIONENSET_RGN2WA_Pos

#define MWU_REGIONENSET_RGN2WA_Pos   (4UL)

Position of RGN2WA field.

◆ MWU_REGIONENSET_RGN2WA_Set

#define MWU_REGIONENSET_RGN2WA_Set   (1UL)

Enable write access watch in this region

◆ MWU_REGIONENSET_RGN3RA_Disabled

#define MWU_REGIONENSET_RGN3RA_Disabled   (0UL)

Read access watch in this region is disabled

◆ MWU_REGIONENSET_RGN3RA_Enabled

#define MWU_REGIONENSET_RGN3RA_Enabled   (1UL)

Read access watch in this region is enabled

◆ MWU_REGIONENSET_RGN3RA_Msk

#define MWU_REGIONENSET_RGN3RA_Msk   (0x1UL << MWU_REGIONENSET_RGN3RA_Pos)

Bit mask of RGN3RA field.

◆ MWU_REGIONENSET_RGN3RA_Pos

#define MWU_REGIONENSET_RGN3RA_Pos   (7UL)

Position of RGN3RA field.

◆ MWU_REGIONENSET_RGN3RA_Set

#define MWU_REGIONENSET_RGN3RA_Set   (1UL)

Enable read access watch in this region

◆ MWU_REGIONENSET_RGN3WA_Disabled

#define MWU_REGIONENSET_RGN3WA_Disabled   (0UL)

Write access watch in this region is disabled

◆ MWU_REGIONENSET_RGN3WA_Enabled

#define MWU_REGIONENSET_RGN3WA_Enabled   (1UL)

Write access watch in this region is enabled

◆ MWU_REGIONENSET_RGN3WA_Msk

#define MWU_REGIONENSET_RGN3WA_Msk   (0x1UL << MWU_REGIONENSET_RGN3WA_Pos)

Bit mask of RGN3WA field.

◆ MWU_REGIONENSET_RGN3WA_Pos

#define MWU_REGIONENSET_RGN3WA_Pos   (6UL)

Position of RGN3WA field.

◆ MWU_REGIONENSET_RGN3WA_Set

#define MWU_REGIONENSET_RGN3WA_Set   (1UL)

Enable write access watch in this region

◆ NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk

#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk   (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos)

Bit mask of CURRENTLOADCTRL field.

◆ NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos

#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos   (0UL)

Position of CURRENTLOADCTRL field.

◆ NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk

#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk   (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos)

Bit mask of FRAMEDELAYTIMEOUT field.

◆ NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos

#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos   (0UL)

Position of FRAMEDELAYTIMEOUT field.

◆ NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk

#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk   (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos)

Bit mask of NFCFIELDTOOSTRONG field.

◆ NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos

#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos   (2UL)

Position of NFCFIELDTOOSTRONG field.

◆ NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk

#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk   (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos)

Bit mask of NFCFIELDTOOWEAK field.

◆ NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos

#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos   (3UL)

Position of NFCFIELDTOOWEAK field.

◆ NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent

#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent   (1UL)

Valid field detected

◆ NFCT_FIELDPRESENT_FIELDPRESENT_Msk

#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk   (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos)

Bit mask of FIELDPRESENT field.

◆ NFCT_FIELDPRESENT_FIELDPRESENT_NoField

#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField   (0UL)

No valid field detected

◆ NFCT_FIELDPRESENT_FIELDPRESENT_Pos

#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos   (0UL)

Position of FIELDPRESENT field.

◆ NFCT_FIELDPRESENT_LOCKDETECT_Locked

#define NFCT_FIELDPRESENT_LOCKDETECT_Locked   (1UL)

Locked to field

◆ NFCT_FIELDPRESENT_LOCKDETECT_Msk

#define NFCT_FIELDPRESENT_LOCKDETECT_Msk   (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos)

Bit mask of LOCKDETECT field.

◆ NFCT_FIELDPRESENT_LOCKDETECT_NotLocked

#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked   (0UL)

Not locked to field

◆ NFCT_FIELDPRESENT_LOCKDETECT_Pos

#define NFCT_FIELDPRESENT_LOCKDETECT_Pos   (1UL)

Position of LOCKDETECT field.

◆ NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk

#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk   (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos)

Bit mask of FRAMEDELAYMAX field.

◆ NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos

#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos   (0UL)

Position of FRAMEDELAYMAX field.

◆ NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk

#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk   (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos)

Bit mask of FRAMEDELAYMIN field.

◆ NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos

#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos   (0UL)

Position of FRAMEDELAYMIN field.

◆ NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal

#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal   (2UL)

Frame is transmitted exactly at FRAMEDELAYMAX

◆ NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun

#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun   (0UL)

Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.

◆ NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk

#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk   (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos)

Bit mask of FRAMEDELAYMODE field.

◆ NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos

#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos   (0UL)

Position of FRAMEDELAYMODE field.

◆ NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window

#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window   (1UL)

Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX

◆ NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid

#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid   (3UL)

Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX

◆ NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect

#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect   (0UL)

Valid CRC detected

◆ NFCT_FRAMESTATUS_RX_CRCERROR_CRCError

#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError   (1UL)

CRC received does not match local check

◆ NFCT_FRAMESTATUS_RX_CRCERROR_Msk

#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk   (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos)

Bit mask of CRCERROR field.

◆ NFCT_FRAMESTATUS_RX_CRCERROR_Pos

#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos   (0UL)

Position of CRCERROR field.

◆ NFCT_FRAMESTATUS_RX_OVERRUN_Msk

#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk   (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos)

Bit mask of OVERRUN field.

◆ NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun

#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun   (0UL)

No overrun detected

◆ NFCT_FRAMESTATUS_RX_OVERRUN_Overrun

#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun   (1UL)

Overrun error

◆ NFCT_FRAMESTATUS_RX_OVERRUN_Pos

#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos   (3UL)

Position of OVERRUN field.

◆ NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk

#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk   (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos)

Bit mask of PARITYSTATUS field.

◆ NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError

#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError   (1UL)

Frame received with parity error

◆ NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK

#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK   (0UL)

Frame received with parity OK

◆ NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos

#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos   (2UL)

Position of PARITYSTATUS field.

◆ NFCT_INTEN_AUTOCOLRESSTARTED_Disabled

#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled   (0UL)

Disable

◆ NFCT_INTEN_AUTOCOLRESSTARTED_Enabled

#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled   (1UL)

Enable

◆ NFCT_INTEN_AUTOCOLRESSTARTED_Msk

#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk   (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos)

Bit mask of AUTOCOLRESSTARTED field.

◆ NFCT_INTEN_AUTOCOLRESSTARTED_Pos

#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos   (14UL)

Position of AUTOCOLRESSTARTED field.

◆ NFCT_INTEN_COLLISION_Disabled

#define NFCT_INTEN_COLLISION_Disabled   (0UL)

Disable

◆ NFCT_INTEN_COLLISION_Enabled

#define NFCT_INTEN_COLLISION_Enabled   (1UL)

Enable

◆ NFCT_INTEN_COLLISION_Msk

#define NFCT_INTEN_COLLISION_Msk   (0x1UL << NFCT_INTEN_COLLISION_Pos)

Bit mask of COLLISION field.

◆ NFCT_INTEN_COLLISION_Pos

#define NFCT_INTEN_COLLISION_Pos   (18UL)

Position of COLLISION field.

◆ NFCT_INTEN_ENDRX_Disabled

#define NFCT_INTEN_ENDRX_Disabled   (0UL)

Disable

◆ NFCT_INTEN_ENDRX_Enabled

#define NFCT_INTEN_ENDRX_Enabled   (1UL)

Enable

◆ NFCT_INTEN_ENDRX_Msk

#define NFCT_INTEN_ENDRX_Msk   (0x1UL << NFCT_INTEN_ENDRX_Pos)

Bit mask of ENDRX field.

◆ NFCT_INTEN_ENDRX_Pos

#define NFCT_INTEN_ENDRX_Pos   (11UL)

Position of ENDRX field.

◆ NFCT_INTEN_ENDTX_Disabled

#define NFCT_INTEN_ENDTX_Disabled   (0UL)

Disable

◆ NFCT_INTEN_ENDTX_Enabled

#define NFCT_INTEN_ENDTX_Enabled   (1UL)

Enable

◆ NFCT_INTEN_ENDTX_Msk

#define NFCT_INTEN_ENDTX_Msk   (0x1UL << NFCT_INTEN_ENDTX_Pos)

Bit mask of ENDTX field.

◆ NFCT_INTEN_ENDTX_Pos

#define NFCT_INTEN_ENDTX_Pos   (12UL)

Position of ENDTX field.

◆ NFCT_INTEN_ERROR_Disabled

#define NFCT_INTEN_ERROR_Disabled   (0UL)

Disable

◆ NFCT_INTEN_ERROR_Enabled

#define NFCT_INTEN_ERROR_Enabled   (1UL)

Enable

◆ NFCT_INTEN_ERROR_Msk

#define NFCT_INTEN_ERROR_Msk   (0x1UL << NFCT_INTEN_ERROR_Pos)

Bit mask of ERROR field.

◆ NFCT_INTEN_ERROR_Pos

#define NFCT_INTEN_ERROR_Pos   (7UL)

Position of ERROR field.

◆ NFCT_INTEN_FIELDDETECTED_Disabled

#define NFCT_INTEN_FIELDDETECTED_Disabled   (0UL)

Disable

◆ NFCT_INTEN_FIELDDETECTED_Enabled

#define NFCT_INTEN_FIELDDETECTED_Enabled   (1UL)

Enable

◆ NFCT_INTEN_FIELDDETECTED_Msk

#define NFCT_INTEN_FIELDDETECTED_Msk   (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos)

Bit mask of FIELDDETECTED field.

◆ NFCT_INTEN_FIELDDETECTED_Pos

#define NFCT_INTEN_FIELDDETECTED_Pos   (1UL)

Position of FIELDDETECTED field.

◆ NFCT_INTEN_FIELDLOST_Disabled

#define NFCT_INTEN_FIELDLOST_Disabled   (0UL)

Disable

◆ NFCT_INTEN_FIELDLOST_Enabled

#define NFCT_INTEN_FIELDLOST_Enabled   (1UL)

Enable

◆ NFCT_INTEN_FIELDLOST_Msk

#define NFCT_INTEN_FIELDLOST_Msk   (0x1UL << NFCT_INTEN_FIELDLOST_Pos)

Bit mask of FIELDLOST field.

◆ NFCT_INTEN_FIELDLOST_Pos

#define NFCT_INTEN_FIELDLOST_Pos   (2UL)

Position of FIELDLOST field.

◆ NFCT_INTEN_READY_Disabled

#define NFCT_INTEN_READY_Disabled   (0UL)

Disable

◆ NFCT_INTEN_READY_Enabled

#define NFCT_INTEN_READY_Enabled   (1UL)

Enable

◆ NFCT_INTEN_READY_Msk

#define NFCT_INTEN_READY_Msk   (0x1UL << NFCT_INTEN_READY_Pos)

Bit mask of READY field.

◆ NFCT_INTEN_READY_Pos

#define NFCT_INTEN_READY_Pos   (0UL)

Position of READY field.

◆ NFCT_INTEN_RXERROR_Disabled

#define NFCT_INTEN_RXERROR_Disabled   (0UL)

Disable

◆ NFCT_INTEN_RXERROR_Enabled

#define NFCT_INTEN_RXERROR_Enabled   (1UL)

Enable

◆ NFCT_INTEN_RXERROR_Msk

#define NFCT_INTEN_RXERROR_Msk   (0x1UL << NFCT_INTEN_RXERROR_Pos)

Bit mask of RXERROR field.

◆ NFCT_INTEN_RXERROR_Pos

#define NFCT_INTEN_RXERROR_Pos   (10UL)

Position of RXERROR field.

◆ NFCT_INTEN_RXFRAMEEND_Disabled

#define NFCT_INTEN_RXFRAMEEND_Disabled   (0UL)

Disable

◆ NFCT_INTEN_RXFRAMEEND_Enabled

#define NFCT_INTEN_RXFRAMEEND_Enabled   (1UL)

Enable

◆ NFCT_INTEN_RXFRAMEEND_Msk

#define NFCT_INTEN_RXFRAMEEND_Msk   (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos)

Bit mask of RXFRAMEEND field.

◆ NFCT_INTEN_RXFRAMEEND_Pos

#define NFCT_INTEN_RXFRAMEEND_Pos   (6UL)

Position of RXFRAMEEND field.

◆ NFCT_INTEN_RXFRAMESTART_Disabled

#define NFCT_INTEN_RXFRAMESTART_Disabled   (0UL)

Disable

◆ NFCT_INTEN_RXFRAMESTART_Enabled

#define NFCT_INTEN_RXFRAMESTART_Enabled   (1UL)

Enable

◆ NFCT_INTEN_RXFRAMESTART_Msk

#define NFCT_INTEN_RXFRAMESTART_Msk   (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos)

Bit mask of RXFRAMESTART field.

◆ NFCT_INTEN_RXFRAMESTART_Pos

#define NFCT_INTEN_RXFRAMESTART_Pos   (5UL)

Position of RXFRAMESTART field.

◆ NFCT_INTEN_SELECTED_Disabled

#define NFCT_INTEN_SELECTED_Disabled   (0UL)

Disable

◆ NFCT_INTEN_SELECTED_Enabled

#define NFCT_INTEN_SELECTED_Enabled   (1UL)

Enable

◆ NFCT_INTEN_SELECTED_Msk

#define NFCT_INTEN_SELECTED_Msk   (0x1UL << NFCT_INTEN_SELECTED_Pos)

Bit mask of SELECTED field.

◆ NFCT_INTEN_SELECTED_Pos

#define NFCT_INTEN_SELECTED_Pos   (19UL)

Position of SELECTED field.

◆ NFCT_INTEN_STARTED_Disabled

#define NFCT_INTEN_STARTED_Disabled   (0UL)

Disable

◆ NFCT_INTEN_STARTED_Enabled

#define NFCT_INTEN_STARTED_Enabled   (1UL)

Enable

◆ NFCT_INTEN_STARTED_Msk

#define NFCT_INTEN_STARTED_Msk   (0x1UL << NFCT_INTEN_STARTED_Pos)

Bit mask of STARTED field.

◆ NFCT_INTEN_STARTED_Pos

#define NFCT_INTEN_STARTED_Pos   (20UL)

Position of STARTED field.

◆ NFCT_INTEN_TXFRAMEEND_Disabled

#define NFCT_INTEN_TXFRAMEEND_Disabled   (0UL)

Disable

◆ NFCT_INTEN_TXFRAMEEND_Enabled

#define NFCT_INTEN_TXFRAMEEND_Enabled   (1UL)

Enable

◆ NFCT_INTEN_TXFRAMEEND_Msk

#define NFCT_INTEN_TXFRAMEEND_Msk   (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos)

Bit mask of TXFRAMEEND field.

◆ NFCT_INTEN_TXFRAMEEND_Pos

#define NFCT_INTEN_TXFRAMEEND_Pos   (4UL)

Position of TXFRAMEEND field.

◆ NFCT_INTEN_TXFRAMESTART_Disabled

#define NFCT_INTEN_TXFRAMESTART_Disabled   (0UL)

Disable

◆ NFCT_INTEN_TXFRAMESTART_Enabled

#define NFCT_INTEN_TXFRAMESTART_Enabled   (1UL)

Enable

◆ NFCT_INTEN_TXFRAMESTART_Msk

#define NFCT_INTEN_TXFRAMESTART_Msk   (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos)

Bit mask of TXFRAMESTART field.

◆ NFCT_INTEN_TXFRAMESTART_Pos

#define NFCT_INTEN_TXFRAMESTART_Pos   (3UL)

Position of TXFRAMESTART field.

◆ NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear

#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled

#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled

#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk

#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk   (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos)

Bit mask of AUTOCOLRESSTARTED field.

◆ NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos

#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos   (14UL)

Position of AUTOCOLRESSTARTED field.

◆ NFCT_INTENCLR_COLLISION_Clear

#define NFCT_INTENCLR_COLLISION_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_COLLISION_Disabled

#define NFCT_INTENCLR_COLLISION_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_COLLISION_Enabled

#define NFCT_INTENCLR_COLLISION_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_COLLISION_Msk

#define NFCT_INTENCLR_COLLISION_Msk   (0x1UL << NFCT_INTENCLR_COLLISION_Pos)

Bit mask of COLLISION field.

◆ NFCT_INTENCLR_COLLISION_Pos

#define NFCT_INTENCLR_COLLISION_Pos   (18UL)

Position of COLLISION field.

◆ NFCT_INTENCLR_ENDRX_Clear

#define NFCT_INTENCLR_ENDRX_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_ENDRX_Disabled

#define NFCT_INTENCLR_ENDRX_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_ENDRX_Enabled

#define NFCT_INTENCLR_ENDRX_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_ENDRX_Msk

#define NFCT_INTENCLR_ENDRX_Msk   (0x1UL << NFCT_INTENCLR_ENDRX_Pos)

Bit mask of ENDRX field.

◆ NFCT_INTENCLR_ENDRX_Pos

#define NFCT_INTENCLR_ENDRX_Pos   (11UL)

Position of ENDRX field.

◆ NFCT_INTENCLR_ENDTX_Clear

#define NFCT_INTENCLR_ENDTX_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_ENDTX_Disabled

#define NFCT_INTENCLR_ENDTX_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_ENDTX_Enabled

#define NFCT_INTENCLR_ENDTX_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_ENDTX_Msk

#define NFCT_INTENCLR_ENDTX_Msk   (0x1UL << NFCT_INTENCLR_ENDTX_Pos)

Bit mask of ENDTX field.

◆ NFCT_INTENCLR_ENDTX_Pos

#define NFCT_INTENCLR_ENDTX_Pos   (12UL)

Position of ENDTX field.

◆ NFCT_INTENCLR_ERROR_Clear

#define NFCT_INTENCLR_ERROR_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_ERROR_Disabled

#define NFCT_INTENCLR_ERROR_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_ERROR_Enabled

#define NFCT_INTENCLR_ERROR_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_ERROR_Msk

#define NFCT_INTENCLR_ERROR_Msk   (0x1UL << NFCT_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

◆ NFCT_INTENCLR_ERROR_Pos

#define NFCT_INTENCLR_ERROR_Pos   (7UL)

Position of ERROR field.

◆ NFCT_INTENCLR_FIELDDETECTED_Clear

#define NFCT_INTENCLR_FIELDDETECTED_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_FIELDDETECTED_Disabled

#define NFCT_INTENCLR_FIELDDETECTED_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_FIELDDETECTED_Enabled

#define NFCT_INTENCLR_FIELDDETECTED_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_FIELDDETECTED_Msk

#define NFCT_INTENCLR_FIELDDETECTED_Msk   (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos)

Bit mask of FIELDDETECTED field.

◆ NFCT_INTENCLR_FIELDDETECTED_Pos

#define NFCT_INTENCLR_FIELDDETECTED_Pos   (1UL)

Position of FIELDDETECTED field.

◆ NFCT_INTENCLR_FIELDLOST_Clear

#define NFCT_INTENCLR_FIELDLOST_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_FIELDLOST_Disabled

#define NFCT_INTENCLR_FIELDLOST_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_FIELDLOST_Enabled

#define NFCT_INTENCLR_FIELDLOST_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_FIELDLOST_Msk

#define NFCT_INTENCLR_FIELDLOST_Msk   (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos)

Bit mask of FIELDLOST field.

◆ NFCT_INTENCLR_FIELDLOST_Pos

#define NFCT_INTENCLR_FIELDLOST_Pos   (2UL)

Position of FIELDLOST field.

◆ NFCT_INTENCLR_READY_Clear

#define NFCT_INTENCLR_READY_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_READY_Disabled

#define NFCT_INTENCLR_READY_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_READY_Enabled

#define NFCT_INTENCLR_READY_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_READY_Msk

#define NFCT_INTENCLR_READY_Msk   (0x1UL << NFCT_INTENCLR_READY_Pos)

Bit mask of READY field.

◆ NFCT_INTENCLR_READY_Pos

#define NFCT_INTENCLR_READY_Pos   (0UL)

Position of READY field.

◆ NFCT_INTENCLR_RXERROR_Clear

#define NFCT_INTENCLR_RXERROR_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_RXERROR_Disabled

#define NFCT_INTENCLR_RXERROR_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_RXERROR_Enabled

#define NFCT_INTENCLR_RXERROR_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_RXERROR_Msk

#define NFCT_INTENCLR_RXERROR_Msk   (0x1UL << NFCT_INTENCLR_RXERROR_Pos)

Bit mask of RXERROR field.

◆ NFCT_INTENCLR_RXERROR_Pos

#define NFCT_INTENCLR_RXERROR_Pos   (10UL)

Position of RXERROR field.

◆ NFCT_INTENCLR_RXFRAMEEND_Clear

#define NFCT_INTENCLR_RXFRAMEEND_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_RXFRAMEEND_Disabled

#define NFCT_INTENCLR_RXFRAMEEND_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_RXFRAMEEND_Enabled

#define NFCT_INTENCLR_RXFRAMEEND_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_RXFRAMEEND_Msk

#define NFCT_INTENCLR_RXFRAMEEND_Msk   (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos)

Bit mask of RXFRAMEEND field.

◆ NFCT_INTENCLR_RXFRAMEEND_Pos

#define NFCT_INTENCLR_RXFRAMEEND_Pos   (6UL)

Position of RXFRAMEEND field.

◆ NFCT_INTENCLR_RXFRAMESTART_Clear

#define NFCT_INTENCLR_RXFRAMESTART_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_RXFRAMESTART_Disabled

#define NFCT_INTENCLR_RXFRAMESTART_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_RXFRAMESTART_Enabled

#define NFCT_INTENCLR_RXFRAMESTART_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_RXFRAMESTART_Msk

#define NFCT_INTENCLR_RXFRAMESTART_Msk   (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos)

Bit mask of RXFRAMESTART field.

◆ NFCT_INTENCLR_RXFRAMESTART_Pos

#define NFCT_INTENCLR_RXFRAMESTART_Pos   (5UL)

Position of RXFRAMESTART field.

◆ NFCT_INTENCLR_SELECTED_Clear

#define NFCT_INTENCLR_SELECTED_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_SELECTED_Disabled

#define NFCT_INTENCLR_SELECTED_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_SELECTED_Enabled

#define NFCT_INTENCLR_SELECTED_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_SELECTED_Msk

#define NFCT_INTENCLR_SELECTED_Msk   (0x1UL << NFCT_INTENCLR_SELECTED_Pos)

Bit mask of SELECTED field.

◆ NFCT_INTENCLR_SELECTED_Pos

#define NFCT_INTENCLR_SELECTED_Pos   (19UL)

Position of SELECTED field.

◆ NFCT_INTENCLR_STARTED_Clear

#define NFCT_INTENCLR_STARTED_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_STARTED_Disabled

#define NFCT_INTENCLR_STARTED_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_STARTED_Enabled

#define NFCT_INTENCLR_STARTED_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_STARTED_Msk

#define NFCT_INTENCLR_STARTED_Msk   (0x1UL << NFCT_INTENCLR_STARTED_Pos)

Bit mask of STARTED field.

◆ NFCT_INTENCLR_STARTED_Pos

#define NFCT_INTENCLR_STARTED_Pos   (20UL)

Position of STARTED field.

◆ NFCT_INTENCLR_TXFRAMEEND_Clear

#define NFCT_INTENCLR_TXFRAMEEND_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_TXFRAMEEND_Disabled

#define NFCT_INTENCLR_TXFRAMEEND_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_TXFRAMEEND_Enabled

#define NFCT_INTENCLR_TXFRAMEEND_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_TXFRAMEEND_Msk

#define NFCT_INTENCLR_TXFRAMEEND_Msk   (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos)

Bit mask of TXFRAMEEND field.

◆ NFCT_INTENCLR_TXFRAMEEND_Pos

#define NFCT_INTENCLR_TXFRAMEEND_Pos   (4UL)

Position of TXFRAMEEND field.

◆ NFCT_INTENCLR_TXFRAMESTART_Clear

#define NFCT_INTENCLR_TXFRAMESTART_Clear   (1UL)

Disable

◆ NFCT_INTENCLR_TXFRAMESTART_Disabled

#define NFCT_INTENCLR_TXFRAMESTART_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENCLR_TXFRAMESTART_Enabled

#define NFCT_INTENCLR_TXFRAMESTART_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENCLR_TXFRAMESTART_Msk

#define NFCT_INTENCLR_TXFRAMESTART_Msk   (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos)

Bit mask of TXFRAMESTART field.

◆ NFCT_INTENCLR_TXFRAMESTART_Pos

#define NFCT_INTENCLR_TXFRAMESTART_Pos   (3UL)

Position of TXFRAMESTART field.

◆ NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled

#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled

#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_AUTOCOLRESSTARTED_Msk

#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk   (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos)

Bit mask of AUTOCOLRESSTARTED field.

◆ NFCT_INTENSET_AUTOCOLRESSTARTED_Pos

#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos   (14UL)

Position of AUTOCOLRESSTARTED field.

◆ NFCT_INTENSET_AUTOCOLRESSTARTED_Set

#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set   (1UL)

Enable

◆ NFCT_INTENSET_COLLISION_Disabled

#define NFCT_INTENSET_COLLISION_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_COLLISION_Enabled

#define NFCT_INTENSET_COLLISION_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_COLLISION_Msk

#define NFCT_INTENSET_COLLISION_Msk   (0x1UL << NFCT_INTENSET_COLLISION_Pos)

Bit mask of COLLISION field.

◆ NFCT_INTENSET_COLLISION_Pos

#define NFCT_INTENSET_COLLISION_Pos   (18UL)

Position of COLLISION field.

◆ NFCT_INTENSET_COLLISION_Set

#define NFCT_INTENSET_COLLISION_Set   (1UL)

Enable

◆ NFCT_INTENSET_ENDRX_Disabled

#define NFCT_INTENSET_ENDRX_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_ENDRX_Enabled

#define NFCT_INTENSET_ENDRX_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_ENDRX_Msk

#define NFCT_INTENSET_ENDRX_Msk   (0x1UL << NFCT_INTENSET_ENDRX_Pos)

Bit mask of ENDRX field.

◆ NFCT_INTENSET_ENDRX_Pos

#define NFCT_INTENSET_ENDRX_Pos   (11UL)

Position of ENDRX field.

◆ NFCT_INTENSET_ENDRX_Set

#define NFCT_INTENSET_ENDRX_Set   (1UL)

Enable

◆ NFCT_INTENSET_ENDTX_Disabled

#define NFCT_INTENSET_ENDTX_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_ENDTX_Enabled

#define NFCT_INTENSET_ENDTX_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_ENDTX_Msk

#define NFCT_INTENSET_ENDTX_Msk   (0x1UL << NFCT_INTENSET_ENDTX_Pos)

Bit mask of ENDTX field.

◆ NFCT_INTENSET_ENDTX_Pos

#define NFCT_INTENSET_ENDTX_Pos   (12UL)

Position of ENDTX field.

◆ NFCT_INTENSET_ENDTX_Set

#define NFCT_INTENSET_ENDTX_Set   (1UL)

Enable

◆ NFCT_INTENSET_ERROR_Disabled

#define NFCT_INTENSET_ERROR_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_ERROR_Enabled

#define NFCT_INTENSET_ERROR_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_ERROR_Msk

#define NFCT_INTENSET_ERROR_Msk   (0x1UL << NFCT_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

◆ NFCT_INTENSET_ERROR_Pos

#define NFCT_INTENSET_ERROR_Pos   (7UL)

Position of ERROR field.

◆ NFCT_INTENSET_ERROR_Set

#define NFCT_INTENSET_ERROR_Set   (1UL)

Enable

◆ NFCT_INTENSET_FIELDDETECTED_Disabled

#define NFCT_INTENSET_FIELDDETECTED_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_FIELDDETECTED_Enabled

#define NFCT_INTENSET_FIELDDETECTED_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_FIELDDETECTED_Msk

#define NFCT_INTENSET_FIELDDETECTED_Msk   (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos)

Bit mask of FIELDDETECTED field.

◆ NFCT_INTENSET_FIELDDETECTED_Pos

#define NFCT_INTENSET_FIELDDETECTED_Pos   (1UL)

Position of FIELDDETECTED field.

◆ NFCT_INTENSET_FIELDDETECTED_Set

#define NFCT_INTENSET_FIELDDETECTED_Set   (1UL)

Enable

◆ NFCT_INTENSET_FIELDLOST_Disabled

#define NFCT_INTENSET_FIELDLOST_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_FIELDLOST_Enabled

#define NFCT_INTENSET_FIELDLOST_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_FIELDLOST_Msk

#define NFCT_INTENSET_FIELDLOST_Msk   (0x1UL << NFCT_INTENSET_FIELDLOST_Pos)

Bit mask of FIELDLOST field.

◆ NFCT_INTENSET_FIELDLOST_Pos

#define NFCT_INTENSET_FIELDLOST_Pos   (2UL)

Position of FIELDLOST field.

◆ NFCT_INTENSET_FIELDLOST_Set

#define NFCT_INTENSET_FIELDLOST_Set   (1UL)

Enable

◆ NFCT_INTENSET_READY_Disabled

#define NFCT_INTENSET_READY_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_READY_Enabled

#define NFCT_INTENSET_READY_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_READY_Msk

#define NFCT_INTENSET_READY_Msk   (0x1UL << NFCT_INTENSET_READY_Pos)

Bit mask of READY field.

◆ NFCT_INTENSET_READY_Pos

#define NFCT_INTENSET_READY_Pos   (0UL)

Position of READY field.

◆ NFCT_INTENSET_READY_Set

#define NFCT_INTENSET_READY_Set   (1UL)

Enable

◆ NFCT_INTENSET_RXERROR_Disabled

#define NFCT_INTENSET_RXERROR_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_RXERROR_Enabled

#define NFCT_INTENSET_RXERROR_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_RXERROR_Msk

#define NFCT_INTENSET_RXERROR_Msk   (0x1UL << NFCT_INTENSET_RXERROR_Pos)

Bit mask of RXERROR field.

◆ NFCT_INTENSET_RXERROR_Pos

#define NFCT_INTENSET_RXERROR_Pos   (10UL)

Position of RXERROR field.

◆ NFCT_INTENSET_RXERROR_Set

#define NFCT_INTENSET_RXERROR_Set   (1UL)

Enable

◆ NFCT_INTENSET_RXFRAMEEND_Disabled

#define NFCT_INTENSET_RXFRAMEEND_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_RXFRAMEEND_Enabled

#define NFCT_INTENSET_RXFRAMEEND_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_RXFRAMEEND_Msk

#define NFCT_INTENSET_RXFRAMEEND_Msk   (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos)

Bit mask of RXFRAMEEND field.

◆ NFCT_INTENSET_RXFRAMEEND_Pos

#define NFCT_INTENSET_RXFRAMEEND_Pos   (6UL)

Position of RXFRAMEEND field.

◆ NFCT_INTENSET_RXFRAMEEND_Set

#define NFCT_INTENSET_RXFRAMEEND_Set   (1UL)

Enable

◆ NFCT_INTENSET_RXFRAMESTART_Disabled

#define NFCT_INTENSET_RXFRAMESTART_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_RXFRAMESTART_Enabled

#define NFCT_INTENSET_RXFRAMESTART_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_RXFRAMESTART_Msk

#define NFCT_INTENSET_RXFRAMESTART_Msk   (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos)

Bit mask of RXFRAMESTART field.

◆ NFCT_INTENSET_RXFRAMESTART_Pos

#define NFCT_INTENSET_RXFRAMESTART_Pos   (5UL)

Position of RXFRAMESTART field.

◆ NFCT_INTENSET_RXFRAMESTART_Set

#define NFCT_INTENSET_RXFRAMESTART_Set   (1UL)

Enable

◆ NFCT_INTENSET_SELECTED_Disabled

#define NFCT_INTENSET_SELECTED_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_SELECTED_Enabled

#define NFCT_INTENSET_SELECTED_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_SELECTED_Msk

#define NFCT_INTENSET_SELECTED_Msk   (0x1UL << NFCT_INTENSET_SELECTED_Pos)

Bit mask of SELECTED field.

◆ NFCT_INTENSET_SELECTED_Pos

#define NFCT_INTENSET_SELECTED_Pos   (19UL)

Position of SELECTED field.

◆ NFCT_INTENSET_SELECTED_Set

#define NFCT_INTENSET_SELECTED_Set   (1UL)

Enable

◆ NFCT_INTENSET_STARTED_Disabled

#define NFCT_INTENSET_STARTED_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_STARTED_Enabled

#define NFCT_INTENSET_STARTED_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_STARTED_Msk

#define NFCT_INTENSET_STARTED_Msk   (0x1UL << NFCT_INTENSET_STARTED_Pos)

Bit mask of STARTED field.

◆ NFCT_INTENSET_STARTED_Pos

#define NFCT_INTENSET_STARTED_Pos   (20UL)

Position of STARTED field.

◆ NFCT_INTENSET_STARTED_Set

#define NFCT_INTENSET_STARTED_Set   (1UL)

Enable

◆ NFCT_INTENSET_TXFRAMEEND_Disabled

#define NFCT_INTENSET_TXFRAMEEND_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_TXFRAMEEND_Enabled

#define NFCT_INTENSET_TXFRAMEEND_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_TXFRAMEEND_Msk

#define NFCT_INTENSET_TXFRAMEEND_Msk   (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos)

Bit mask of TXFRAMEEND field.

◆ NFCT_INTENSET_TXFRAMEEND_Pos

#define NFCT_INTENSET_TXFRAMEEND_Pos   (4UL)

Position of TXFRAMEEND field.

◆ NFCT_INTENSET_TXFRAMEEND_Set

#define NFCT_INTENSET_TXFRAMEEND_Set   (1UL)

Enable

◆ NFCT_INTENSET_TXFRAMESTART_Disabled

#define NFCT_INTENSET_TXFRAMESTART_Disabled   (0UL)

Read: Disabled

◆ NFCT_INTENSET_TXFRAMESTART_Enabled

#define NFCT_INTENSET_TXFRAMESTART_Enabled   (1UL)

Read: Enabled

◆ NFCT_INTENSET_TXFRAMESTART_Msk

#define NFCT_INTENSET_TXFRAMESTART_Msk   (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos)

Bit mask of TXFRAMESTART field.

◆ NFCT_INTENSET_TXFRAMESTART_Pos

#define NFCT_INTENSET_TXFRAMESTART_Pos   (3UL)

Position of TXFRAMESTART field.

◆ NFCT_INTENSET_TXFRAMESTART_Set

#define NFCT_INTENSET_TXFRAMESTART_Set   (1UL)

Enable

◆ NFCT_MAXLEN_MAXLEN_Msk

#define NFCT_MAXLEN_MAXLEN_Msk   (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos)

Bit mask of MAXLEN field.

◆ NFCT_MAXLEN_MAXLEN_Pos

#define NFCT_MAXLEN_MAXLEN_Pos   (0UL)

Position of MAXLEN field.

◆ NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk

#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk   (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos)

Bit mask of NFCID1_T field.

◆ NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos

#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos   (16UL)

Position of NFCID1_T field.

◆ NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk

#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk   (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos)

Bit mask of NFCID1_U field.

◆ NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos

#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos   (8UL)

Position of NFCID1_U field.

◆ NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk

#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk   (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos)

Bit mask of NFCID1_V field.

◆ NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos

#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos   (0UL)

Position of NFCID1_V field.

◆ NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk

#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk   (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos)

Bit mask of NFCID1_Q field.

◆ NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos

#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos   (16UL)

Position of NFCID1_Q field.

◆ NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk

#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk   (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos)

Bit mask of NFCID1_R field.

◆ NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos

#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos   (8UL)

Position of NFCID1_R field.

◆ NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk

#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk   (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos)

Bit mask of NFCID1_S field.

◆ NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos

#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos   (0UL)

Position of NFCID1_S field.

◆ NFCT_NFCID1_LAST_NFCID1_W_Msk

#define NFCT_NFCID1_LAST_NFCID1_W_Msk   (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos)

Bit mask of NFCID1_W field.

◆ NFCT_NFCID1_LAST_NFCID1_W_Pos

#define NFCT_NFCID1_LAST_NFCID1_W_Pos   (24UL)

Position of NFCID1_W field.

◆ NFCT_NFCID1_LAST_NFCID1_X_Msk

#define NFCT_NFCID1_LAST_NFCID1_X_Msk   (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos)

Bit mask of NFCID1_X field.

◆ NFCT_NFCID1_LAST_NFCID1_X_Pos

#define NFCT_NFCID1_LAST_NFCID1_X_Pos   (16UL)

Position of NFCID1_X field.

◆ NFCT_NFCID1_LAST_NFCID1_Y_Msk

#define NFCT_NFCID1_LAST_NFCID1_Y_Msk   (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos)

Bit mask of NFCID1_Y field.

◆ NFCT_NFCID1_LAST_NFCID1_Y_Pos

#define NFCT_NFCID1_LAST_NFCID1_Y_Pos   (8UL)

Position of NFCID1_Y field.

◆ NFCT_NFCID1_LAST_NFCID1_Z_Msk

#define NFCT_NFCID1_LAST_NFCID1_Z_Msk   (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos)

Bit mask of NFCID1_Z field.

◆ NFCT_NFCID1_LAST_NFCID1_Z_Pos

#define NFCT_NFCID1_LAST_NFCID1_Z_Pos   (0UL)

Position of NFCID1_Z field.

◆ NFCT_PACKETPTR_PTR_Msk

#define NFCT_PACKETPTR_PTR_Msk   (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos)

Bit mask of PTR field.

◆ NFCT_PACKETPTR_PTR_Pos

#define NFCT_PACKETPTR_PTR_Pos   (0UL)

Position of PTR field.

◆ NFCT_RXD_AMOUNT_RXDATABITS_Msk

#define NFCT_RXD_AMOUNT_RXDATABITS_Msk   (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos)

Bit mask of RXDATABITS field.

◆ NFCT_RXD_AMOUNT_RXDATABITS_Pos

#define NFCT_RXD_AMOUNT_RXDATABITS_Pos   (0UL)

Position of RXDATABITS field.

◆ NFCT_RXD_AMOUNT_RXDATABYTES_Msk

#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk   (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos)

Bit mask of RXDATABYTES field.

◆ NFCT_RXD_AMOUNT_RXDATABYTES_Pos

#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos   (3UL)

Position of RXDATABYTES field.

◆ NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX

#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX   (1UL)

Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated

◆ NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk

#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk   (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos)

Bit mask of CRCMODERX field.

◆ NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX

#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX   (0UL)

CRC is not expected in RX frames

◆ NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos

#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos   (4UL)

Position of CRCMODERX field.

◆ NFCT_RXD_FRAMECONFIG_PARITY_Msk

#define NFCT_RXD_FRAMECONFIG_PARITY_Msk   (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos)

Bit mask of PARITY field.

◆ NFCT_RXD_FRAMECONFIG_PARITY_NoParity

#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity   (0UL)

Parity is not expected in RX frames

◆ NFCT_RXD_FRAMECONFIG_PARITY_Parity

#define NFCT_RXD_FRAMECONFIG_PARITY_Parity   (1UL)

Parity is expected in RX frames

◆ NFCT_RXD_FRAMECONFIG_PARITY_Pos

#define NFCT_RXD_FRAMECONFIG_PARITY_Pos   (0UL)

Position of PARITY field.

◆ NFCT_RXD_FRAMECONFIG_SOF_Msk

#define NFCT_RXD_FRAMECONFIG_SOF_Msk   (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos)

Bit mask of SOF field.

◆ NFCT_RXD_FRAMECONFIG_SOF_NoSoF

#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF   (0UL)

Start of Frame symbol is not expected in RX frames

◆ NFCT_RXD_FRAMECONFIG_SOF_Pos

#define NFCT_RXD_FRAMECONFIG_SOF_Pos   (2UL)

Position of SOF field.

◆ NFCT_RXD_FRAMECONFIG_SOF_SoF

#define NFCT_RXD_FRAMECONFIG_SOF_SoF   (1UL)

Start of Frame symbol is expected in RX frames

◆ NFCT_SELRES_CASCADE_Complete

#define NFCT_SELRES_CASCADE_Complete   (0UL)

NFCID1 complete

◆ NFCT_SELRES_CASCADE_Msk

#define NFCT_SELRES_CASCADE_Msk   (0x1UL << NFCT_SELRES_CASCADE_Pos)

Bit mask of CASCADE field.

◆ NFCT_SELRES_CASCADE_NotComplete

#define NFCT_SELRES_CASCADE_NotComplete   (1UL)

NFCID1 not complete

◆ NFCT_SELRES_CASCADE_Pos

#define NFCT_SELRES_CASCADE_Pos   (2UL)

Position of CASCADE field.

◆ NFCT_SELRES_PROTOCOL_Msk

#define NFCT_SELRES_PROTOCOL_Msk   (0x3UL << NFCT_SELRES_PROTOCOL_Pos)

Bit mask of PROTOCOL field.

◆ NFCT_SELRES_PROTOCOL_Pos

#define NFCT_SELRES_PROTOCOL_Pos   (5UL)

Position of PROTOCOL field.

◆ NFCT_SELRES_RFU10_Msk

#define NFCT_SELRES_RFU10_Msk   (0x3UL << NFCT_SELRES_RFU10_Pos)

Bit mask of RFU10 field.

◆ NFCT_SELRES_RFU10_Pos

#define NFCT_SELRES_RFU10_Pos   (0UL)

Position of RFU10 field.

◆ NFCT_SELRES_RFU43_Msk

#define NFCT_SELRES_RFU43_Msk   (0x3UL << NFCT_SELRES_RFU43_Pos)

Bit mask of RFU43 field.

◆ NFCT_SELRES_RFU43_Pos

#define NFCT_SELRES_RFU43_Pos   (3UL)

Position of RFU43 field.

◆ NFCT_SELRES_RFU7_Msk

#define NFCT_SELRES_RFU7_Msk   (0x1UL << NFCT_SELRES_RFU7_Pos)

Bit mask of RFU7 field.

◆ NFCT_SELRES_RFU7_Pos

#define NFCT_SELRES_RFU7_Pos   (7UL)

Position of RFU7 field.

◆ NFCT_SENSRES_BITFRAMESDD_Msk

#define NFCT_SENSRES_BITFRAMESDD_Msk   (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos)

Bit mask of BITFRAMESDD field.

◆ NFCT_SENSRES_BITFRAMESDD_Pos

#define NFCT_SENSRES_BITFRAMESDD_Pos   (0UL)

Position of BITFRAMESDD field.

◆ NFCT_SENSRES_BITFRAMESDD_SDD00000

#define NFCT_SENSRES_BITFRAMESDD_SDD00000   (0UL)

SDD pattern 00000

◆ NFCT_SENSRES_BITFRAMESDD_SDD00001

#define NFCT_SENSRES_BITFRAMESDD_SDD00001   (1UL)

SDD pattern 00001

◆ NFCT_SENSRES_BITFRAMESDD_SDD00010

#define NFCT_SENSRES_BITFRAMESDD_SDD00010   (2UL)

SDD pattern 00010

◆ NFCT_SENSRES_BITFRAMESDD_SDD00100

#define NFCT_SENSRES_BITFRAMESDD_SDD00100   (4UL)

SDD pattern 00100

◆ NFCT_SENSRES_BITFRAMESDD_SDD01000

#define NFCT_SENSRES_BITFRAMESDD_SDD01000   (8UL)

SDD pattern 01000

◆ NFCT_SENSRES_BITFRAMESDD_SDD10000

#define NFCT_SENSRES_BITFRAMESDD_SDD10000   (16UL)

SDD pattern 10000

◆ NFCT_SENSRES_NFCIDSIZE_Msk

#define NFCT_SENSRES_NFCIDSIZE_Msk   (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos)

Bit mask of NFCIDSIZE field.

◆ NFCT_SENSRES_NFCIDSIZE_NFCID1Double

#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double   (1UL)

NFCID1 size: double (7 bytes)

◆ NFCT_SENSRES_NFCIDSIZE_NFCID1Single

#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single   (0UL)

NFCID1 size: single (4 bytes)

◆ NFCT_SENSRES_NFCIDSIZE_NFCID1Triple

#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple   (2UL)

NFCID1 size: triple (10 bytes)

◆ NFCT_SENSRES_NFCIDSIZE_Pos

#define NFCT_SENSRES_NFCIDSIZE_Pos   (6UL)

Position of NFCIDSIZE field.

◆ NFCT_SENSRES_PLATFCONFIG_Msk

#define NFCT_SENSRES_PLATFCONFIG_Msk   (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos)

Bit mask of PLATFCONFIG field.

◆ NFCT_SENSRES_PLATFCONFIG_Pos

#define NFCT_SENSRES_PLATFCONFIG_Pos   (8UL)

Position of PLATFCONFIG field.

◆ NFCT_SENSRES_RFU5_Msk

#define NFCT_SENSRES_RFU5_Msk   (0x1UL << NFCT_SENSRES_RFU5_Pos)

Bit mask of RFU5 field.

◆ NFCT_SENSRES_RFU5_Pos

#define NFCT_SENSRES_RFU5_Pos   (5UL)

Position of RFU5 field.

◆ NFCT_SENSRES_RFU74_Msk

#define NFCT_SENSRES_RFU74_Msk   (0xFUL << NFCT_SENSRES_RFU74_Pos)

Bit mask of RFU74 field.

◆ NFCT_SENSRES_RFU74_Pos

#define NFCT_SENSRES_RFU74_Pos   (12UL)

Position of RFU74 field.

◆ NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled

#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled   (0UL)

Disable shortcut

◆ NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled

#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled   (1UL)

Enable shortcut

◆ NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk

#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk   (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos)

Bit mask of FIELDDETECTED_ACTIVATE field.

◆ NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos

#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos   (0UL)

Position of FIELDDETECTED_ACTIVATE field.

◆ NFCT_SHORTS_FIELDLOST_SENSE_Disabled

#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled   (0UL)

Disable shortcut

◆ NFCT_SHORTS_FIELDLOST_SENSE_Enabled

#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled   (1UL)

Enable shortcut

◆ NFCT_SHORTS_FIELDLOST_SENSE_Msk

#define NFCT_SHORTS_FIELDLOST_SENSE_Msk   (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos)

Bit mask of FIELDLOST_SENSE field.

◆ NFCT_SHORTS_FIELDLOST_SENSE_Pos

#define NFCT_SHORTS_FIELDLOST_SENSE_Pos   (1UL)

Position of FIELDLOST_SENSE field.

◆ NFCT_TXD_AMOUNT_TXDATABITS_Msk

#define NFCT_TXD_AMOUNT_TXDATABITS_Msk   (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos)

Bit mask of TXDATABITS field.

◆ NFCT_TXD_AMOUNT_TXDATABITS_Pos

#define NFCT_TXD_AMOUNT_TXDATABITS_Pos   (0UL)

Position of TXDATABITS field.

◆ NFCT_TXD_AMOUNT_TXDATABYTES_Msk

#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk   (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos)

Bit mask of TXDATABYTES field.

◆ NFCT_TXD_AMOUNT_TXDATABYTES_Pos

#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos   (3UL)

Position of TXDATABYTES field.

◆ NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX

#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX   (1UL)

16 bit CRC added to the frame based on all the data read from RAM that is used in the frame

◆ NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk

#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk   (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos)

Bit mask of CRCMODETX field.

◆ NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX

#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX   (0UL)

CRC is not added to the frame

◆ NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos

#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos   (4UL)

Position of CRCMODETX field.

◆ NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd

#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd   (0UL)

Unused bits is discarded at end of frame

◆ NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart

#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart   (1UL)

Unused bits is discarded at start of frame

◆ NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk

#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk   (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos)

Bit mask of DISCARDMODE field.

◆ NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos

#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos   (1UL)

Position of DISCARDMODE field.

◆ NFCT_TXD_FRAMECONFIG_PARITY_Msk

#define NFCT_TXD_FRAMECONFIG_PARITY_Msk   (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos)

Bit mask of PARITY field.

◆ NFCT_TXD_FRAMECONFIG_PARITY_NoParity

#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity   (0UL)

Parity is not added in TX frames

◆ NFCT_TXD_FRAMECONFIG_PARITY_Parity

#define NFCT_TXD_FRAMECONFIG_PARITY_Parity   (1UL)

Parity is added TX frames

◆ NFCT_TXD_FRAMECONFIG_PARITY_Pos

#define NFCT_TXD_FRAMECONFIG_PARITY_Pos   (0UL)

Position of PARITY field.

◆ NFCT_TXD_FRAMECONFIG_SOF_Msk

#define NFCT_TXD_FRAMECONFIG_SOF_Msk   (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos)

Bit mask of SOF field.

◆ NFCT_TXD_FRAMECONFIG_SOF_NoSoF

#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF   (0UL)

Start of Frame symbol not added

◆ NFCT_TXD_FRAMECONFIG_SOF_Pos

#define NFCT_TXD_FRAMECONFIG_SOF_Pos   (2UL)

Position of SOF field.

◆ NFCT_TXD_FRAMECONFIG_SOF_SoF

#define NFCT_TXD_FRAMECONFIG_SOF_SoF   (1UL)

Start of Frame symbol added

◆ NVMC_CONFIG_WEN_Een

#define NVMC_CONFIG_WEN_Een   (2UL)

Erase enabled

◆ NVMC_CONFIG_WEN_Msk

#define NVMC_CONFIG_WEN_Msk   (0x3UL << NVMC_CONFIG_WEN_Pos)

Bit mask of WEN field.

◆ NVMC_CONFIG_WEN_Pos

#define NVMC_CONFIG_WEN_Pos   (0UL)

Position of WEN field.

◆ NVMC_CONFIG_WEN_Ren

#define NVMC_CONFIG_WEN_Ren   (0UL)

Read only access

◆ NVMC_CONFIG_WEN_Wen

#define NVMC_CONFIG_WEN_Wen   (1UL)

Write Enabled

◆ NVMC_ERASEALL_ERASEALL_Erase

#define NVMC_ERASEALL_ERASEALL_Erase   (1UL)

Start chip erase

◆ NVMC_ERASEALL_ERASEALL_Msk

#define NVMC_ERASEALL_ERASEALL_Msk   (0x1UL << NVMC_ERASEALL_ERASEALL_Pos)

Bit mask of ERASEALL field.

◆ NVMC_ERASEALL_ERASEALL_NoOperation

#define NVMC_ERASEALL_ERASEALL_NoOperation   (0UL)

No operation

◆ NVMC_ERASEALL_ERASEALL_Pos

#define NVMC_ERASEALL_ERASEALL_Pos   (0UL)

Position of ERASEALL field.

◆ NVMC_ERASEPAGE_ERASEPAGE_Msk

#define NVMC_ERASEPAGE_ERASEPAGE_Msk   (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos)

Bit mask of ERASEPAGE field.

◆ NVMC_ERASEPAGE_ERASEPAGE_Pos

#define NVMC_ERASEPAGE_ERASEPAGE_Pos   (0UL)

Position of ERASEPAGE field.

◆ NVMC_ERASEPCR0_ERASEPCR0_Msk

#define NVMC_ERASEPCR0_ERASEPCR0_Msk   (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos)

Bit mask of ERASEPCR0 field.

◆ NVMC_ERASEPCR0_ERASEPCR0_Pos

#define NVMC_ERASEPCR0_ERASEPCR0_Pos   (0UL)

Position of ERASEPCR0 field.

◆ NVMC_ERASEPCR1_ERASEPCR1_Msk

#define NVMC_ERASEPCR1_ERASEPCR1_Msk   (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos)

Bit mask of ERASEPCR1 field.

◆ NVMC_ERASEPCR1_ERASEPCR1_Pos

#define NVMC_ERASEPCR1_ERASEPCR1_Pos   (0UL)

Position of ERASEPCR1 field.

◆ NVMC_ERASEUICR_ERASEUICR_Erase

#define NVMC_ERASEUICR_ERASEUICR_Erase   (1UL)

Start erase of UICR

◆ NVMC_ERASEUICR_ERASEUICR_Msk

#define NVMC_ERASEUICR_ERASEUICR_Msk   (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos)

Bit mask of ERASEUICR field.

◆ NVMC_ERASEUICR_ERASEUICR_NoOperation

#define NVMC_ERASEUICR_ERASEUICR_NoOperation   (0UL)

No operation

◆ NVMC_ERASEUICR_ERASEUICR_Pos

#define NVMC_ERASEUICR_ERASEUICR_Pos   (0UL)

Position of ERASEUICR field.

◆ NVMC_ICACHECNF_CACHEEN_Disabled

#define NVMC_ICACHECNF_CACHEEN_Disabled   (0UL)

Disable cache. Invalidates all cache entries.

◆ NVMC_ICACHECNF_CACHEEN_Enabled

#define NVMC_ICACHECNF_CACHEEN_Enabled   (1UL)

Enable cache

◆ NVMC_ICACHECNF_CACHEEN_Msk

#define NVMC_ICACHECNF_CACHEEN_Msk   (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos)

Bit mask of CACHEEN field.

◆ NVMC_ICACHECNF_CACHEEN_Pos

#define NVMC_ICACHECNF_CACHEEN_Pos   (0UL)

Position of CACHEEN field.

◆ NVMC_ICACHECNF_CACHEPROFEN_Disabled

#define NVMC_ICACHECNF_CACHEPROFEN_Disabled   (0UL)

Disable cache profiling

◆ NVMC_ICACHECNF_CACHEPROFEN_Enabled

#define NVMC_ICACHECNF_CACHEPROFEN_Enabled   (1UL)

Enable cache profiling

◆ NVMC_ICACHECNF_CACHEPROFEN_Msk

#define NVMC_ICACHECNF_CACHEPROFEN_Msk   (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos)

Bit mask of CACHEPROFEN field.

◆ NVMC_ICACHECNF_CACHEPROFEN_Pos

#define NVMC_ICACHECNF_CACHEPROFEN_Pos   (8UL)

Position of CACHEPROFEN field.

◆ NVMC_IHIT_HITS_Msk

#define NVMC_IHIT_HITS_Msk   (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos)

Bit mask of HITS field.

◆ NVMC_IHIT_HITS_Pos

#define NVMC_IHIT_HITS_Pos   (0UL)

Position of HITS field.

◆ NVMC_IMISS_MISSES_Msk

#define NVMC_IMISS_MISSES_Msk   (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos)

Bit mask of MISSES field.

◆ NVMC_IMISS_MISSES_Pos

#define NVMC_IMISS_MISSES_Pos   (0UL)

Position of MISSES field.

◆ NVMC_READY_READY_Busy

#define NVMC_READY_READY_Busy   (0UL)

NVMC is busy (on-going write or erase operation)

◆ NVMC_READY_READY_Msk

#define NVMC_READY_READY_Msk   (0x1UL << NVMC_READY_READY_Pos)

Bit mask of READY field.

◆ NVMC_READY_READY_Pos

#define NVMC_READY_READY_Pos   (0UL)

Position of READY field.

◆ NVMC_READY_READY_Ready

#define NVMC_READY_READY_Ready   (1UL)

NVMC is ready

◆ PDM_ENABLE_ENABLE_Disabled

#define PDM_ENABLE_ENABLE_Disabled   (0UL)

Disable

◆ PDM_ENABLE_ENABLE_Enabled

#define PDM_ENABLE_ENABLE_Enabled   (1UL)

Enable

◆ PDM_ENABLE_ENABLE_Msk

#define PDM_ENABLE_ENABLE_Msk   (0x1UL << PDM_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ PDM_ENABLE_ENABLE_Pos

#define PDM_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ PDM_GAINL_GAINL_DefaultGain

#define PDM_GAINL_GAINL_DefaultGain   (0x28UL)

0dB gain adjustment ('2500 RMS' requirement)

◆ PDM_GAINL_GAINL_MaxGain

#define PDM_GAINL_GAINL_MaxGain   (0x50UL)

+20dB gain adjustment (maximum)

◆ PDM_GAINL_GAINL_MinGain

#define PDM_GAINL_GAINL_MinGain   (0x00UL)

-20dB gain adjustment (minimum)

◆ PDM_GAINL_GAINL_Msk

#define PDM_GAINL_GAINL_Msk   (0x7FUL << PDM_GAINL_GAINL_Pos)

Bit mask of GAINL field.

◆ PDM_GAINL_GAINL_Pos

#define PDM_GAINL_GAINL_Pos   (0UL)

Position of GAINL field.

◆ PDM_GAINR_GAINR_DefaultGain

#define PDM_GAINR_GAINR_DefaultGain   (0x28UL)

0dB gain adjustment ('2500 RMS' requirement)

◆ PDM_GAINR_GAINR_MaxGain

#define PDM_GAINR_GAINR_MaxGain   (0x50UL)

+20dB gain adjustment (maximum)

◆ PDM_GAINR_GAINR_MinGain

#define PDM_GAINR_GAINR_MinGain   (0x00UL)

-20dB gain adjustment (minimum)

◆ PDM_GAINR_GAINR_Msk

#define PDM_GAINR_GAINR_Msk   (0xFFUL << PDM_GAINR_GAINR_Pos)

Bit mask of GAINR field.

◆ PDM_GAINR_GAINR_Pos

#define PDM_GAINR_GAINR_Pos   (0UL)

Position of GAINR field.

◆ PDM_INTEN_END_Disabled

#define PDM_INTEN_END_Disabled   (0UL)

Disable

◆ PDM_INTEN_END_Enabled

#define PDM_INTEN_END_Enabled   (1UL)

Enable

◆ PDM_INTEN_END_Msk

#define PDM_INTEN_END_Msk   (0x1UL << PDM_INTEN_END_Pos)

Bit mask of END field.

◆ PDM_INTEN_END_Pos

#define PDM_INTEN_END_Pos   (2UL)

Position of END field.

◆ PDM_INTEN_STARTED_Disabled

#define PDM_INTEN_STARTED_Disabled   (0UL)

Disable

◆ PDM_INTEN_STARTED_Enabled

#define PDM_INTEN_STARTED_Enabled   (1UL)

Enable

◆ PDM_INTEN_STARTED_Msk

#define PDM_INTEN_STARTED_Msk   (0x1UL << PDM_INTEN_STARTED_Pos)

Bit mask of STARTED field.

◆ PDM_INTEN_STARTED_Pos

#define PDM_INTEN_STARTED_Pos   (0UL)

Position of STARTED field.

◆ PDM_INTEN_STOPPED_Disabled

#define PDM_INTEN_STOPPED_Disabled   (0UL)

Disable

◆ PDM_INTEN_STOPPED_Enabled

#define PDM_INTEN_STOPPED_Enabled   (1UL)

Enable

◆ PDM_INTEN_STOPPED_Msk

#define PDM_INTEN_STOPPED_Msk   (0x1UL << PDM_INTEN_STOPPED_Pos)

Bit mask of STOPPED field.

◆ PDM_INTEN_STOPPED_Pos

#define PDM_INTEN_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ PDM_INTENCLR_END_Clear

#define PDM_INTENCLR_END_Clear   (1UL)

Disable

◆ PDM_INTENCLR_END_Disabled

#define PDM_INTENCLR_END_Disabled   (0UL)

Read: Disabled

◆ PDM_INTENCLR_END_Enabled

#define PDM_INTENCLR_END_Enabled   (1UL)

Read: Enabled

◆ PDM_INTENCLR_END_Msk

#define PDM_INTENCLR_END_Msk   (0x1UL << PDM_INTENCLR_END_Pos)

Bit mask of END field.

◆ PDM_INTENCLR_END_Pos

#define PDM_INTENCLR_END_Pos   (2UL)

Position of END field.

◆ PDM_INTENCLR_STARTED_Clear

#define PDM_INTENCLR_STARTED_Clear   (1UL)

Disable

◆ PDM_INTENCLR_STARTED_Disabled

#define PDM_INTENCLR_STARTED_Disabled   (0UL)

Read: Disabled

◆ PDM_INTENCLR_STARTED_Enabled

#define PDM_INTENCLR_STARTED_Enabled   (1UL)

Read: Enabled

◆ PDM_INTENCLR_STARTED_Msk

#define PDM_INTENCLR_STARTED_Msk   (0x1UL << PDM_INTENCLR_STARTED_Pos)

Bit mask of STARTED field.

◆ PDM_INTENCLR_STARTED_Pos

#define PDM_INTENCLR_STARTED_Pos   (0UL)

Position of STARTED field.

◆ PDM_INTENCLR_STOPPED_Clear

#define PDM_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ PDM_INTENCLR_STOPPED_Disabled

#define PDM_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ PDM_INTENCLR_STOPPED_Enabled

#define PDM_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ PDM_INTENCLR_STOPPED_Msk

#define PDM_INTENCLR_STOPPED_Msk   (0x1UL << PDM_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ PDM_INTENCLR_STOPPED_Pos

#define PDM_INTENCLR_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ PDM_INTENSET_END_Disabled

#define PDM_INTENSET_END_Disabled   (0UL)

Read: Disabled

◆ PDM_INTENSET_END_Enabled

#define PDM_INTENSET_END_Enabled   (1UL)

Read: Enabled

◆ PDM_INTENSET_END_Msk

#define PDM_INTENSET_END_Msk   (0x1UL << PDM_INTENSET_END_Pos)

Bit mask of END field.

◆ PDM_INTENSET_END_Pos

#define PDM_INTENSET_END_Pos   (2UL)

Position of END field.

◆ PDM_INTENSET_END_Set

#define PDM_INTENSET_END_Set   (1UL)

Enable

◆ PDM_INTENSET_STARTED_Disabled

#define PDM_INTENSET_STARTED_Disabled   (0UL)

Read: Disabled

◆ PDM_INTENSET_STARTED_Enabled

#define PDM_INTENSET_STARTED_Enabled   (1UL)

Read: Enabled

◆ PDM_INTENSET_STARTED_Msk

#define PDM_INTENSET_STARTED_Msk   (0x1UL << PDM_INTENSET_STARTED_Pos)

Bit mask of STARTED field.

◆ PDM_INTENSET_STARTED_Pos

#define PDM_INTENSET_STARTED_Pos   (0UL)

Position of STARTED field.

◆ PDM_INTENSET_STARTED_Set

#define PDM_INTENSET_STARTED_Set   (1UL)

Enable

◆ PDM_INTENSET_STOPPED_Disabled

#define PDM_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ PDM_INTENSET_STOPPED_Enabled

#define PDM_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ PDM_INTENSET_STOPPED_Msk

#define PDM_INTENSET_STOPPED_Msk   (0x1UL << PDM_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ PDM_INTENSET_STOPPED_Pos

#define PDM_INTENSET_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ PDM_INTENSET_STOPPED_Set

#define PDM_INTENSET_STOPPED_Set   (1UL)

Enable

◆ PDM_MODE_EDGE_LeftFalling

#define PDM_MODE_EDGE_LeftFalling   (0UL)

Left (or mono) is sampled on falling edge of PDM_CLK

◆ PDM_MODE_EDGE_LeftRising

#define PDM_MODE_EDGE_LeftRising   (1UL)

Left (or mono) is sampled on rising edge of PDM_CLK

◆ PDM_MODE_EDGE_Msk

#define PDM_MODE_EDGE_Msk   (0x1UL << PDM_MODE_EDGE_Pos)

Bit mask of EDGE field.

◆ PDM_MODE_EDGE_Pos

#define PDM_MODE_EDGE_Pos   (1UL)

Position of EDGE field.

◆ PDM_MODE_OPERATION_Mono

#define PDM_MODE_OPERATION_Mono   (1UL)

Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]

◆ PDM_MODE_OPERATION_Msk

#define PDM_MODE_OPERATION_Msk   (0x1UL << PDM_MODE_OPERATION_Pos)

Bit mask of OPERATION field.

◆ PDM_MODE_OPERATION_Pos

#define PDM_MODE_OPERATION_Pos   (0UL)

Position of OPERATION field.

◆ PDM_MODE_OPERATION_Stereo

#define PDM_MODE_OPERATION_Stereo   (0UL)

Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]

◆ PDM_PDMCLKCTRL_FREQ_1000K

#define PDM_PDMCLKCTRL_FREQ_1000K   (0x08000000UL)

PDM_CLK = 32 MHz / 32 = 1.000 MHz

◆ PDM_PDMCLKCTRL_FREQ_1067K

#define PDM_PDMCLKCTRL_FREQ_1067K   (0x08800000UL)

PDM_CLK = 32 MHz / 30 = 1.067 MHz

◆ PDM_PDMCLKCTRL_FREQ_Default

#define PDM_PDMCLKCTRL_FREQ_Default   (0x08400000UL)

PDM_CLK = 32 MHz / 31 = 1.032 MHz

◆ PDM_PDMCLKCTRL_FREQ_Msk

#define PDM_PDMCLKCTRL_FREQ_Msk   (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos)

Bit mask of FREQ field.

◆ PDM_PDMCLKCTRL_FREQ_Pos

#define PDM_PDMCLKCTRL_FREQ_Pos   (0UL)

Position of FREQ field.

◆ PDM_PSEL_CLK_CONNECT_Connected

#define PDM_PSEL_CLK_CONNECT_Connected   (0UL)

Connect

◆ PDM_PSEL_CLK_CONNECT_Disconnected

#define PDM_PSEL_CLK_CONNECT_Disconnected   (1UL)

Disconnect

◆ PDM_PSEL_CLK_CONNECT_Msk

#define PDM_PSEL_CLK_CONNECT_Msk   (0x1UL << PDM_PSEL_CLK_CONNECT_Pos)

Bit mask of CONNECT field.

◆ PDM_PSEL_CLK_CONNECT_Pos

#define PDM_PSEL_CLK_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ PDM_PSEL_CLK_PIN_Msk

#define PDM_PSEL_CLK_PIN_Msk   (0x1FUL << PDM_PSEL_CLK_PIN_Pos)

Bit mask of PIN field.

◆ PDM_PSEL_CLK_PIN_Pos

#define PDM_PSEL_CLK_PIN_Pos   (0UL)

Position of PIN field.

◆ PDM_PSEL_DIN_CONNECT_Connected

#define PDM_PSEL_DIN_CONNECT_Connected   (0UL)

Connect

◆ PDM_PSEL_DIN_CONNECT_Disconnected

#define PDM_PSEL_DIN_CONNECT_Disconnected   (1UL)

Disconnect

◆ PDM_PSEL_DIN_CONNECT_Msk

#define PDM_PSEL_DIN_CONNECT_Msk   (0x1UL << PDM_PSEL_DIN_CONNECT_Pos)

Bit mask of CONNECT field.

◆ PDM_PSEL_DIN_CONNECT_Pos

#define PDM_PSEL_DIN_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ PDM_PSEL_DIN_PIN_Msk

#define PDM_PSEL_DIN_PIN_Msk   (0x1FUL << PDM_PSEL_DIN_PIN_Pos)

Bit mask of PIN field.

◆ PDM_PSEL_DIN_PIN_Pos

#define PDM_PSEL_DIN_PIN_Pos   (0UL)

Position of PIN field.

◆ PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk

#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk   (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos)

Bit mask of BUFFSIZE field.

◆ PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos

#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos   (0UL)

Position of BUFFSIZE field.

◆ PDM_SAMPLE_PTR_SAMPLEPTR_Msk

#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk   (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos)

Bit mask of SAMPLEPTR field.

◆ PDM_SAMPLE_PTR_SAMPLEPTR_Pos

#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos   (0UL)

Position of SAMPLEPTR field.

◆ POWER_DCDCEN_DCDCEN_Disabled

#define POWER_DCDCEN_DCDCEN_Disabled   (0UL)

Disable

◆ POWER_DCDCEN_DCDCEN_Enabled

#define POWER_DCDCEN_DCDCEN_Enabled   (1UL)

Enable

◆ POWER_DCDCEN_DCDCEN_Msk

#define POWER_DCDCEN_DCDCEN_Msk   (0x1UL << POWER_DCDCEN_DCDCEN_Pos)

Bit mask of DCDCEN field.

◆ POWER_DCDCEN_DCDCEN_Pos

#define POWER_DCDCEN_DCDCEN_Pos   (0UL)

Position of DCDCEN field.

◆ POWER_GPREGRET2_GPREGRET_Msk

#define POWER_GPREGRET2_GPREGRET_Msk   (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos)

Bit mask of GPREGRET field.

◆ POWER_GPREGRET2_GPREGRET_Pos

#define POWER_GPREGRET2_GPREGRET_Pos   (0UL)

Position of GPREGRET field.

◆ POWER_GPREGRET_GPREGRET_Msk

#define POWER_GPREGRET_GPREGRET_Msk   (0xFFUL << POWER_GPREGRET_GPREGRET_Pos)

Bit mask of GPREGRET field.

◆ POWER_GPREGRET_GPREGRET_Pos

#define POWER_GPREGRET_GPREGRET_Pos   (0UL)

Position of GPREGRET field.

◆ POWER_INTENCLR_POFWARN_Clear

#define POWER_INTENCLR_POFWARN_Clear   (1UL)

Disable

◆ POWER_INTENCLR_POFWARN_Disabled

#define POWER_INTENCLR_POFWARN_Disabled   (0UL)

Read: Disabled

◆ POWER_INTENCLR_POFWARN_Enabled

#define POWER_INTENCLR_POFWARN_Enabled   (1UL)

Read: Enabled

◆ POWER_INTENCLR_POFWARN_Msk

#define POWER_INTENCLR_POFWARN_Msk   (0x1UL << POWER_INTENCLR_POFWARN_Pos)

Bit mask of POFWARN field.

◆ POWER_INTENCLR_POFWARN_Pos

#define POWER_INTENCLR_POFWARN_Pos   (2UL)

Position of POFWARN field.

◆ POWER_INTENCLR_SLEEPENTER_Clear

#define POWER_INTENCLR_SLEEPENTER_Clear   (1UL)

Disable

◆ POWER_INTENCLR_SLEEPENTER_Disabled

#define POWER_INTENCLR_SLEEPENTER_Disabled   (0UL)

Read: Disabled

◆ POWER_INTENCLR_SLEEPENTER_Enabled

#define POWER_INTENCLR_SLEEPENTER_Enabled   (1UL)

Read: Enabled

◆ POWER_INTENCLR_SLEEPENTER_Msk

#define POWER_INTENCLR_SLEEPENTER_Msk   (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos)

Bit mask of SLEEPENTER field.

◆ POWER_INTENCLR_SLEEPENTER_Pos

#define POWER_INTENCLR_SLEEPENTER_Pos   (5UL)

Position of SLEEPENTER field.

◆ POWER_INTENCLR_SLEEPEXIT_Clear

#define POWER_INTENCLR_SLEEPEXIT_Clear   (1UL)

Disable

◆ POWER_INTENCLR_SLEEPEXIT_Disabled

#define POWER_INTENCLR_SLEEPEXIT_Disabled   (0UL)

Read: Disabled

◆ POWER_INTENCLR_SLEEPEXIT_Enabled

#define POWER_INTENCLR_SLEEPEXIT_Enabled   (1UL)

Read: Enabled

◆ POWER_INTENCLR_SLEEPEXIT_Msk

#define POWER_INTENCLR_SLEEPEXIT_Msk   (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos)

Bit mask of SLEEPEXIT field.

◆ POWER_INTENCLR_SLEEPEXIT_Pos

#define POWER_INTENCLR_SLEEPEXIT_Pos   (6UL)

Position of SLEEPEXIT field.

◆ POWER_INTENSET_POFWARN_Disabled

#define POWER_INTENSET_POFWARN_Disabled   (0UL)

Read: Disabled

◆ POWER_INTENSET_POFWARN_Enabled

#define POWER_INTENSET_POFWARN_Enabled   (1UL)

Read: Enabled

◆ POWER_INTENSET_POFWARN_Msk

#define POWER_INTENSET_POFWARN_Msk   (0x1UL << POWER_INTENSET_POFWARN_Pos)

Bit mask of POFWARN field.

◆ POWER_INTENSET_POFWARN_Pos

#define POWER_INTENSET_POFWARN_Pos   (2UL)

Position of POFWARN field.

◆ POWER_INTENSET_POFWARN_Set

#define POWER_INTENSET_POFWARN_Set   (1UL)

Enable

◆ POWER_INTENSET_SLEEPENTER_Disabled

#define POWER_INTENSET_SLEEPENTER_Disabled   (0UL)

Read: Disabled

◆ POWER_INTENSET_SLEEPENTER_Enabled

#define POWER_INTENSET_SLEEPENTER_Enabled   (1UL)

Read: Enabled

◆ POWER_INTENSET_SLEEPENTER_Msk

#define POWER_INTENSET_SLEEPENTER_Msk   (0x1UL << POWER_INTENSET_SLEEPENTER_Pos)

Bit mask of SLEEPENTER field.

◆ POWER_INTENSET_SLEEPENTER_Pos

#define POWER_INTENSET_SLEEPENTER_Pos   (5UL)

Position of SLEEPENTER field.

◆ POWER_INTENSET_SLEEPENTER_Set

#define POWER_INTENSET_SLEEPENTER_Set   (1UL)

Enable

◆ POWER_INTENSET_SLEEPEXIT_Disabled

#define POWER_INTENSET_SLEEPEXIT_Disabled   (0UL)

Read: Disabled

◆ POWER_INTENSET_SLEEPEXIT_Enabled

#define POWER_INTENSET_SLEEPEXIT_Enabled   (1UL)

Read: Enabled

◆ POWER_INTENSET_SLEEPEXIT_Msk

#define POWER_INTENSET_SLEEPEXIT_Msk   (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos)

Bit mask of SLEEPEXIT field.

◆ POWER_INTENSET_SLEEPEXIT_Pos

#define POWER_INTENSET_SLEEPEXIT_Pos   (6UL)

Position of SLEEPEXIT field.

◆ POWER_INTENSET_SLEEPEXIT_Set

#define POWER_INTENSET_SLEEPEXIT_Set   (1UL)

Enable

◆ POWER_POFCON_POF_Disabled

#define POWER_POFCON_POF_Disabled   (0UL)

Disable

◆ POWER_POFCON_POF_Enabled

#define POWER_POFCON_POF_Enabled   (1UL)

Enable

◆ POWER_POFCON_POF_Msk

#define POWER_POFCON_POF_Msk   (0x1UL << POWER_POFCON_POF_Pos)

Bit mask of POF field.

◆ POWER_POFCON_POF_Pos

#define POWER_POFCON_POF_Pos   (0UL)

Position of POF field.

◆ POWER_POFCON_THRESHOLD_Msk

#define POWER_POFCON_THRESHOLD_Msk   (0xFUL << POWER_POFCON_THRESHOLD_Pos)

Bit mask of THRESHOLD field.

◆ POWER_POFCON_THRESHOLD_Pos

#define POWER_POFCON_THRESHOLD_Pos   (1UL)

Position of THRESHOLD field.

◆ POWER_POFCON_THRESHOLD_V17

#define POWER_POFCON_THRESHOLD_V17   (4UL)

Set threshold to 1.7 V

◆ POWER_POFCON_THRESHOLD_V18

#define POWER_POFCON_THRESHOLD_V18   (5UL)

Set threshold to 1.8 V

◆ POWER_POFCON_THRESHOLD_V19

#define POWER_POFCON_THRESHOLD_V19   (6UL)

Set threshold to 1.9 V

◆ POWER_POFCON_THRESHOLD_V20

#define POWER_POFCON_THRESHOLD_V20   (7UL)

Set threshold to 2.0 V

◆ POWER_POFCON_THRESHOLD_V21

#define POWER_POFCON_THRESHOLD_V21   (8UL)

Set threshold to 2.1 V

◆ POWER_POFCON_THRESHOLD_V22

#define POWER_POFCON_THRESHOLD_V22   (9UL)

Set threshold to 2.2 V

◆ POWER_POFCON_THRESHOLD_V23

#define POWER_POFCON_THRESHOLD_V23   (10UL)

Set threshold to 2.3 V

◆ POWER_POFCON_THRESHOLD_V24

#define POWER_POFCON_THRESHOLD_V24   (11UL)

Set threshold to 2.4 V

◆ POWER_POFCON_THRESHOLD_V25

#define POWER_POFCON_THRESHOLD_V25   (12UL)

Set threshold to 2.5 V

◆ POWER_POFCON_THRESHOLD_V26

#define POWER_POFCON_THRESHOLD_V26   (13UL)

Set threshold to 2.6 V

◆ POWER_POFCON_THRESHOLD_V27

#define POWER_POFCON_THRESHOLD_V27   (14UL)

Set threshold to 2.7 V

◆ POWER_POFCON_THRESHOLD_V28

#define POWER_POFCON_THRESHOLD_V28   (15UL)

Set threshold to 2.8 V

◆ POWER_RAM_POWER_S0POWER_Msk

#define POWER_RAM_POWER_S0POWER_Msk   (0x1UL << POWER_RAM_POWER_S0POWER_Pos)

Bit mask of S0POWER field.

◆ POWER_RAM_POWER_S0POWER_Off

#define POWER_RAM_POWER_S0POWER_Off   (0UL)

Off

◆ POWER_RAM_POWER_S0POWER_On

#define POWER_RAM_POWER_S0POWER_On   (1UL)

On

◆ POWER_RAM_POWER_S0POWER_Pos

#define POWER_RAM_POWER_S0POWER_Pos   (0UL)

Position of S0POWER field.

◆ POWER_RAM_POWER_S0RETENTION_Msk

#define POWER_RAM_POWER_S0RETENTION_Msk   (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos)

Bit mask of S0RETENTION field.

◆ POWER_RAM_POWER_S0RETENTION_Off

#define POWER_RAM_POWER_S0RETENTION_Off   (0UL)

Off

◆ POWER_RAM_POWER_S0RETENTION_On

#define POWER_RAM_POWER_S0RETENTION_On   (1UL)

On

◆ POWER_RAM_POWER_S0RETENTION_Pos

#define POWER_RAM_POWER_S0RETENTION_Pos   (16UL)

Position of S0RETENTION field.

◆ POWER_RAM_POWER_S1POWER_Msk

#define POWER_RAM_POWER_S1POWER_Msk   (0x1UL << POWER_RAM_POWER_S1POWER_Pos)

Bit mask of S1POWER field.

◆ POWER_RAM_POWER_S1POWER_Off

#define POWER_RAM_POWER_S1POWER_Off   (0UL)

Off

◆ POWER_RAM_POWER_S1POWER_On

#define POWER_RAM_POWER_S1POWER_On   (1UL)

On

◆ POWER_RAM_POWER_S1POWER_Pos

#define POWER_RAM_POWER_S1POWER_Pos   (1UL)

Position of S1POWER field.

◆ POWER_RAM_POWER_S1RETENTION_Msk

#define POWER_RAM_POWER_S1RETENTION_Msk   (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos)

Bit mask of S1RETENTION field.

◆ POWER_RAM_POWER_S1RETENTION_Off

#define POWER_RAM_POWER_S1RETENTION_Off   (0UL)

Off

◆ POWER_RAM_POWER_S1RETENTION_On

#define POWER_RAM_POWER_S1RETENTION_On   (1UL)

On

◆ POWER_RAM_POWER_S1RETENTION_Pos

#define POWER_RAM_POWER_S1RETENTION_Pos   (17UL)

Position of S1RETENTION field.

◆ POWER_RAM_POWERCLR_S0POWER_Msk

#define POWER_RAM_POWERCLR_S0POWER_Msk   (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos)

Bit mask of S0POWER field.

◆ POWER_RAM_POWERCLR_S0POWER_Off

#define POWER_RAM_POWERCLR_S0POWER_Off   (1UL)

Off

◆ POWER_RAM_POWERCLR_S0POWER_Pos

#define POWER_RAM_POWERCLR_S0POWER_Pos   (0UL)

Position of S0POWER field.

◆ POWER_RAM_POWERCLR_S0RETENTION_Msk

#define POWER_RAM_POWERCLR_S0RETENTION_Msk   (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos)

Bit mask of S0RETENTION field.

◆ POWER_RAM_POWERCLR_S0RETENTION_Off

#define POWER_RAM_POWERCLR_S0RETENTION_Off   (1UL)

Off

◆ POWER_RAM_POWERCLR_S0RETENTION_Pos

#define POWER_RAM_POWERCLR_S0RETENTION_Pos   (16UL)

Position of S0RETENTION field.

◆ POWER_RAM_POWERCLR_S1POWER_Msk

#define POWER_RAM_POWERCLR_S1POWER_Msk   (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos)

Bit mask of S1POWER field.

◆ POWER_RAM_POWERCLR_S1POWER_Off

#define POWER_RAM_POWERCLR_S1POWER_Off   (1UL)

Off

◆ POWER_RAM_POWERCLR_S1POWER_Pos

#define POWER_RAM_POWERCLR_S1POWER_Pos   (1UL)

Position of S1POWER field.

◆ POWER_RAM_POWERCLR_S1RETENTION_Msk

#define POWER_RAM_POWERCLR_S1RETENTION_Msk   (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos)

Bit mask of S1RETENTION field.

◆ POWER_RAM_POWERCLR_S1RETENTION_Off

#define POWER_RAM_POWERCLR_S1RETENTION_Off   (1UL)

Off

◆ POWER_RAM_POWERCLR_S1RETENTION_Pos

#define POWER_RAM_POWERCLR_S1RETENTION_Pos   (17UL)

Position of S1RETENTION field.

◆ POWER_RAM_POWERSET_S0POWER_Msk

#define POWER_RAM_POWERSET_S0POWER_Msk   (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos)

Bit mask of S0POWER field.

◆ POWER_RAM_POWERSET_S0POWER_On

#define POWER_RAM_POWERSET_S0POWER_On   (1UL)

On

◆ POWER_RAM_POWERSET_S0POWER_Pos

#define POWER_RAM_POWERSET_S0POWER_Pos   (0UL)

Position of S0POWER field.

◆ POWER_RAM_POWERSET_S0RETENTION_Msk

#define POWER_RAM_POWERSET_S0RETENTION_Msk   (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos)

Bit mask of S0RETENTION field.

◆ POWER_RAM_POWERSET_S0RETENTION_On

#define POWER_RAM_POWERSET_S0RETENTION_On   (1UL)

On

◆ POWER_RAM_POWERSET_S0RETENTION_Pos

#define POWER_RAM_POWERSET_S0RETENTION_Pos   (16UL)

Position of S0RETENTION field.

◆ POWER_RAM_POWERSET_S1POWER_Msk

#define POWER_RAM_POWERSET_S1POWER_Msk   (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos)

Bit mask of S1POWER field.

◆ POWER_RAM_POWERSET_S1POWER_On

#define POWER_RAM_POWERSET_S1POWER_On   (1UL)

On

◆ POWER_RAM_POWERSET_S1POWER_Pos

#define POWER_RAM_POWERSET_S1POWER_Pos   (1UL)

Position of S1POWER field.

◆ POWER_RAM_POWERSET_S1RETENTION_Msk

#define POWER_RAM_POWERSET_S1RETENTION_Msk   (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos)

Bit mask of S1RETENTION field.

◆ POWER_RAM_POWERSET_S1RETENTION_On

#define POWER_RAM_POWERSET_S1RETENTION_On   (1UL)

On

◆ POWER_RAM_POWERSET_S1RETENTION_Pos

#define POWER_RAM_POWERSET_S1RETENTION_Pos   (17UL)

Position of S1RETENTION field.

◆ POWER_RAMON_OFFRAM0_Msk

#define POWER_RAMON_OFFRAM0_Msk   (0x1UL << POWER_RAMON_OFFRAM0_Pos)

Bit mask of OFFRAM0 field.

◆ POWER_RAMON_OFFRAM0_Pos

#define POWER_RAMON_OFFRAM0_Pos   (16UL)

Position of OFFRAM0 field.

◆ POWER_RAMON_OFFRAM0_RAM0Off

#define POWER_RAMON_OFFRAM0_RAM0Off   (0UL)

Off

◆ POWER_RAMON_OFFRAM0_RAM0On

#define POWER_RAMON_OFFRAM0_RAM0On   (1UL)

On

◆ POWER_RAMON_OFFRAM1_Msk

#define POWER_RAMON_OFFRAM1_Msk   (0x1UL << POWER_RAMON_OFFRAM1_Pos)

Bit mask of OFFRAM1 field.

◆ POWER_RAMON_OFFRAM1_Pos

#define POWER_RAMON_OFFRAM1_Pos   (17UL)

Position of OFFRAM1 field.

◆ POWER_RAMON_OFFRAM1_RAM1Off

#define POWER_RAMON_OFFRAM1_RAM1Off   (0UL)

Off

◆ POWER_RAMON_OFFRAM1_RAM1On

#define POWER_RAMON_OFFRAM1_RAM1On   (1UL)

On

◆ POWER_RAMON_ONRAM0_Msk

#define POWER_RAMON_ONRAM0_Msk   (0x1UL << POWER_RAMON_ONRAM0_Pos)

Bit mask of ONRAM0 field.

◆ POWER_RAMON_ONRAM0_Pos

#define POWER_RAMON_ONRAM0_Pos   (0UL)

Position of ONRAM0 field.

◆ POWER_RAMON_ONRAM0_RAM0Off

#define POWER_RAMON_ONRAM0_RAM0Off   (0UL)

Off

◆ POWER_RAMON_ONRAM0_RAM0On

#define POWER_RAMON_ONRAM0_RAM0On   (1UL)

On

◆ POWER_RAMON_ONRAM1_Msk

#define POWER_RAMON_ONRAM1_Msk   (0x1UL << POWER_RAMON_ONRAM1_Pos)

Bit mask of ONRAM1 field.

◆ POWER_RAMON_ONRAM1_Pos

#define POWER_RAMON_ONRAM1_Pos   (1UL)

Position of ONRAM1 field.

◆ POWER_RAMON_ONRAM1_RAM1Off

#define POWER_RAMON_ONRAM1_RAM1Off   (0UL)

Off

◆ POWER_RAMON_ONRAM1_RAM1On

#define POWER_RAMON_ONRAM1_RAM1On   (1UL)

On

◆ POWER_RAMONB_OFFRAM2_Msk

#define POWER_RAMONB_OFFRAM2_Msk   (0x1UL << POWER_RAMONB_OFFRAM2_Pos)

Bit mask of OFFRAM2 field.

◆ POWER_RAMONB_OFFRAM2_Pos

#define POWER_RAMONB_OFFRAM2_Pos   (16UL)

Position of OFFRAM2 field.

◆ POWER_RAMONB_OFFRAM2_RAM2Off

#define POWER_RAMONB_OFFRAM2_RAM2Off   (0UL)

Off

◆ POWER_RAMONB_OFFRAM2_RAM2On

#define POWER_RAMONB_OFFRAM2_RAM2On   (1UL)

On

◆ POWER_RAMONB_OFFRAM3_Msk

#define POWER_RAMONB_OFFRAM3_Msk   (0x1UL << POWER_RAMONB_OFFRAM3_Pos)

Bit mask of OFFRAM3 field.

◆ POWER_RAMONB_OFFRAM3_Pos

#define POWER_RAMONB_OFFRAM3_Pos   (17UL)

Position of OFFRAM3 field.

◆ POWER_RAMONB_OFFRAM3_RAM3Off

#define POWER_RAMONB_OFFRAM3_RAM3Off   (0UL)

Off

◆ POWER_RAMONB_OFFRAM3_RAM3On

#define POWER_RAMONB_OFFRAM3_RAM3On   (1UL)

On

◆ POWER_RAMONB_ONRAM2_Msk

#define POWER_RAMONB_ONRAM2_Msk   (0x1UL << POWER_RAMONB_ONRAM2_Pos)

Bit mask of ONRAM2 field.

◆ POWER_RAMONB_ONRAM2_Pos

#define POWER_RAMONB_ONRAM2_Pos   (0UL)

Position of ONRAM2 field.

◆ POWER_RAMONB_ONRAM2_RAM2Off

#define POWER_RAMONB_ONRAM2_RAM2Off   (0UL)

Off

◆ POWER_RAMONB_ONRAM2_RAM2On

#define POWER_RAMONB_ONRAM2_RAM2On   (1UL)

On

◆ POWER_RAMONB_ONRAM3_Msk

#define POWER_RAMONB_ONRAM3_Msk   (0x1UL << POWER_RAMONB_ONRAM3_Pos)

Bit mask of ONRAM3 field.

◆ POWER_RAMONB_ONRAM3_Pos

#define POWER_RAMONB_ONRAM3_Pos   (1UL)

Position of ONRAM3 field.

◆ POWER_RAMONB_ONRAM3_RAM3Off

#define POWER_RAMONB_ONRAM3_RAM3Off   (0UL)

Off

◆ POWER_RAMONB_ONRAM3_RAM3On

#define POWER_RAMONB_ONRAM3_RAM3On   (1UL)

On

◆ POWER_RAMSTATUS_RAMBLOCK0_Msk

#define POWER_RAMSTATUS_RAMBLOCK0_Msk   (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos)

Bit mask of RAMBLOCK0 field.

◆ POWER_RAMSTATUS_RAMBLOCK0_Off

#define POWER_RAMSTATUS_RAMBLOCK0_Off   (0UL)

Off

◆ POWER_RAMSTATUS_RAMBLOCK0_On

#define POWER_RAMSTATUS_RAMBLOCK0_On   (1UL)

On

◆ POWER_RAMSTATUS_RAMBLOCK0_Pos

#define POWER_RAMSTATUS_RAMBLOCK0_Pos   (0UL)

Position of RAMBLOCK0 field.

◆ POWER_RAMSTATUS_RAMBLOCK1_Msk

#define POWER_RAMSTATUS_RAMBLOCK1_Msk   (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos)

Bit mask of RAMBLOCK1 field.

◆ POWER_RAMSTATUS_RAMBLOCK1_Off

#define POWER_RAMSTATUS_RAMBLOCK1_Off   (0UL)

Off

◆ POWER_RAMSTATUS_RAMBLOCK1_On

#define POWER_RAMSTATUS_RAMBLOCK1_On   (1UL)

On

◆ POWER_RAMSTATUS_RAMBLOCK1_Pos

#define POWER_RAMSTATUS_RAMBLOCK1_Pos   (1UL)

Position of RAMBLOCK1 field.

◆ POWER_RAMSTATUS_RAMBLOCK2_Msk

#define POWER_RAMSTATUS_RAMBLOCK2_Msk   (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos)

Bit mask of RAMBLOCK2 field.

◆ POWER_RAMSTATUS_RAMBLOCK2_Off

#define POWER_RAMSTATUS_RAMBLOCK2_Off   (0UL)

Off

◆ POWER_RAMSTATUS_RAMBLOCK2_On

#define POWER_RAMSTATUS_RAMBLOCK2_On   (1UL)

On

◆ POWER_RAMSTATUS_RAMBLOCK2_Pos

#define POWER_RAMSTATUS_RAMBLOCK2_Pos   (2UL)

Position of RAMBLOCK2 field.

◆ POWER_RAMSTATUS_RAMBLOCK3_Msk

#define POWER_RAMSTATUS_RAMBLOCK3_Msk   (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos)

Bit mask of RAMBLOCK3 field.

◆ POWER_RAMSTATUS_RAMBLOCK3_Off

#define POWER_RAMSTATUS_RAMBLOCK3_Off   (0UL)

Off

◆ POWER_RAMSTATUS_RAMBLOCK3_On

#define POWER_RAMSTATUS_RAMBLOCK3_On   (1UL)

On

◆ POWER_RAMSTATUS_RAMBLOCK3_Pos

#define POWER_RAMSTATUS_RAMBLOCK3_Pos   (3UL)

Position of RAMBLOCK3 field.

◆ POWER_RESETREAS_DIF_Detected

#define POWER_RESETREAS_DIF_Detected   (1UL)

Detected

◆ POWER_RESETREAS_DIF_Msk

#define POWER_RESETREAS_DIF_Msk   (0x1UL << POWER_RESETREAS_DIF_Pos)

Bit mask of DIF field.

◆ POWER_RESETREAS_DIF_NotDetected

#define POWER_RESETREAS_DIF_NotDetected   (0UL)

Not detected

◆ POWER_RESETREAS_DIF_Pos

#define POWER_RESETREAS_DIF_Pos   (18UL)

Position of DIF field.

◆ POWER_RESETREAS_DOG_Detected

#define POWER_RESETREAS_DOG_Detected   (1UL)

Detected

◆ POWER_RESETREAS_DOG_Msk

#define POWER_RESETREAS_DOG_Msk   (0x1UL << POWER_RESETREAS_DOG_Pos)

Bit mask of DOG field.

◆ POWER_RESETREAS_DOG_NotDetected

#define POWER_RESETREAS_DOG_NotDetected   (0UL)

Not detected

◆ POWER_RESETREAS_DOG_Pos

#define POWER_RESETREAS_DOG_Pos   (1UL)

Position of DOG field.

◆ POWER_RESETREAS_LOCKUP_Detected

#define POWER_RESETREAS_LOCKUP_Detected   (1UL)

Detected

◆ POWER_RESETREAS_LOCKUP_Msk

#define POWER_RESETREAS_LOCKUP_Msk   (0x1UL << POWER_RESETREAS_LOCKUP_Pos)

Bit mask of LOCKUP field.

◆ POWER_RESETREAS_LOCKUP_NotDetected

#define POWER_RESETREAS_LOCKUP_NotDetected   (0UL)

Not detected

◆ POWER_RESETREAS_LOCKUP_Pos

#define POWER_RESETREAS_LOCKUP_Pos   (3UL)

Position of LOCKUP field.

◆ POWER_RESETREAS_LPCOMP_Detected

#define POWER_RESETREAS_LPCOMP_Detected   (1UL)

Detected

◆ POWER_RESETREAS_LPCOMP_Msk

#define POWER_RESETREAS_LPCOMP_Msk   (0x1UL << POWER_RESETREAS_LPCOMP_Pos)

Bit mask of LPCOMP field.

◆ POWER_RESETREAS_LPCOMP_NotDetected

#define POWER_RESETREAS_LPCOMP_NotDetected   (0UL)

Not detected

◆ POWER_RESETREAS_LPCOMP_Pos

#define POWER_RESETREAS_LPCOMP_Pos   (17UL)

Position of LPCOMP field.

◆ POWER_RESETREAS_NFC_Detected

#define POWER_RESETREAS_NFC_Detected   (1UL)

Detected

◆ POWER_RESETREAS_NFC_Msk

#define POWER_RESETREAS_NFC_Msk   (0x1UL << POWER_RESETREAS_NFC_Pos)

Bit mask of NFC field.

◆ POWER_RESETREAS_NFC_NotDetected

#define POWER_RESETREAS_NFC_NotDetected   (0UL)

Not detected

◆ POWER_RESETREAS_NFC_Pos

#define POWER_RESETREAS_NFC_Pos   (19UL)

Position of NFC field.

◆ POWER_RESETREAS_OFF_Detected

#define POWER_RESETREAS_OFF_Detected   (1UL)

Detected

◆ POWER_RESETREAS_OFF_Msk

#define POWER_RESETREAS_OFF_Msk   (0x1UL << POWER_RESETREAS_OFF_Pos)

Bit mask of OFF field.

◆ POWER_RESETREAS_OFF_NotDetected

#define POWER_RESETREAS_OFF_NotDetected   (0UL)

Not detected

◆ POWER_RESETREAS_OFF_Pos

#define POWER_RESETREAS_OFF_Pos   (16UL)

Position of OFF field.

◆ POWER_RESETREAS_RESETPIN_Detected

#define POWER_RESETREAS_RESETPIN_Detected   (1UL)

Detected

◆ POWER_RESETREAS_RESETPIN_Msk

#define POWER_RESETREAS_RESETPIN_Msk   (0x1UL << POWER_RESETREAS_RESETPIN_Pos)

Bit mask of RESETPIN field.

◆ POWER_RESETREAS_RESETPIN_NotDetected

#define POWER_RESETREAS_RESETPIN_NotDetected   (0UL)

Not detected

◆ POWER_RESETREAS_RESETPIN_Pos

#define POWER_RESETREAS_RESETPIN_Pos   (0UL)

Position of RESETPIN field.

◆ POWER_RESETREAS_SREQ_Detected

#define POWER_RESETREAS_SREQ_Detected   (1UL)

Detected

◆ POWER_RESETREAS_SREQ_Msk

#define POWER_RESETREAS_SREQ_Msk   (0x1UL << POWER_RESETREAS_SREQ_Pos)

Bit mask of SREQ field.

◆ POWER_RESETREAS_SREQ_NotDetected

#define POWER_RESETREAS_SREQ_NotDetected   (0UL)

Not detected

◆ POWER_RESETREAS_SREQ_Pos

#define POWER_RESETREAS_SREQ_Pos   (2UL)

Position of SREQ field.

◆ POWER_SYSTEMOFF_SYSTEMOFF_Enter

#define POWER_SYSTEMOFF_SYSTEMOFF_Enter   (1UL)

Enable System OFF mode

◆ POWER_SYSTEMOFF_SYSTEMOFF_Msk

#define POWER_SYSTEMOFF_SYSTEMOFF_Msk   (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos)

Bit mask of SYSTEMOFF field.

◆ POWER_SYSTEMOFF_SYSTEMOFF_Pos

#define POWER_SYSTEMOFF_SYSTEMOFF_Pos   (0UL)

Position of SYSTEMOFF field.

◆ PPI_CH_EEP_EEP_Msk

#define PPI_CH_EEP_EEP_Msk   (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos)

Bit mask of EEP field.

◆ PPI_CH_EEP_EEP_Pos

#define PPI_CH_EEP_EEP_Pos   (0UL)

Position of EEP field.

◆ PPI_CH_TEP_TEP_Msk

#define PPI_CH_TEP_TEP_Msk   (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos)

Bit mask of TEP field.

◆ PPI_CH_TEP_TEP_Pos

#define PPI_CH_TEP_TEP_Pos   (0UL)

Position of TEP field.

◆ PPI_CHEN_CH0_Disabled

#define PPI_CHEN_CH0_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH0_Enabled

#define PPI_CHEN_CH0_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH0_Msk

#define PPI_CHEN_CH0_Msk   (0x1UL << PPI_CHEN_CH0_Pos)

Bit mask of CH0 field.

◆ PPI_CHEN_CH0_Pos

#define PPI_CHEN_CH0_Pos   (0UL)

Position of CH0 field.

◆ PPI_CHEN_CH10_Disabled

#define PPI_CHEN_CH10_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH10_Enabled

#define PPI_CHEN_CH10_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH10_Msk

#define PPI_CHEN_CH10_Msk   (0x1UL << PPI_CHEN_CH10_Pos)

Bit mask of CH10 field.

◆ PPI_CHEN_CH10_Pos

#define PPI_CHEN_CH10_Pos   (10UL)

Position of CH10 field.

◆ PPI_CHEN_CH11_Disabled

#define PPI_CHEN_CH11_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH11_Enabled

#define PPI_CHEN_CH11_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH11_Msk

#define PPI_CHEN_CH11_Msk   (0x1UL << PPI_CHEN_CH11_Pos)

Bit mask of CH11 field.

◆ PPI_CHEN_CH11_Pos

#define PPI_CHEN_CH11_Pos   (11UL)

Position of CH11 field.

◆ PPI_CHEN_CH12_Disabled

#define PPI_CHEN_CH12_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH12_Enabled

#define PPI_CHEN_CH12_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH12_Msk

#define PPI_CHEN_CH12_Msk   (0x1UL << PPI_CHEN_CH12_Pos)

Bit mask of CH12 field.

◆ PPI_CHEN_CH12_Pos

#define PPI_CHEN_CH12_Pos   (12UL)

Position of CH12 field.

◆ PPI_CHEN_CH13_Disabled

#define PPI_CHEN_CH13_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH13_Enabled

#define PPI_CHEN_CH13_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH13_Msk

#define PPI_CHEN_CH13_Msk   (0x1UL << PPI_CHEN_CH13_Pos)

Bit mask of CH13 field.

◆ PPI_CHEN_CH13_Pos

#define PPI_CHEN_CH13_Pos   (13UL)

Position of CH13 field.

◆ PPI_CHEN_CH14_Disabled

#define PPI_CHEN_CH14_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH14_Enabled

#define PPI_CHEN_CH14_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH14_Msk

#define PPI_CHEN_CH14_Msk   (0x1UL << PPI_CHEN_CH14_Pos)

Bit mask of CH14 field.

◆ PPI_CHEN_CH14_Pos

#define PPI_CHEN_CH14_Pos   (14UL)

Position of CH14 field.

◆ PPI_CHEN_CH15_Disabled

#define PPI_CHEN_CH15_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH15_Enabled

#define PPI_CHEN_CH15_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH15_Msk

#define PPI_CHEN_CH15_Msk   (0x1UL << PPI_CHEN_CH15_Pos)

Bit mask of CH15 field.

◆ PPI_CHEN_CH15_Pos

#define PPI_CHEN_CH15_Pos   (15UL)

Position of CH15 field.

◆ PPI_CHEN_CH16_Disabled

#define PPI_CHEN_CH16_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH16_Enabled

#define PPI_CHEN_CH16_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH16_Msk

#define PPI_CHEN_CH16_Msk   (0x1UL << PPI_CHEN_CH16_Pos)

Bit mask of CH16 field.

◆ PPI_CHEN_CH16_Pos

#define PPI_CHEN_CH16_Pos   (16UL)

Position of CH16 field.

◆ PPI_CHEN_CH17_Disabled

#define PPI_CHEN_CH17_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH17_Enabled

#define PPI_CHEN_CH17_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH17_Msk

#define PPI_CHEN_CH17_Msk   (0x1UL << PPI_CHEN_CH17_Pos)

Bit mask of CH17 field.

◆ PPI_CHEN_CH17_Pos

#define PPI_CHEN_CH17_Pos   (17UL)

Position of CH17 field.

◆ PPI_CHEN_CH18_Disabled

#define PPI_CHEN_CH18_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH18_Enabled

#define PPI_CHEN_CH18_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH18_Msk

#define PPI_CHEN_CH18_Msk   (0x1UL << PPI_CHEN_CH18_Pos)

Bit mask of CH18 field.

◆ PPI_CHEN_CH18_Pos

#define PPI_CHEN_CH18_Pos   (18UL)

Position of CH18 field.

◆ PPI_CHEN_CH19_Disabled

#define PPI_CHEN_CH19_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH19_Enabled

#define PPI_CHEN_CH19_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH19_Msk

#define PPI_CHEN_CH19_Msk   (0x1UL << PPI_CHEN_CH19_Pos)

Bit mask of CH19 field.

◆ PPI_CHEN_CH19_Pos

#define PPI_CHEN_CH19_Pos   (19UL)

Position of CH19 field.

◆ PPI_CHEN_CH1_Disabled

#define PPI_CHEN_CH1_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH1_Enabled

#define PPI_CHEN_CH1_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH1_Msk

#define PPI_CHEN_CH1_Msk   (0x1UL << PPI_CHEN_CH1_Pos)

Bit mask of CH1 field.

◆ PPI_CHEN_CH1_Pos

#define PPI_CHEN_CH1_Pos   (1UL)

Position of CH1 field.

◆ PPI_CHEN_CH20_Disabled

#define PPI_CHEN_CH20_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH20_Enabled

#define PPI_CHEN_CH20_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH20_Msk

#define PPI_CHEN_CH20_Msk   (0x1UL << PPI_CHEN_CH20_Pos)

Bit mask of CH20 field.

◆ PPI_CHEN_CH20_Pos

#define PPI_CHEN_CH20_Pos   (20UL)

Position of CH20 field.

◆ PPI_CHEN_CH21_Disabled

#define PPI_CHEN_CH21_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH21_Enabled

#define PPI_CHEN_CH21_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH21_Msk

#define PPI_CHEN_CH21_Msk   (0x1UL << PPI_CHEN_CH21_Pos)

Bit mask of CH21 field.

◆ PPI_CHEN_CH21_Pos

#define PPI_CHEN_CH21_Pos   (21UL)

Position of CH21 field.

◆ PPI_CHEN_CH22_Disabled

#define PPI_CHEN_CH22_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH22_Enabled

#define PPI_CHEN_CH22_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH22_Msk

#define PPI_CHEN_CH22_Msk   (0x1UL << PPI_CHEN_CH22_Pos)

Bit mask of CH22 field.

◆ PPI_CHEN_CH22_Pos

#define PPI_CHEN_CH22_Pos   (22UL)

Position of CH22 field.

◆ PPI_CHEN_CH23_Disabled

#define PPI_CHEN_CH23_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH23_Enabled

#define PPI_CHEN_CH23_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH23_Msk

#define PPI_CHEN_CH23_Msk   (0x1UL << PPI_CHEN_CH23_Pos)

Bit mask of CH23 field.

◆ PPI_CHEN_CH23_Pos

#define PPI_CHEN_CH23_Pos   (23UL)

Position of CH23 field.

◆ PPI_CHEN_CH24_Disabled

#define PPI_CHEN_CH24_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH24_Enabled

#define PPI_CHEN_CH24_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH24_Msk

#define PPI_CHEN_CH24_Msk   (0x1UL << PPI_CHEN_CH24_Pos)

Bit mask of CH24 field.

◆ PPI_CHEN_CH24_Pos

#define PPI_CHEN_CH24_Pos   (24UL)

Position of CH24 field.

◆ PPI_CHEN_CH25_Disabled

#define PPI_CHEN_CH25_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH25_Enabled

#define PPI_CHEN_CH25_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH25_Msk

#define PPI_CHEN_CH25_Msk   (0x1UL << PPI_CHEN_CH25_Pos)

Bit mask of CH25 field.

◆ PPI_CHEN_CH25_Pos

#define PPI_CHEN_CH25_Pos   (25UL)

Position of CH25 field.

◆ PPI_CHEN_CH26_Disabled

#define PPI_CHEN_CH26_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH26_Enabled

#define PPI_CHEN_CH26_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH26_Msk

#define PPI_CHEN_CH26_Msk   (0x1UL << PPI_CHEN_CH26_Pos)

Bit mask of CH26 field.

◆ PPI_CHEN_CH26_Pos

#define PPI_CHEN_CH26_Pos   (26UL)

Position of CH26 field.

◆ PPI_CHEN_CH27_Disabled

#define PPI_CHEN_CH27_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH27_Enabled

#define PPI_CHEN_CH27_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH27_Msk

#define PPI_CHEN_CH27_Msk   (0x1UL << PPI_CHEN_CH27_Pos)

Bit mask of CH27 field.

◆ PPI_CHEN_CH27_Pos

#define PPI_CHEN_CH27_Pos   (27UL)

Position of CH27 field.

◆ PPI_CHEN_CH28_Disabled

#define PPI_CHEN_CH28_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH28_Enabled

#define PPI_CHEN_CH28_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH28_Msk

#define PPI_CHEN_CH28_Msk   (0x1UL << PPI_CHEN_CH28_Pos)

Bit mask of CH28 field.

◆ PPI_CHEN_CH28_Pos

#define PPI_CHEN_CH28_Pos   (28UL)

Position of CH28 field.

◆ PPI_CHEN_CH29_Disabled

#define PPI_CHEN_CH29_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH29_Enabled

#define PPI_CHEN_CH29_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH29_Msk

#define PPI_CHEN_CH29_Msk   (0x1UL << PPI_CHEN_CH29_Pos)

Bit mask of CH29 field.

◆ PPI_CHEN_CH29_Pos

#define PPI_CHEN_CH29_Pos   (29UL)

Position of CH29 field.

◆ PPI_CHEN_CH2_Disabled

#define PPI_CHEN_CH2_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH2_Enabled

#define PPI_CHEN_CH2_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH2_Msk

#define PPI_CHEN_CH2_Msk   (0x1UL << PPI_CHEN_CH2_Pos)

Bit mask of CH2 field.

◆ PPI_CHEN_CH2_Pos

#define PPI_CHEN_CH2_Pos   (2UL)

Position of CH2 field.

◆ PPI_CHEN_CH30_Disabled

#define PPI_CHEN_CH30_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH30_Enabled

#define PPI_CHEN_CH30_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH30_Msk

#define PPI_CHEN_CH30_Msk   (0x1UL << PPI_CHEN_CH30_Pos)

Bit mask of CH30 field.

◆ PPI_CHEN_CH30_Pos

#define PPI_CHEN_CH30_Pos   (30UL)

Position of CH30 field.

◆ PPI_CHEN_CH31_Disabled

#define PPI_CHEN_CH31_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH31_Enabled

#define PPI_CHEN_CH31_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH31_Msk

#define PPI_CHEN_CH31_Msk   (0x1UL << PPI_CHEN_CH31_Pos)

Bit mask of CH31 field.

◆ PPI_CHEN_CH31_Pos

#define PPI_CHEN_CH31_Pos   (31UL)

Position of CH31 field.

◆ PPI_CHEN_CH3_Disabled

#define PPI_CHEN_CH3_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH3_Enabled

#define PPI_CHEN_CH3_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH3_Msk

#define PPI_CHEN_CH3_Msk   (0x1UL << PPI_CHEN_CH3_Pos)

Bit mask of CH3 field.

◆ PPI_CHEN_CH3_Pos

#define PPI_CHEN_CH3_Pos   (3UL)

Position of CH3 field.

◆ PPI_CHEN_CH4_Disabled

#define PPI_CHEN_CH4_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH4_Enabled

#define PPI_CHEN_CH4_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH4_Msk

#define PPI_CHEN_CH4_Msk   (0x1UL << PPI_CHEN_CH4_Pos)

Bit mask of CH4 field.

◆ PPI_CHEN_CH4_Pos

#define PPI_CHEN_CH4_Pos   (4UL)

Position of CH4 field.

◆ PPI_CHEN_CH5_Disabled

#define PPI_CHEN_CH5_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH5_Enabled

#define PPI_CHEN_CH5_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH5_Msk

#define PPI_CHEN_CH5_Msk   (0x1UL << PPI_CHEN_CH5_Pos)

Bit mask of CH5 field.

◆ PPI_CHEN_CH5_Pos

#define PPI_CHEN_CH5_Pos   (5UL)

Position of CH5 field.

◆ PPI_CHEN_CH6_Disabled

#define PPI_CHEN_CH6_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH6_Enabled

#define PPI_CHEN_CH6_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH6_Msk

#define PPI_CHEN_CH6_Msk   (0x1UL << PPI_CHEN_CH6_Pos)

Bit mask of CH6 field.

◆ PPI_CHEN_CH6_Pos

#define PPI_CHEN_CH6_Pos   (6UL)

Position of CH6 field.

◆ PPI_CHEN_CH7_Disabled

#define PPI_CHEN_CH7_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH7_Enabled

#define PPI_CHEN_CH7_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH7_Msk

#define PPI_CHEN_CH7_Msk   (0x1UL << PPI_CHEN_CH7_Pos)

Bit mask of CH7 field.

◆ PPI_CHEN_CH7_Pos

#define PPI_CHEN_CH7_Pos   (7UL)

Position of CH7 field.

◆ PPI_CHEN_CH8_Disabled

#define PPI_CHEN_CH8_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH8_Enabled

#define PPI_CHEN_CH8_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH8_Msk

#define PPI_CHEN_CH8_Msk   (0x1UL << PPI_CHEN_CH8_Pos)

Bit mask of CH8 field.

◆ PPI_CHEN_CH8_Pos

#define PPI_CHEN_CH8_Pos   (8UL)

Position of CH8 field.

◆ PPI_CHEN_CH9_Disabled

#define PPI_CHEN_CH9_Disabled   (0UL)

Disable channel

◆ PPI_CHEN_CH9_Enabled

#define PPI_CHEN_CH9_Enabled   (1UL)

Enable channel

◆ PPI_CHEN_CH9_Msk

#define PPI_CHEN_CH9_Msk   (0x1UL << PPI_CHEN_CH9_Pos)

Bit mask of CH9 field.

◆ PPI_CHEN_CH9_Pos

#define PPI_CHEN_CH9_Pos   (9UL)

Position of CH9 field.

◆ PPI_CHENCLR_CH0_Clear

#define PPI_CHENCLR_CH0_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH0_Disabled

#define PPI_CHENCLR_CH0_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH0_Enabled

#define PPI_CHENCLR_CH0_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH0_Msk

#define PPI_CHENCLR_CH0_Msk   (0x1UL << PPI_CHENCLR_CH0_Pos)

Bit mask of CH0 field.

◆ PPI_CHENCLR_CH0_Pos

#define PPI_CHENCLR_CH0_Pos   (0UL)

Position of CH0 field.

◆ PPI_CHENCLR_CH10_Clear

#define PPI_CHENCLR_CH10_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH10_Disabled

#define PPI_CHENCLR_CH10_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH10_Enabled

#define PPI_CHENCLR_CH10_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH10_Msk

#define PPI_CHENCLR_CH10_Msk   (0x1UL << PPI_CHENCLR_CH10_Pos)

Bit mask of CH10 field.

◆ PPI_CHENCLR_CH10_Pos

#define PPI_CHENCLR_CH10_Pos   (10UL)

Position of CH10 field.

◆ PPI_CHENCLR_CH11_Clear

#define PPI_CHENCLR_CH11_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH11_Disabled

#define PPI_CHENCLR_CH11_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH11_Enabled

#define PPI_CHENCLR_CH11_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH11_Msk

#define PPI_CHENCLR_CH11_Msk   (0x1UL << PPI_CHENCLR_CH11_Pos)

Bit mask of CH11 field.

◆ PPI_CHENCLR_CH11_Pos

#define PPI_CHENCLR_CH11_Pos   (11UL)

Position of CH11 field.

◆ PPI_CHENCLR_CH12_Clear

#define PPI_CHENCLR_CH12_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH12_Disabled

#define PPI_CHENCLR_CH12_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH12_Enabled

#define PPI_CHENCLR_CH12_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH12_Msk

#define PPI_CHENCLR_CH12_Msk   (0x1UL << PPI_CHENCLR_CH12_Pos)

Bit mask of CH12 field.

◆ PPI_CHENCLR_CH12_Pos

#define PPI_CHENCLR_CH12_Pos   (12UL)

Position of CH12 field.

◆ PPI_CHENCLR_CH13_Clear

#define PPI_CHENCLR_CH13_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH13_Disabled

#define PPI_CHENCLR_CH13_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH13_Enabled

#define PPI_CHENCLR_CH13_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH13_Msk

#define PPI_CHENCLR_CH13_Msk   (0x1UL << PPI_CHENCLR_CH13_Pos)

Bit mask of CH13 field.

◆ PPI_CHENCLR_CH13_Pos

#define PPI_CHENCLR_CH13_Pos   (13UL)

Position of CH13 field.

◆ PPI_CHENCLR_CH14_Clear

#define PPI_CHENCLR_CH14_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH14_Disabled

#define PPI_CHENCLR_CH14_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH14_Enabled

#define PPI_CHENCLR_CH14_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH14_Msk

#define PPI_CHENCLR_CH14_Msk   (0x1UL << PPI_CHENCLR_CH14_Pos)

Bit mask of CH14 field.

◆ PPI_CHENCLR_CH14_Pos

#define PPI_CHENCLR_CH14_Pos   (14UL)

Position of CH14 field.

◆ PPI_CHENCLR_CH15_Clear

#define PPI_CHENCLR_CH15_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH15_Disabled

#define PPI_CHENCLR_CH15_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH15_Enabled

#define PPI_CHENCLR_CH15_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH15_Msk

#define PPI_CHENCLR_CH15_Msk   (0x1UL << PPI_CHENCLR_CH15_Pos)

Bit mask of CH15 field.

◆ PPI_CHENCLR_CH15_Pos

#define PPI_CHENCLR_CH15_Pos   (15UL)

Position of CH15 field.

◆ PPI_CHENCLR_CH16_Clear

#define PPI_CHENCLR_CH16_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH16_Disabled

#define PPI_CHENCLR_CH16_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH16_Enabled

#define PPI_CHENCLR_CH16_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH16_Msk

#define PPI_CHENCLR_CH16_Msk   (0x1UL << PPI_CHENCLR_CH16_Pos)

Bit mask of CH16 field.

◆ PPI_CHENCLR_CH16_Pos

#define PPI_CHENCLR_CH16_Pos   (16UL)

Position of CH16 field.

◆ PPI_CHENCLR_CH17_Clear

#define PPI_CHENCLR_CH17_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH17_Disabled

#define PPI_CHENCLR_CH17_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH17_Enabled

#define PPI_CHENCLR_CH17_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH17_Msk

#define PPI_CHENCLR_CH17_Msk   (0x1UL << PPI_CHENCLR_CH17_Pos)

Bit mask of CH17 field.

◆ PPI_CHENCLR_CH17_Pos

#define PPI_CHENCLR_CH17_Pos   (17UL)

Position of CH17 field.

◆ PPI_CHENCLR_CH18_Clear

#define PPI_CHENCLR_CH18_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH18_Disabled

#define PPI_CHENCLR_CH18_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH18_Enabled

#define PPI_CHENCLR_CH18_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH18_Msk

#define PPI_CHENCLR_CH18_Msk   (0x1UL << PPI_CHENCLR_CH18_Pos)

Bit mask of CH18 field.

◆ PPI_CHENCLR_CH18_Pos

#define PPI_CHENCLR_CH18_Pos   (18UL)

Position of CH18 field.

◆ PPI_CHENCLR_CH19_Clear

#define PPI_CHENCLR_CH19_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH19_Disabled

#define PPI_CHENCLR_CH19_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH19_Enabled

#define PPI_CHENCLR_CH19_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH19_Msk

#define PPI_CHENCLR_CH19_Msk   (0x1UL << PPI_CHENCLR_CH19_Pos)

Bit mask of CH19 field.

◆ PPI_CHENCLR_CH19_Pos

#define PPI_CHENCLR_CH19_Pos   (19UL)

Position of CH19 field.

◆ PPI_CHENCLR_CH1_Clear

#define PPI_CHENCLR_CH1_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH1_Disabled

#define PPI_CHENCLR_CH1_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH1_Enabled

#define PPI_CHENCLR_CH1_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH1_Msk

#define PPI_CHENCLR_CH1_Msk   (0x1UL << PPI_CHENCLR_CH1_Pos)

Bit mask of CH1 field.

◆ PPI_CHENCLR_CH1_Pos

#define PPI_CHENCLR_CH1_Pos   (1UL)

Position of CH1 field.

◆ PPI_CHENCLR_CH20_Clear

#define PPI_CHENCLR_CH20_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH20_Disabled

#define PPI_CHENCLR_CH20_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH20_Enabled

#define PPI_CHENCLR_CH20_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH20_Msk

#define PPI_CHENCLR_CH20_Msk   (0x1UL << PPI_CHENCLR_CH20_Pos)

Bit mask of CH20 field.

◆ PPI_CHENCLR_CH20_Pos

#define PPI_CHENCLR_CH20_Pos   (20UL)

Position of CH20 field.

◆ PPI_CHENCLR_CH21_Clear

#define PPI_CHENCLR_CH21_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH21_Disabled

#define PPI_CHENCLR_CH21_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH21_Enabled

#define PPI_CHENCLR_CH21_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH21_Msk

#define PPI_CHENCLR_CH21_Msk   (0x1UL << PPI_CHENCLR_CH21_Pos)

Bit mask of CH21 field.

◆ PPI_CHENCLR_CH21_Pos

#define PPI_CHENCLR_CH21_Pos   (21UL)

Position of CH21 field.

◆ PPI_CHENCLR_CH22_Clear

#define PPI_CHENCLR_CH22_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH22_Disabled

#define PPI_CHENCLR_CH22_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH22_Enabled

#define PPI_CHENCLR_CH22_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH22_Msk

#define PPI_CHENCLR_CH22_Msk   (0x1UL << PPI_CHENCLR_CH22_Pos)

Bit mask of CH22 field.

◆ PPI_CHENCLR_CH22_Pos

#define PPI_CHENCLR_CH22_Pos   (22UL)

Position of CH22 field.

◆ PPI_CHENCLR_CH23_Clear

#define PPI_CHENCLR_CH23_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH23_Disabled

#define PPI_CHENCLR_CH23_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH23_Enabled

#define PPI_CHENCLR_CH23_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH23_Msk

#define PPI_CHENCLR_CH23_Msk   (0x1UL << PPI_CHENCLR_CH23_Pos)

Bit mask of CH23 field.

◆ PPI_CHENCLR_CH23_Pos

#define PPI_CHENCLR_CH23_Pos   (23UL)

Position of CH23 field.

◆ PPI_CHENCLR_CH24_Clear

#define PPI_CHENCLR_CH24_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH24_Disabled

#define PPI_CHENCLR_CH24_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH24_Enabled

#define PPI_CHENCLR_CH24_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH24_Msk

#define PPI_CHENCLR_CH24_Msk   (0x1UL << PPI_CHENCLR_CH24_Pos)

Bit mask of CH24 field.

◆ PPI_CHENCLR_CH24_Pos

#define PPI_CHENCLR_CH24_Pos   (24UL)

Position of CH24 field.

◆ PPI_CHENCLR_CH25_Clear

#define PPI_CHENCLR_CH25_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH25_Disabled

#define PPI_CHENCLR_CH25_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH25_Enabled

#define PPI_CHENCLR_CH25_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH25_Msk

#define PPI_CHENCLR_CH25_Msk   (0x1UL << PPI_CHENCLR_CH25_Pos)

Bit mask of CH25 field.

◆ PPI_CHENCLR_CH25_Pos

#define PPI_CHENCLR_CH25_Pos   (25UL)

Position of CH25 field.

◆ PPI_CHENCLR_CH26_Clear

#define PPI_CHENCLR_CH26_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH26_Disabled

#define PPI_CHENCLR_CH26_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH26_Enabled

#define PPI_CHENCLR_CH26_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH26_Msk

#define PPI_CHENCLR_CH26_Msk   (0x1UL << PPI_CHENCLR_CH26_Pos)

Bit mask of CH26 field.

◆ PPI_CHENCLR_CH26_Pos

#define PPI_CHENCLR_CH26_Pos   (26UL)

Position of CH26 field.

◆ PPI_CHENCLR_CH27_Clear

#define PPI_CHENCLR_CH27_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH27_Disabled

#define PPI_CHENCLR_CH27_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH27_Enabled

#define PPI_CHENCLR_CH27_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH27_Msk

#define PPI_CHENCLR_CH27_Msk   (0x1UL << PPI_CHENCLR_CH27_Pos)

Bit mask of CH27 field.

◆ PPI_CHENCLR_CH27_Pos

#define PPI_CHENCLR_CH27_Pos   (27UL)

Position of CH27 field.

◆ PPI_CHENCLR_CH28_Clear

#define PPI_CHENCLR_CH28_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH28_Disabled

#define PPI_CHENCLR_CH28_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH28_Enabled

#define PPI_CHENCLR_CH28_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH28_Msk

#define PPI_CHENCLR_CH28_Msk   (0x1UL << PPI_CHENCLR_CH28_Pos)

Bit mask of CH28 field.

◆ PPI_CHENCLR_CH28_Pos

#define PPI_CHENCLR_CH28_Pos   (28UL)

Position of CH28 field.

◆ PPI_CHENCLR_CH29_Clear

#define PPI_CHENCLR_CH29_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH29_Disabled

#define PPI_CHENCLR_CH29_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH29_Enabled

#define PPI_CHENCLR_CH29_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH29_Msk

#define PPI_CHENCLR_CH29_Msk   (0x1UL << PPI_CHENCLR_CH29_Pos)

Bit mask of CH29 field.

◆ PPI_CHENCLR_CH29_Pos

#define PPI_CHENCLR_CH29_Pos   (29UL)

Position of CH29 field.

◆ PPI_CHENCLR_CH2_Clear

#define PPI_CHENCLR_CH2_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH2_Disabled

#define PPI_CHENCLR_CH2_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH2_Enabled

#define PPI_CHENCLR_CH2_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH2_Msk

#define PPI_CHENCLR_CH2_Msk   (0x1UL << PPI_CHENCLR_CH2_Pos)

Bit mask of CH2 field.

◆ PPI_CHENCLR_CH2_Pos

#define PPI_CHENCLR_CH2_Pos   (2UL)

Position of CH2 field.

◆ PPI_CHENCLR_CH30_Clear

#define PPI_CHENCLR_CH30_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH30_Disabled

#define PPI_CHENCLR_CH30_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH30_Enabled

#define PPI_CHENCLR_CH30_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH30_Msk

#define PPI_CHENCLR_CH30_Msk   (0x1UL << PPI_CHENCLR_CH30_Pos)

Bit mask of CH30 field.

◆ PPI_CHENCLR_CH30_Pos

#define PPI_CHENCLR_CH30_Pos   (30UL)

Position of CH30 field.

◆ PPI_CHENCLR_CH31_Clear

#define PPI_CHENCLR_CH31_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH31_Disabled

#define PPI_CHENCLR_CH31_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH31_Enabled

#define PPI_CHENCLR_CH31_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH31_Msk

#define PPI_CHENCLR_CH31_Msk   (0x1UL << PPI_CHENCLR_CH31_Pos)

Bit mask of CH31 field.

◆ PPI_CHENCLR_CH31_Pos

#define PPI_CHENCLR_CH31_Pos   (31UL)

Position of CH31 field.

◆ PPI_CHENCLR_CH3_Clear

#define PPI_CHENCLR_CH3_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH3_Disabled

#define PPI_CHENCLR_CH3_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH3_Enabled

#define PPI_CHENCLR_CH3_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH3_Msk

#define PPI_CHENCLR_CH3_Msk   (0x1UL << PPI_CHENCLR_CH3_Pos)

Bit mask of CH3 field.

◆ PPI_CHENCLR_CH3_Pos

#define PPI_CHENCLR_CH3_Pos   (3UL)

Position of CH3 field.

◆ PPI_CHENCLR_CH4_Clear

#define PPI_CHENCLR_CH4_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH4_Disabled

#define PPI_CHENCLR_CH4_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH4_Enabled

#define PPI_CHENCLR_CH4_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH4_Msk

#define PPI_CHENCLR_CH4_Msk   (0x1UL << PPI_CHENCLR_CH4_Pos)

Bit mask of CH4 field.

◆ PPI_CHENCLR_CH4_Pos

#define PPI_CHENCLR_CH4_Pos   (4UL)

Position of CH4 field.

◆ PPI_CHENCLR_CH5_Clear

#define PPI_CHENCLR_CH5_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH5_Disabled

#define PPI_CHENCLR_CH5_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH5_Enabled

#define PPI_CHENCLR_CH5_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH5_Msk

#define PPI_CHENCLR_CH5_Msk   (0x1UL << PPI_CHENCLR_CH5_Pos)

Bit mask of CH5 field.

◆ PPI_CHENCLR_CH5_Pos

#define PPI_CHENCLR_CH5_Pos   (5UL)

Position of CH5 field.

◆ PPI_CHENCLR_CH6_Clear

#define PPI_CHENCLR_CH6_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH6_Disabled

#define PPI_CHENCLR_CH6_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH6_Enabled

#define PPI_CHENCLR_CH6_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH6_Msk

#define PPI_CHENCLR_CH6_Msk   (0x1UL << PPI_CHENCLR_CH6_Pos)

Bit mask of CH6 field.

◆ PPI_CHENCLR_CH6_Pos

#define PPI_CHENCLR_CH6_Pos   (6UL)

Position of CH6 field.

◆ PPI_CHENCLR_CH7_Clear

#define PPI_CHENCLR_CH7_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH7_Disabled

#define PPI_CHENCLR_CH7_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH7_Enabled

#define PPI_CHENCLR_CH7_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH7_Msk

#define PPI_CHENCLR_CH7_Msk   (0x1UL << PPI_CHENCLR_CH7_Pos)

Bit mask of CH7 field.

◆ PPI_CHENCLR_CH7_Pos

#define PPI_CHENCLR_CH7_Pos   (7UL)

Position of CH7 field.

◆ PPI_CHENCLR_CH8_Clear

#define PPI_CHENCLR_CH8_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH8_Disabled

#define PPI_CHENCLR_CH8_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH8_Enabled

#define PPI_CHENCLR_CH8_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH8_Msk

#define PPI_CHENCLR_CH8_Msk   (0x1UL << PPI_CHENCLR_CH8_Pos)

Bit mask of CH8 field.

◆ PPI_CHENCLR_CH8_Pos

#define PPI_CHENCLR_CH8_Pos   (8UL)

Position of CH8 field.

◆ PPI_CHENCLR_CH9_Clear

#define PPI_CHENCLR_CH9_Clear   (1UL)

Write: disable channel

◆ PPI_CHENCLR_CH9_Disabled

#define PPI_CHENCLR_CH9_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENCLR_CH9_Enabled

#define PPI_CHENCLR_CH9_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENCLR_CH9_Msk

#define PPI_CHENCLR_CH9_Msk   (0x1UL << PPI_CHENCLR_CH9_Pos)

Bit mask of CH9 field.

◆ PPI_CHENCLR_CH9_Pos

#define PPI_CHENCLR_CH9_Pos   (9UL)

Position of CH9 field.

◆ PPI_CHENSET_CH0_Disabled

#define PPI_CHENSET_CH0_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH0_Enabled

#define PPI_CHENSET_CH0_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH0_Msk

#define PPI_CHENSET_CH0_Msk   (0x1UL << PPI_CHENSET_CH0_Pos)

Bit mask of CH0 field.

◆ PPI_CHENSET_CH0_Pos

#define PPI_CHENSET_CH0_Pos   (0UL)

Position of CH0 field.

◆ PPI_CHENSET_CH0_Set

#define PPI_CHENSET_CH0_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH10_Disabled

#define PPI_CHENSET_CH10_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH10_Enabled

#define PPI_CHENSET_CH10_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH10_Msk

#define PPI_CHENSET_CH10_Msk   (0x1UL << PPI_CHENSET_CH10_Pos)

Bit mask of CH10 field.

◆ PPI_CHENSET_CH10_Pos

#define PPI_CHENSET_CH10_Pos   (10UL)

Position of CH10 field.

◆ PPI_CHENSET_CH10_Set

#define PPI_CHENSET_CH10_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH11_Disabled

#define PPI_CHENSET_CH11_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH11_Enabled

#define PPI_CHENSET_CH11_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH11_Msk

#define PPI_CHENSET_CH11_Msk   (0x1UL << PPI_CHENSET_CH11_Pos)

Bit mask of CH11 field.

◆ PPI_CHENSET_CH11_Pos

#define PPI_CHENSET_CH11_Pos   (11UL)

Position of CH11 field.

◆ PPI_CHENSET_CH11_Set

#define PPI_CHENSET_CH11_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH12_Disabled

#define PPI_CHENSET_CH12_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH12_Enabled

#define PPI_CHENSET_CH12_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH12_Msk

#define PPI_CHENSET_CH12_Msk   (0x1UL << PPI_CHENSET_CH12_Pos)

Bit mask of CH12 field.

◆ PPI_CHENSET_CH12_Pos

#define PPI_CHENSET_CH12_Pos   (12UL)

Position of CH12 field.

◆ PPI_CHENSET_CH12_Set

#define PPI_CHENSET_CH12_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH13_Disabled

#define PPI_CHENSET_CH13_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH13_Enabled

#define PPI_CHENSET_CH13_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH13_Msk

#define PPI_CHENSET_CH13_Msk   (0x1UL << PPI_CHENSET_CH13_Pos)

Bit mask of CH13 field.

◆ PPI_CHENSET_CH13_Pos

#define PPI_CHENSET_CH13_Pos   (13UL)

Position of CH13 field.

◆ PPI_CHENSET_CH13_Set

#define PPI_CHENSET_CH13_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH14_Disabled

#define PPI_CHENSET_CH14_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH14_Enabled

#define PPI_CHENSET_CH14_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH14_Msk

#define PPI_CHENSET_CH14_Msk   (0x1UL << PPI_CHENSET_CH14_Pos)

Bit mask of CH14 field.

◆ PPI_CHENSET_CH14_Pos

#define PPI_CHENSET_CH14_Pos   (14UL)

Position of CH14 field.

◆ PPI_CHENSET_CH14_Set

#define PPI_CHENSET_CH14_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH15_Disabled

#define PPI_CHENSET_CH15_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH15_Enabled

#define PPI_CHENSET_CH15_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH15_Msk

#define PPI_CHENSET_CH15_Msk   (0x1UL << PPI_CHENSET_CH15_Pos)

Bit mask of CH15 field.

◆ PPI_CHENSET_CH15_Pos

#define PPI_CHENSET_CH15_Pos   (15UL)

Position of CH15 field.

◆ PPI_CHENSET_CH15_Set

#define PPI_CHENSET_CH15_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH16_Disabled

#define PPI_CHENSET_CH16_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH16_Enabled

#define PPI_CHENSET_CH16_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH16_Msk

#define PPI_CHENSET_CH16_Msk   (0x1UL << PPI_CHENSET_CH16_Pos)

Bit mask of CH16 field.

◆ PPI_CHENSET_CH16_Pos

#define PPI_CHENSET_CH16_Pos   (16UL)

Position of CH16 field.

◆ PPI_CHENSET_CH16_Set

#define PPI_CHENSET_CH16_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH17_Disabled

#define PPI_CHENSET_CH17_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH17_Enabled

#define PPI_CHENSET_CH17_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH17_Msk

#define PPI_CHENSET_CH17_Msk   (0x1UL << PPI_CHENSET_CH17_Pos)

Bit mask of CH17 field.

◆ PPI_CHENSET_CH17_Pos

#define PPI_CHENSET_CH17_Pos   (17UL)

Position of CH17 field.

◆ PPI_CHENSET_CH17_Set

#define PPI_CHENSET_CH17_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH18_Disabled

#define PPI_CHENSET_CH18_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH18_Enabled

#define PPI_CHENSET_CH18_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH18_Msk

#define PPI_CHENSET_CH18_Msk   (0x1UL << PPI_CHENSET_CH18_Pos)

Bit mask of CH18 field.

◆ PPI_CHENSET_CH18_Pos

#define PPI_CHENSET_CH18_Pos   (18UL)

Position of CH18 field.

◆ PPI_CHENSET_CH18_Set

#define PPI_CHENSET_CH18_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH19_Disabled

#define PPI_CHENSET_CH19_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH19_Enabled

#define PPI_CHENSET_CH19_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH19_Msk

#define PPI_CHENSET_CH19_Msk   (0x1UL << PPI_CHENSET_CH19_Pos)

Bit mask of CH19 field.

◆ PPI_CHENSET_CH19_Pos

#define PPI_CHENSET_CH19_Pos   (19UL)

Position of CH19 field.

◆ PPI_CHENSET_CH19_Set

#define PPI_CHENSET_CH19_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH1_Disabled

#define PPI_CHENSET_CH1_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH1_Enabled

#define PPI_CHENSET_CH1_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH1_Msk

#define PPI_CHENSET_CH1_Msk   (0x1UL << PPI_CHENSET_CH1_Pos)

Bit mask of CH1 field.

◆ PPI_CHENSET_CH1_Pos

#define PPI_CHENSET_CH1_Pos   (1UL)

Position of CH1 field.

◆ PPI_CHENSET_CH1_Set

#define PPI_CHENSET_CH1_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH20_Disabled

#define PPI_CHENSET_CH20_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH20_Enabled

#define PPI_CHENSET_CH20_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH20_Msk

#define PPI_CHENSET_CH20_Msk   (0x1UL << PPI_CHENSET_CH20_Pos)

Bit mask of CH20 field.

◆ PPI_CHENSET_CH20_Pos

#define PPI_CHENSET_CH20_Pos   (20UL)

Position of CH20 field.

◆ PPI_CHENSET_CH20_Set

#define PPI_CHENSET_CH20_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH21_Disabled

#define PPI_CHENSET_CH21_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH21_Enabled

#define PPI_CHENSET_CH21_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH21_Msk

#define PPI_CHENSET_CH21_Msk   (0x1UL << PPI_CHENSET_CH21_Pos)

Bit mask of CH21 field.

◆ PPI_CHENSET_CH21_Pos

#define PPI_CHENSET_CH21_Pos   (21UL)

Position of CH21 field.

◆ PPI_CHENSET_CH21_Set

#define PPI_CHENSET_CH21_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH22_Disabled

#define PPI_CHENSET_CH22_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH22_Enabled

#define PPI_CHENSET_CH22_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH22_Msk

#define PPI_CHENSET_CH22_Msk   (0x1UL << PPI_CHENSET_CH22_Pos)

Bit mask of CH22 field.

◆ PPI_CHENSET_CH22_Pos

#define PPI_CHENSET_CH22_Pos   (22UL)

Position of CH22 field.

◆ PPI_CHENSET_CH22_Set

#define PPI_CHENSET_CH22_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH23_Disabled

#define PPI_CHENSET_CH23_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH23_Enabled

#define PPI_CHENSET_CH23_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH23_Msk

#define PPI_CHENSET_CH23_Msk   (0x1UL << PPI_CHENSET_CH23_Pos)

Bit mask of CH23 field.

◆ PPI_CHENSET_CH23_Pos

#define PPI_CHENSET_CH23_Pos   (23UL)

Position of CH23 field.

◆ PPI_CHENSET_CH23_Set

#define PPI_CHENSET_CH23_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH24_Disabled

#define PPI_CHENSET_CH24_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH24_Enabled

#define PPI_CHENSET_CH24_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH24_Msk

#define PPI_CHENSET_CH24_Msk   (0x1UL << PPI_CHENSET_CH24_Pos)

Bit mask of CH24 field.

◆ PPI_CHENSET_CH24_Pos

#define PPI_CHENSET_CH24_Pos   (24UL)

Position of CH24 field.

◆ PPI_CHENSET_CH24_Set

#define PPI_CHENSET_CH24_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH25_Disabled

#define PPI_CHENSET_CH25_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH25_Enabled

#define PPI_CHENSET_CH25_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH25_Msk

#define PPI_CHENSET_CH25_Msk   (0x1UL << PPI_CHENSET_CH25_Pos)

Bit mask of CH25 field.

◆ PPI_CHENSET_CH25_Pos

#define PPI_CHENSET_CH25_Pos   (25UL)

Position of CH25 field.

◆ PPI_CHENSET_CH25_Set

#define PPI_CHENSET_CH25_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH26_Disabled

#define PPI_CHENSET_CH26_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH26_Enabled

#define PPI_CHENSET_CH26_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH26_Msk

#define PPI_CHENSET_CH26_Msk   (0x1UL << PPI_CHENSET_CH26_Pos)

Bit mask of CH26 field.

◆ PPI_CHENSET_CH26_Pos

#define PPI_CHENSET_CH26_Pos   (26UL)

Position of CH26 field.

◆ PPI_CHENSET_CH26_Set

#define PPI_CHENSET_CH26_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH27_Disabled

#define PPI_CHENSET_CH27_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH27_Enabled

#define PPI_CHENSET_CH27_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH27_Msk

#define PPI_CHENSET_CH27_Msk   (0x1UL << PPI_CHENSET_CH27_Pos)

Bit mask of CH27 field.

◆ PPI_CHENSET_CH27_Pos

#define PPI_CHENSET_CH27_Pos   (27UL)

Position of CH27 field.

◆ PPI_CHENSET_CH27_Set

#define PPI_CHENSET_CH27_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH28_Disabled

#define PPI_CHENSET_CH28_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH28_Enabled

#define PPI_CHENSET_CH28_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH28_Msk

#define PPI_CHENSET_CH28_Msk   (0x1UL << PPI_CHENSET_CH28_Pos)

Bit mask of CH28 field.

◆ PPI_CHENSET_CH28_Pos

#define PPI_CHENSET_CH28_Pos   (28UL)

Position of CH28 field.

◆ PPI_CHENSET_CH28_Set

#define PPI_CHENSET_CH28_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH29_Disabled

#define PPI_CHENSET_CH29_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH29_Enabled

#define PPI_CHENSET_CH29_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH29_Msk

#define PPI_CHENSET_CH29_Msk   (0x1UL << PPI_CHENSET_CH29_Pos)

Bit mask of CH29 field.

◆ PPI_CHENSET_CH29_Pos

#define PPI_CHENSET_CH29_Pos   (29UL)

Position of CH29 field.

◆ PPI_CHENSET_CH29_Set

#define PPI_CHENSET_CH29_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH2_Disabled

#define PPI_CHENSET_CH2_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH2_Enabled

#define PPI_CHENSET_CH2_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH2_Msk

#define PPI_CHENSET_CH2_Msk   (0x1UL << PPI_CHENSET_CH2_Pos)

Bit mask of CH2 field.

◆ PPI_CHENSET_CH2_Pos

#define PPI_CHENSET_CH2_Pos   (2UL)

Position of CH2 field.

◆ PPI_CHENSET_CH2_Set

#define PPI_CHENSET_CH2_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH30_Disabled

#define PPI_CHENSET_CH30_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH30_Enabled

#define PPI_CHENSET_CH30_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH30_Msk

#define PPI_CHENSET_CH30_Msk   (0x1UL << PPI_CHENSET_CH30_Pos)

Bit mask of CH30 field.

◆ PPI_CHENSET_CH30_Pos

#define PPI_CHENSET_CH30_Pos   (30UL)

Position of CH30 field.

◆ PPI_CHENSET_CH30_Set

#define PPI_CHENSET_CH30_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH31_Disabled

#define PPI_CHENSET_CH31_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH31_Enabled

#define PPI_CHENSET_CH31_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH31_Msk

#define PPI_CHENSET_CH31_Msk   (0x1UL << PPI_CHENSET_CH31_Pos)

Bit mask of CH31 field.

◆ PPI_CHENSET_CH31_Pos

#define PPI_CHENSET_CH31_Pos   (31UL)

Position of CH31 field.

◆ PPI_CHENSET_CH31_Set

#define PPI_CHENSET_CH31_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH3_Disabled

#define PPI_CHENSET_CH3_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH3_Enabled

#define PPI_CHENSET_CH3_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH3_Msk

#define PPI_CHENSET_CH3_Msk   (0x1UL << PPI_CHENSET_CH3_Pos)

Bit mask of CH3 field.

◆ PPI_CHENSET_CH3_Pos

#define PPI_CHENSET_CH3_Pos   (3UL)

Position of CH3 field.

◆ PPI_CHENSET_CH3_Set

#define PPI_CHENSET_CH3_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH4_Disabled

#define PPI_CHENSET_CH4_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH4_Enabled

#define PPI_CHENSET_CH4_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH4_Msk

#define PPI_CHENSET_CH4_Msk   (0x1UL << PPI_CHENSET_CH4_Pos)

Bit mask of CH4 field.

◆ PPI_CHENSET_CH4_Pos

#define PPI_CHENSET_CH4_Pos   (4UL)

Position of CH4 field.

◆ PPI_CHENSET_CH4_Set

#define PPI_CHENSET_CH4_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH5_Disabled

#define PPI_CHENSET_CH5_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH5_Enabled

#define PPI_CHENSET_CH5_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH5_Msk

#define PPI_CHENSET_CH5_Msk   (0x1UL << PPI_CHENSET_CH5_Pos)

Bit mask of CH5 field.

◆ PPI_CHENSET_CH5_Pos

#define PPI_CHENSET_CH5_Pos   (5UL)

Position of CH5 field.

◆ PPI_CHENSET_CH5_Set

#define PPI_CHENSET_CH5_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH6_Disabled

#define PPI_CHENSET_CH6_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH6_Enabled

#define PPI_CHENSET_CH6_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH6_Msk

#define PPI_CHENSET_CH6_Msk   (0x1UL << PPI_CHENSET_CH6_Pos)

Bit mask of CH6 field.

◆ PPI_CHENSET_CH6_Pos

#define PPI_CHENSET_CH6_Pos   (6UL)

Position of CH6 field.

◆ PPI_CHENSET_CH6_Set

#define PPI_CHENSET_CH6_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH7_Disabled

#define PPI_CHENSET_CH7_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH7_Enabled

#define PPI_CHENSET_CH7_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH7_Msk

#define PPI_CHENSET_CH7_Msk   (0x1UL << PPI_CHENSET_CH7_Pos)

Bit mask of CH7 field.

◆ PPI_CHENSET_CH7_Pos

#define PPI_CHENSET_CH7_Pos   (7UL)

Position of CH7 field.

◆ PPI_CHENSET_CH7_Set

#define PPI_CHENSET_CH7_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH8_Disabled

#define PPI_CHENSET_CH8_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH8_Enabled

#define PPI_CHENSET_CH8_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH8_Msk

#define PPI_CHENSET_CH8_Msk   (0x1UL << PPI_CHENSET_CH8_Pos)

Bit mask of CH8 field.

◆ PPI_CHENSET_CH8_Pos

#define PPI_CHENSET_CH8_Pos   (8UL)

Position of CH8 field.

◆ PPI_CHENSET_CH8_Set

#define PPI_CHENSET_CH8_Set   (1UL)

Write: Enable channel

◆ PPI_CHENSET_CH9_Disabled

#define PPI_CHENSET_CH9_Disabled   (0UL)

Read: channel disabled

◆ PPI_CHENSET_CH9_Enabled

#define PPI_CHENSET_CH9_Enabled   (1UL)

Read: channel enabled

◆ PPI_CHENSET_CH9_Msk

#define PPI_CHENSET_CH9_Msk   (0x1UL << PPI_CHENSET_CH9_Pos)

Bit mask of CH9 field.

◆ PPI_CHENSET_CH9_Pos

#define PPI_CHENSET_CH9_Pos   (9UL)

Position of CH9 field.

◆ PPI_CHENSET_CH9_Set

#define PPI_CHENSET_CH9_Set   (1UL)

Write: Enable channel

◆ PPI_CHG_CH0_Excluded

#define PPI_CHG_CH0_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH0_Included

#define PPI_CHG_CH0_Included   (1UL)

Include

◆ PPI_CHG_CH0_Msk

#define PPI_CHG_CH0_Msk   (0x1UL << PPI_CHG_CH0_Pos)

Bit mask of CH0 field.

◆ PPI_CHG_CH0_Pos

#define PPI_CHG_CH0_Pos   (0UL)

Position of CH0 field.

◆ PPI_CHG_CH10_Excluded

#define PPI_CHG_CH10_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH10_Included

#define PPI_CHG_CH10_Included   (1UL)

Include

◆ PPI_CHG_CH10_Msk

#define PPI_CHG_CH10_Msk   (0x1UL << PPI_CHG_CH10_Pos)

Bit mask of CH10 field.

◆ PPI_CHG_CH10_Pos

#define PPI_CHG_CH10_Pos   (10UL)

Position of CH10 field.

◆ PPI_CHG_CH11_Excluded

#define PPI_CHG_CH11_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH11_Included

#define PPI_CHG_CH11_Included   (1UL)

Include

◆ PPI_CHG_CH11_Msk

#define PPI_CHG_CH11_Msk   (0x1UL << PPI_CHG_CH11_Pos)

Bit mask of CH11 field.

◆ PPI_CHG_CH11_Pos

#define PPI_CHG_CH11_Pos   (11UL)

Position of CH11 field.

◆ PPI_CHG_CH12_Excluded

#define PPI_CHG_CH12_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH12_Included

#define PPI_CHG_CH12_Included   (1UL)

Include

◆ PPI_CHG_CH12_Msk

#define PPI_CHG_CH12_Msk   (0x1UL << PPI_CHG_CH12_Pos)

Bit mask of CH12 field.

◆ PPI_CHG_CH12_Pos

#define PPI_CHG_CH12_Pos   (12UL)

Position of CH12 field.

◆ PPI_CHG_CH13_Excluded

#define PPI_CHG_CH13_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH13_Included

#define PPI_CHG_CH13_Included   (1UL)

Include

◆ PPI_CHG_CH13_Msk

#define PPI_CHG_CH13_Msk   (0x1UL << PPI_CHG_CH13_Pos)

Bit mask of CH13 field.

◆ PPI_CHG_CH13_Pos

#define PPI_CHG_CH13_Pos   (13UL)

Position of CH13 field.

◆ PPI_CHG_CH14_Excluded

#define PPI_CHG_CH14_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH14_Included

#define PPI_CHG_CH14_Included   (1UL)

Include

◆ PPI_CHG_CH14_Msk

#define PPI_CHG_CH14_Msk   (0x1UL << PPI_CHG_CH14_Pos)

Bit mask of CH14 field.

◆ PPI_CHG_CH14_Pos

#define PPI_CHG_CH14_Pos   (14UL)

Position of CH14 field.

◆ PPI_CHG_CH15_Excluded

#define PPI_CHG_CH15_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH15_Included

#define PPI_CHG_CH15_Included   (1UL)

Include

◆ PPI_CHG_CH15_Msk

#define PPI_CHG_CH15_Msk   (0x1UL << PPI_CHG_CH15_Pos)

Bit mask of CH15 field.

◆ PPI_CHG_CH15_Pos

#define PPI_CHG_CH15_Pos   (15UL)

Position of CH15 field.

◆ PPI_CHG_CH16_Excluded

#define PPI_CHG_CH16_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH16_Included

#define PPI_CHG_CH16_Included   (1UL)

Include

◆ PPI_CHG_CH16_Msk

#define PPI_CHG_CH16_Msk   (0x1UL << PPI_CHG_CH16_Pos)

Bit mask of CH16 field.

◆ PPI_CHG_CH16_Pos

#define PPI_CHG_CH16_Pos   (16UL)

Position of CH16 field.

◆ PPI_CHG_CH17_Excluded

#define PPI_CHG_CH17_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH17_Included

#define PPI_CHG_CH17_Included   (1UL)

Include

◆ PPI_CHG_CH17_Msk

#define PPI_CHG_CH17_Msk   (0x1UL << PPI_CHG_CH17_Pos)

Bit mask of CH17 field.

◆ PPI_CHG_CH17_Pos

#define PPI_CHG_CH17_Pos   (17UL)

Position of CH17 field.

◆ PPI_CHG_CH18_Excluded

#define PPI_CHG_CH18_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH18_Included

#define PPI_CHG_CH18_Included   (1UL)

Include

◆ PPI_CHG_CH18_Msk

#define PPI_CHG_CH18_Msk   (0x1UL << PPI_CHG_CH18_Pos)

Bit mask of CH18 field.

◆ PPI_CHG_CH18_Pos

#define PPI_CHG_CH18_Pos   (18UL)

Position of CH18 field.

◆ PPI_CHG_CH19_Excluded

#define PPI_CHG_CH19_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH19_Included

#define PPI_CHG_CH19_Included   (1UL)

Include

◆ PPI_CHG_CH19_Msk

#define PPI_CHG_CH19_Msk   (0x1UL << PPI_CHG_CH19_Pos)

Bit mask of CH19 field.

◆ PPI_CHG_CH19_Pos

#define PPI_CHG_CH19_Pos   (19UL)

Position of CH19 field.

◆ PPI_CHG_CH1_Excluded

#define PPI_CHG_CH1_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH1_Included

#define PPI_CHG_CH1_Included   (1UL)

Include

◆ PPI_CHG_CH1_Msk

#define PPI_CHG_CH1_Msk   (0x1UL << PPI_CHG_CH1_Pos)

Bit mask of CH1 field.

◆ PPI_CHG_CH1_Pos

#define PPI_CHG_CH1_Pos   (1UL)

Position of CH1 field.

◆ PPI_CHG_CH20_Excluded

#define PPI_CHG_CH20_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH20_Included

#define PPI_CHG_CH20_Included   (1UL)

Include

◆ PPI_CHG_CH20_Msk

#define PPI_CHG_CH20_Msk   (0x1UL << PPI_CHG_CH20_Pos)

Bit mask of CH20 field.

◆ PPI_CHG_CH20_Pos

#define PPI_CHG_CH20_Pos   (20UL)

Position of CH20 field.

◆ PPI_CHG_CH21_Excluded

#define PPI_CHG_CH21_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH21_Included

#define PPI_CHG_CH21_Included   (1UL)

Include

◆ PPI_CHG_CH21_Msk

#define PPI_CHG_CH21_Msk   (0x1UL << PPI_CHG_CH21_Pos)

Bit mask of CH21 field.

◆ PPI_CHG_CH21_Pos

#define PPI_CHG_CH21_Pos   (21UL)

Position of CH21 field.

◆ PPI_CHG_CH22_Excluded

#define PPI_CHG_CH22_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH22_Included

#define PPI_CHG_CH22_Included   (1UL)

Include

◆ PPI_CHG_CH22_Msk

#define PPI_CHG_CH22_Msk   (0x1UL << PPI_CHG_CH22_Pos)

Bit mask of CH22 field.

◆ PPI_CHG_CH22_Pos

#define PPI_CHG_CH22_Pos   (22UL)

Position of CH22 field.

◆ PPI_CHG_CH23_Excluded

#define PPI_CHG_CH23_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH23_Included

#define PPI_CHG_CH23_Included   (1UL)

Include

◆ PPI_CHG_CH23_Msk

#define PPI_CHG_CH23_Msk   (0x1UL << PPI_CHG_CH23_Pos)

Bit mask of CH23 field.

◆ PPI_CHG_CH23_Pos

#define PPI_CHG_CH23_Pos   (23UL)

Position of CH23 field.

◆ PPI_CHG_CH24_Excluded

#define PPI_CHG_CH24_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH24_Included

#define PPI_CHG_CH24_Included   (1UL)

Include

◆ PPI_CHG_CH24_Msk

#define PPI_CHG_CH24_Msk   (0x1UL << PPI_CHG_CH24_Pos)

Bit mask of CH24 field.

◆ PPI_CHG_CH24_Pos

#define PPI_CHG_CH24_Pos   (24UL)

Position of CH24 field.

◆ PPI_CHG_CH25_Excluded

#define PPI_CHG_CH25_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH25_Included

#define PPI_CHG_CH25_Included   (1UL)

Include

◆ PPI_CHG_CH25_Msk

#define PPI_CHG_CH25_Msk   (0x1UL << PPI_CHG_CH25_Pos)

Bit mask of CH25 field.

◆ PPI_CHG_CH25_Pos

#define PPI_CHG_CH25_Pos   (25UL)

Position of CH25 field.

◆ PPI_CHG_CH26_Excluded

#define PPI_CHG_CH26_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH26_Included

#define PPI_CHG_CH26_Included   (1UL)

Include

◆ PPI_CHG_CH26_Msk

#define PPI_CHG_CH26_Msk   (0x1UL << PPI_CHG_CH26_Pos)

Bit mask of CH26 field.

◆ PPI_CHG_CH26_Pos

#define PPI_CHG_CH26_Pos   (26UL)

Position of CH26 field.

◆ PPI_CHG_CH27_Excluded

#define PPI_CHG_CH27_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH27_Included

#define PPI_CHG_CH27_Included   (1UL)

Include

◆ PPI_CHG_CH27_Msk

#define PPI_CHG_CH27_Msk   (0x1UL << PPI_CHG_CH27_Pos)

Bit mask of CH27 field.

◆ PPI_CHG_CH27_Pos

#define PPI_CHG_CH27_Pos   (27UL)

Position of CH27 field.

◆ PPI_CHG_CH28_Excluded

#define PPI_CHG_CH28_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH28_Included

#define PPI_CHG_CH28_Included   (1UL)

Include

◆ PPI_CHG_CH28_Msk

#define PPI_CHG_CH28_Msk   (0x1UL << PPI_CHG_CH28_Pos)

Bit mask of CH28 field.

◆ PPI_CHG_CH28_Pos

#define PPI_CHG_CH28_Pos   (28UL)

Position of CH28 field.

◆ PPI_CHG_CH29_Excluded

#define PPI_CHG_CH29_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH29_Included

#define PPI_CHG_CH29_Included   (1UL)

Include

◆ PPI_CHG_CH29_Msk

#define PPI_CHG_CH29_Msk   (0x1UL << PPI_CHG_CH29_Pos)

Bit mask of CH29 field.

◆ PPI_CHG_CH29_Pos

#define PPI_CHG_CH29_Pos   (29UL)

Position of CH29 field.

◆ PPI_CHG_CH2_Excluded

#define PPI_CHG_CH2_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH2_Included

#define PPI_CHG_CH2_Included   (1UL)

Include

◆ PPI_CHG_CH2_Msk

#define PPI_CHG_CH2_Msk   (0x1UL << PPI_CHG_CH2_Pos)

Bit mask of CH2 field.

◆ PPI_CHG_CH2_Pos

#define PPI_CHG_CH2_Pos   (2UL)

Position of CH2 field.

◆ PPI_CHG_CH30_Excluded

#define PPI_CHG_CH30_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH30_Included

#define PPI_CHG_CH30_Included   (1UL)

Include

◆ PPI_CHG_CH30_Msk

#define PPI_CHG_CH30_Msk   (0x1UL << PPI_CHG_CH30_Pos)

Bit mask of CH30 field.

◆ PPI_CHG_CH30_Pos

#define PPI_CHG_CH30_Pos   (30UL)

Position of CH30 field.

◆ PPI_CHG_CH31_Excluded

#define PPI_CHG_CH31_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH31_Included

#define PPI_CHG_CH31_Included   (1UL)

Include

◆ PPI_CHG_CH31_Msk

#define PPI_CHG_CH31_Msk   (0x1UL << PPI_CHG_CH31_Pos)

Bit mask of CH31 field.

◆ PPI_CHG_CH31_Pos

#define PPI_CHG_CH31_Pos   (31UL)

Position of CH31 field.

◆ PPI_CHG_CH3_Excluded

#define PPI_CHG_CH3_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH3_Included

#define PPI_CHG_CH3_Included   (1UL)

Include

◆ PPI_CHG_CH3_Msk

#define PPI_CHG_CH3_Msk   (0x1UL << PPI_CHG_CH3_Pos)

Bit mask of CH3 field.

◆ PPI_CHG_CH3_Pos

#define PPI_CHG_CH3_Pos   (3UL)

Position of CH3 field.

◆ PPI_CHG_CH4_Excluded

#define PPI_CHG_CH4_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH4_Included

#define PPI_CHG_CH4_Included   (1UL)

Include

◆ PPI_CHG_CH4_Msk

#define PPI_CHG_CH4_Msk   (0x1UL << PPI_CHG_CH4_Pos)

Bit mask of CH4 field.

◆ PPI_CHG_CH4_Pos

#define PPI_CHG_CH4_Pos   (4UL)

Position of CH4 field.

◆ PPI_CHG_CH5_Excluded

#define PPI_CHG_CH5_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH5_Included

#define PPI_CHG_CH5_Included   (1UL)

Include

◆ PPI_CHG_CH5_Msk

#define PPI_CHG_CH5_Msk   (0x1UL << PPI_CHG_CH5_Pos)

Bit mask of CH5 field.

◆ PPI_CHG_CH5_Pos

#define PPI_CHG_CH5_Pos   (5UL)

Position of CH5 field.

◆ PPI_CHG_CH6_Excluded

#define PPI_CHG_CH6_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH6_Included

#define PPI_CHG_CH6_Included   (1UL)

Include

◆ PPI_CHG_CH6_Msk

#define PPI_CHG_CH6_Msk   (0x1UL << PPI_CHG_CH6_Pos)

Bit mask of CH6 field.

◆ PPI_CHG_CH6_Pos

#define PPI_CHG_CH6_Pos   (6UL)

Position of CH6 field.

◆ PPI_CHG_CH7_Excluded

#define PPI_CHG_CH7_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH7_Included

#define PPI_CHG_CH7_Included   (1UL)

Include

◆ PPI_CHG_CH7_Msk

#define PPI_CHG_CH7_Msk   (0x1UL << PPI_CHG_CH7_Pos)

Bit mask of CH7 field.

◆ PPI_CHG_CH7_Pos

#define PPI_CHG_CH7_Pos   (7UL)

Position of CH7 field.

◆ PPI_CHG_CH8_Excluded

#define PPI_CHG_CH8_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH8_Included

#define PPI_CHG_CH8_Included   (1UL)

Include

◆ PPI_CHG_CH8_Msk

#define PPI_CHG_CH8_Msk   (0x1UL << PPI_CHG_CH8_Pos)

Bit mask of CH8 field.

◆ PPI_CHG_CH8_Pos

#define PPI_CHG_CH8_Pos   (8UL)

Position of CH8 field.

◆ PPI_CHG_CH9_Excluded

#define PPI_CHG_CH9_Excluded   (0UL)

Exclude

◆ PPI_CHG_CH9_Included

#define PPI_CHG_CH9_Included   (1UL)

Include

◆ PPI_CHG_CH9_Msk

#define PPI_CHG_CH9_Msk   (0x1UL << PPI_CHG_CH9_Pos)

Bit mask of CH9 field.

◆ PPI_CHG_CH9_Pos

#define PPI_CHG_CH9_Pos   (9UL)

Position of CH9 field.

◆ PPI_FORK_TEP_TEP_Msk

#define PPI_FORK_TEP_TEP_Msk   (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos)

Bit mask of TEP field.

◆ PPI_FORK_TEP_TEP_Pos

#define PPI_FORK_TEP_TEP_Pos   (0UL)

Position of TEP field.

◆ PWM_COUNTERTOP_COUNTERTOP_Msk

#define PWM_COUNTERTOP_COUNTERTOP_Msk   (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos)

Bit mask of COUNTERTOP field.

◆ PWM_COUNTERTOP_COUNTERTOP_Pos

#define PWM_COUNTERTOP_COUNTERTOP_Pos   (0UL)

Position of COUNTERTOP field.

◆ PWM_DECODER_LOAD_Common

#define PWM_DECODER_LOAD_Common   (0UL)

1st half word (16-bit) used in all PWM channels 0..3

◆ PWM_DECODER_LOAD_Grouped

#define PWM_DECODER_LOAD_Grouped   (1UL)

1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3

◆ PWM_DECODER_LOAD_Individual

#define PWM_DECODER_LOAD_Individual   (2UL)

1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3

◆ PWM_DECODER_LOAD_Msk

#define PWM_DECODER_LOAD_Msk   (0x3UL << PWM_DECODER_LOAD_Pos)

Bit mask of LOAD field.

◆ PWM_DECODER_LOAD_Pos

#define PWM_DECODER_LOAD_Pos   (0UL)

Position of LOAD field.

◆ PWM_DECODER_LOAD_WaveForm

#define PWM_DECODER_LOAD_WaveForm   (3UL)

1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP

◆ PWM_DECODER_MODE_Msk

#define PWM_DECODER_MODE_Msk   (0x1UL << PWM_DECODER_MODE_Pos)

Bit mask of MODE field.

◆ PWM_DECODER_MODE_NextStep

#define PWM_DECODER_MODE_NextStep   (1UL)

NEXTSTEP task causes a new value to be loaded to internal compare registers

◆ PWM_DECODER_MODE_Pos

#define PWM_DECODER_MODE_Pos   (8UL)

Position of MODE field.

◆ PWM_DECODER_MODE_RefreshCount

#define PWM_DECODER_MODE_RefreshCount   (0UL)

SEQ[n].REFRESH is used to determine loading internal compare registers

◆ PWM_ENABLE_ENABLE_Disabled

#define PWM_ENABLE_ENABLE_Disabled   (0UL)

Disabled

◆ PWM_ENABLE_ENABLE_Enabled

#define PWM_ENABLE_ENABLE_Enabled   (1UL)

Enable

◆ PWM_ENABLE_ENABLE_Msk

#define PWM_ENABLE_ENABLE_Msk   (0x1UL << PWM_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ PWM_ENABLE_ENABLE_Pos

#define PWM_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ PWM_INTEN_LOOPSDONE_Disabled

#define PWM_INTEN_LOOPSDONE_Disabled   (0UL)

Disable

◆ PWM_INTEN_LOOPSDONE_Enabled

#define PWM_INTEN_LOOPSDONE_Enabled   (1UL)

Enable

◆ PWM_INTEN_LOOPSDONE_Msk

#define PWM_INTEN_LOOPSDONE_Msk   (0x1UL << PWM_INTEN_LOOPSDONE_Pos)

Bit mask of LOOPSDONE field.

◆ PWM_INTEN_LOOPSDONE_Pos

#define PWM_INTEN_LOOPSDONE_Pos   (7UL)

Position of LOOPSDONE field.

◆ PWM_INTEN_PWMPERIODEND_Disabled

#define PWM_INTEN_PWMPERIODEND_Disabled   (0UL)

Disable

◆ PWM_INTEN_PWMPERIODEND_Enabled

#define PWM_INTEN_PWMPERIODEND_Enabled   (1UL)

Enable

◆ PWM_INTEN_PWMPERIODEND_Msk

#define PWM_INTEN_PWMPERIODEND_Msk   (0x1UL << PWM_INTEN_PWMPERIODEND_Pos)

Bit mask of PWMPERIODEND field.

◆ PWM_INTEN_PWMPERIODEND_Pos

#define PWM_INTEN_PWMPERIODEND_Pos   (6UL)

Position of PWMPERIODEND field.

◆ PWM_INTEN_SEQEND0_Disabled

#define PWM_INTEN_SEQEND0_Disabled   (0UL)

Disable

◆ PWM_INTEN_SEQEND0_Enabled

#define PWM_INTEN_SEQEND0_Enabled   (1UL)

Enable

◆ PWM_INTEN_SEQEND0_Msk

#define PWM_INTEN_SEQEND0_Msk   (0x1UL << PWM_INTEN_SEQEND0_Pos)

Bit mask of SEQEND0 field.

◆ PWM_INTEN_SEQEND0_Pos

#define PWM_INTEN_SEQEND0_Pos   (4UL)

Position of SEQEND0 field.

◆ PWM_INTEN_SEQEND1_Disabled

#define PWM_INTEN_SEQEND1_Disabled   (0UL)

Disable

◆ PWM_INTEN_SEQEND1_Enabled

#define PWM_INTEN_SEQEND1_Enabled   (1UL)

Enable

◆ PWM_INTEN_SEQEND1_Msk

#define PWM_INTEN_SEQEND1_Msk   (0x1UL << PWM_INTEN_SEQEND1_Pos)

Bit mask of SEQEND1 field.

◆ PWM_INTEN_SEQEND1_Pos

#define PWM_INTEN_SEQEND1_Pos   (5UL)

Position of SEQEND1 field.

◆ PWM_INTEN_SEQSTARTED0_Disabled

#define PWM_INTEN_SEQSTARTED0_Disabled   (0UL)

Disable

◆ PWM_INTEN_SEQSTARTED0_Enabled

#define PWM_INTEN_SEQSTARTED0_Enabled   (1UL)

Enable

◆ PWM_INTEN_SEQSTARTED0_Msk

#define PWM_INTEN_SEQSTARTED0_Msk   (0x1UL << PWM_INTEN_SEQSTARTED0_Pos)

Bit mask of SEQSTARTED0 field.

◆ PWM_INTEN_SEQSTARTED0_Pos

#define PWM_INTEN_SEQSTARTED0_Pos   (2UL)

Position of SEQSTARTED0 field.

◆ PWM_INTEN_SEQSTARTED1_Disabled

#define PWM_INTEN_SEQSTARTED1_Disabled   (0UL)

Disable

◆ PWM_INTEN_SEQSTARTED1_Enabled

#define PWM_INTEN_SEQSTARTED1_Enabled   (1UL)

Enable

◆ PWM_INTEN_SEQSTARTED1_Msk

#define PWM_INTEN_SEQSTARTED1_Msk   (0x1UL << PWM_INTEN_SEQSTARTED1_Pos)

Bit mask of SEQSTARTED1 field.

◆ PWM_INTEN_SEQSTARTED1_Pos

#define PWM_INTEN_SEQSTARTED1_Pos   (3UL)

Position of SEQSTARTED1 field.

◆ PWM_INTEN_STOPPED_Disabled

#define PWM_INTEN_STOPPED_Disabled   (0UL)

Disable

◆ PWM_INTEN_STOPPED_Enabled

#define PWM_INTEN_STOPPED_Enabled   (1UL)

Enable

◆ PWM_INTEN_STOPPED_Msk

#define PWM_INTEN_STOPPED_Msk   (0x1UL << PWM_INTEN_STOPPED_Pos)

Bit mask of STOPPED field.

◆ PWM_INTEN_STOPPED_Pos

#define PWM_INTEN_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ PWM_INTENCLR_LOOPSDONE_Clear

#define PWM_INTENCLR_LOOPSDONE_Clear   (1UL)

Disable

◆ PWM_INTENCLR_LOOPSDONE_Disabled

#define PWM_INTENCLR_LOOPSDONE_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENCLR_LOOPSDONE_Enabled

#define PWM_INTENCLR_LOOPSDONE_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENCLR_LOOPSDONE_Msk

#define PWM_INTENCLR_LOOPSDONE_Msk   (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos)

Bit mask of LOOPSDONE field.

◆ PWM_INTENCLR_LOOPSDONE_Pos

#define PWM_INTENCLR_LOOPSDONE_Pos   (7UL)

Position of LOOPSDONE field.

◆ PWM_INTENCLR_PWMPERIODEND_Clear

#define PWM_INTENCLR_PWMPERIODEND_Clear   (1UL)

Disable

◆ PWM_INTENCLR_PWMPERIODEND_Disabled

#define PWM_INTENCLR_PWMPERIODEND_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENCLR_PWMPERIODEND_Enabled

#define PWM_INTENCLR_PWMPERIODEND_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENCLR_PWMPERIODEND_Msk

#define PWM_INTENCLR_PWMPERIODEND_Msk   (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos)

Bit mask of PWMPERIODEND field.

◆ PWM_INTENCLR_PWMPERIODEND_Pos

#define PWM_INTENCLR_PWMPERIODEND_Pos   (6UL)

Position of PWMPERIODEND field.

◆ PWM_INTENCLR_SEQEND0_Clear

#define PWM_INTENCLR_SEQEND0_Clear   (1UL)

Disable

◆ PWM_INTENCLR_SEQEND0_Disabled

#define PWM_INTENCLR_SEQEND0_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENCLR_SEQEND0_Enabled

#define PWM_INTENCLR_SEQEND0_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENCLR_SEQEND0_Msk

#define PWM_INTENCLR_SEQEND0_Msk   (0x1UL << PWM_INTENCLR_SEQEND0_Pos)

Bit mask of SEQEND0 field.

◆ PWM_INTENCLR_SEQEND0_Pos

#define PWM_INTENCLR_SEQEND0_Pos   (4UL)

Position of SEQEND0 field.

◆ PWM_INTENCLR_SEQEND1_Clear

#define PWM_INTENCLR_SEQEND1_Clear   (1UL)

Disable

◆ PWM_INTENCLR_SEQEND1_Disabled

#define PWM_INTENCLR_SEQEND1_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENCLR_SEQEND1_Enabled

#define PWM_INTENCLR_SEQEND1_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENCLR_SEQEND1_Msk

#define PWM_INTENCLR_SEQEND1_Msk   (0x1UL << PWM_INTENCLR_SEQEND1_Pos)

Bit mask of SEQEND1 field.

◆ PWM_INTENCLR_SEQEND1_Pos

#define PWM_INTENCLR_SEQEND1_Pos   (5UL)

Position of SEQEND1 field.

◆ PWM_INTENCLR_SEQSTARTED0_Clear

#define PWM_INTENCLR_SEQSTARTED0_Clear   (1UL)

Disable

◆ PWM_INTENCLR_SEQSTARTED0_Disabled

#define PWM_INTENCLR_SEQSTARTED0_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENCLR_SEQSTARTED0_Enabled

#define PWM_INTENCLR_SEQSTARTED0_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENCLR_SEQSTARTED0_Msk

#define PWM_INTENCLR_SEQSTARTED0_Msk   (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos)

Bit mask of SEQSTARTED0 field.

◆ PWM_INTENCLR_SEQSTARTED0_Pos

#define PWM_INTENCLR_SEQSTARTED0_Pos   (2UL)

Position of SEQSTARTED0 field.

◆ PWM_INTENCLR_SEQSTARTED1_Clear

#define PWM_INTENCLR_SEQSTARTED1_Clear   (1UL)

Disable

◆ PWM_INTENCLR_SEQSTARTED1_Disabled

#define PWM_INTENCLR_SEQSTARTED1_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENCLR_SEQSTARTED1_Enabled

#define PWM_INTENCLR_SEQSTARTED1_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENCLR_SEQSTARTED1_Msk

#define PWM_INTENCLR_SEQSTARTED1_Msk   (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos)

Bit mask of SEQSTARTED1 field.

◆ PWM_INTENCLR_SEQSTARTED1_Pos

#define PWM_INTENCLR_SEQSTARTED1_Pos   (3UL)

Position of SEQSTARTED1 field.

◆ PWM_INTENCLR_STOPPED_Clear

#define PWM_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ PWM_INTENCLR_STOPPED_Disabled

#define PWM_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENCLR_STOPPED_Enabled

#define PWM_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENCLR_STOPPED_Msk

#define PWM_INTENCLR_STOPPED_Msk   (0x1UL << PWM_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ PWM_INTENCLR_STOPPED_Pos

#define PWM_INTENCLR_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ PWM_INTENSET_LOOPSDONE_Disabled

#define PWM_INTENSET_LOOPSDONE_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENSET_LOOPSDONE_Enabled

#define PWM_INTENSET_LOOPSDONE_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENSET_LOOPSDONE_Msk

#define PWM_INTENSET_LOOPSDONE_Msk   (0x1UL << PWM_INTENSET_LOOPSDONE_Pos)

Bit mask of LOOPSDONE field.

◆ PWM_INTENSET_LOOPSDONE_Pos

#define PWM_INTENSET_LOOPSDONE_Pos   (7UL)

Position of LOOPSDONE field.

◆ PWM_INTENSET_LOOPSDONE_Set

#define PWM_INTENSET_LOOPSDONE_Set   (1UL)

Enable

◆ PWM_INTENSET_PWMPERIODEND_Disabled

#define PWM_INTENSET_PWMPERIODEND_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENSET_PWMPERIODEND_Enabled

#define PWM_INTENSET_PWMPERIODEND_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENSET_PWMPERIODEND_Msk

#define PWM_INTENSET_PWMPERIODEND_Msk   (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos)

Bit mask of PWMPERIODEND field.

◆ PWM_INTENSET_PWMPERIODEND_Pos

#define PWM_INTENSET_PWMPERIODEND_Pos   (6UL)

Position of PWMPERIODEND field.

◆ PWM_INTENSET_PWMPERIODEND_Set

#define PWM_INTENSET_PWMPERIODEND_Set   (1UL)

Enable

◆ PWM_INTENSET_SEQEND0_Disabled

#define PWM_INTENSET_SEQEND0_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENSET_SEQEND0_Enabled

#define PWM_INTENSET_SEQEND0_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENSET_SEQEND0_Msk

#define PWM_INTENSET_SEQEND0_Msk   (0x1UL << PWM_INTENSET_SEQEND0_Pos)

Bit mask of SEQEND0 field.

◆ PWM_INTENSET_SEQEND0_Pos

#define PWM_INTENSET_SEQEND0_Pos   (4UL)

Position of SEQEND0 field.

◆ PWM_INTENSET_SEQEND0_Set

#define PWM_INTENSET_SEQEND0_Set   (1UL)

Enable

◆ PWM_INTENSET_SEQEND1_Disabled

#define PWM_INTENSET_SEQEND1_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENSET_SEQEND1_Enabled

#define PWM_INTENSET_SEQEND1_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENSET_SEQEND1_Msk

#define PWM_INTENSET_SEQEND1_Msk   (0x1UL << PWM_INTENSET_SEQEND1_Pos)

Bit mask of SEQEND1 field.

◆ PWM_INTENSET_SEQEND1_Pos

#define PWM_INTENSET_SEQEND1_Pos   (5UL)

Position of SEQEND1 field.

◆ PWM_INTENSET_SEQEND1_Set

#define PWM_INTENSET_SEQEND1_Set   (1UL)

Enable

◆ PWM_INTENSET_SEQSTARTED0_Disabled

#define PWM_INTENSET_SEQSTARTED0_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENSET_SEQSTARTED0_Enabled

#define PWM_INTENSET_SEQSTARTED0_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENSET_SEQSTARTED0_Msk

#define PWM_INTENSET_SEQSTARTED0_Msk   (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos)

Bit mask of SEQSTARTED0 field.

◆ PWM_INTENSET_SEQSTARTED0_Pos

#define PWM_INTENSET_SEQSTARTED0_Pos   (2UL)

Position of SEQSTARTED0 field.

◆ PWM_INTENSET_SEQSTARTED0_Set

#define PWM_INTENSET_SEQSTARTED0_Set   (1UL)

Enable

◆ PWM_INTENSET_SEQSTARTED1_Disabled

#define PWM_INTENSET_SEQSTARTED1_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENSET_SEQSTARTED1_Enabled

#define PWM_INTENSET_SEQSTARTED1_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENSET_SEQSTARTED1_Msk

#define PWM_INTENSET_SEQSTARTED1_Msk   (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos)

Bit mask of SEQSTARTED1 field.

◆ PWM_INTENSET_SEQSTARTED1_Pos

#define PWM_INTENSET_SEQSTARTED1_Pos   (3UL)

Position of SEQSTARTED1 field.

◆ PWM_INTENSET_SEQSTARTED1_Set

#define PWM_INTENSET_SEQSTARTED1_Set   (1UL)

Enable

◆ PWM_INTENSET_STOPPED_Disabled

#define PWM_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ PWM_INTENSET_STOPPED_Enabled

#define PWM_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ PWM_INTENSET_STOPPED_Msk

#define PWM_INTENSET_STOPPED_Msk   (0x1UL << PWM_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ PWM_INTENSET_STOPPED_Pos

#define PWM_INTENSET_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ PWM_INTENSET_STOPPED_Set

#define PWM_INTENSET_STOPPED_Set   (1UL)

Enable

◆ PWM_LOOP_CNT_Disabled

#define PWM_LOOP_CNT_Disabled   (0UL)

Looping disabled (stop at the end of the sequence)

◆ PWM_LOOP_CNT_Msk

#define PWM_LOOP_CNT_Msk   (0xFFFFUL << PWM_LOOP_CNT_Pos)

Bit mask of CNT field.

◆ PWM_LOOP_CNT_Pos

#define PWM_LOOP_CNT_Pos   (0UL)

Position of CNT field.

◆ PWM_MODE_UPDOWN_Msk

#define PWM_MODE_UPDOWN_Msk   (0x1UL << PWM_MODE_UPDOWN_Pos)

Bit mask of UPDOWN field.

◆ PWM_MODE_UPDOWN_Pos

#define PWM_MODE_UPDOWN_Pos   (0UL)

Position of UPDOWN field.

◆ PWM_MODE_UPDOWN_Up

#define PWM_MODE_UPDOWN_Up   (0UL)

Up counter - edge aligned PWM duty-cycle

◆ PWM_MODE_UPDOWN_UpAndDown

#define PWM_MODE_UPDOWN_UpAndDown   (1UL)

Up and down counter - center aligned PWM duty cycle

◆ PWM_PRESCALER_PRESCALER_DIV_1

#define PWM_PRESCALER_PRESCALER_DIV_1   (0UL)

Divide by 1 (16MHz)

◆ PWM_PRESCALER_PRESCALER_DIV_128

#define PWM_PRESCALER_PRESCALER_DIV_128   (7UL)

Divide by 128 ( 125kHz)

◆ PWM_PRESCALER_PRESCALER_DIV_16

#define PWM_PRESCALER_PRESCALER_DIV_16   (4UL)

Divide by 16 ( 1MHz)

◆ PWM_PRESCALER_PRESCALER_DIV_2

#define PWM_PRESCALER_PRESCALER_DIV_2   (1UL)

Divide by 2 ( 8MHz)

◆ PWM_PRESCALER_PRESCALER_DIV_32

#define PWM_PRESCALER_PRESCALER_DIV_32   (5UL)

Divide by 32 ( 500kHz)

◆ PWM_PRESCALER_PRESCALER_DIV_4

#define PWM_PRESCALER_PRESCALER_DIV_4   (2UL)

Divide by 4 ( 4MHz)

◆ PWM_PRESCALER_PRESCALER_DIV_64

#define PWM_PRESCALER_PRESCALER_DIV_64   (6UL)

Divide by 64 ( 250kHz)

◆ PWM_PRESCALER_PRESCALER_DIV_8

#define PWM_PRESCALER_PRESCALER_DIV_8   (3UL)

Divide by 8 ( 2MHz)

◆ PWM_PRESCALER_PRESCALER_Msk

#define PWM_PRESCALER_PRESCALER_Msk   (0x7UL << PWM_PRESCALER_PRESCALER_Pos)

Bit mask of PRESCALER field.

◆ PWM_PRESCALER_PRESCALER_Pos

#define PWM_PRESCALER_PRESCALER_Pos   (0UL)

Position of PRESCALER field.

◆ PWM_PSEL_OUT_CONNECT_Connected

#define PWM_PSEL_OUT_CONNECT_Connected   (0UL)

Connect

◆ PWM_PSEL_OUT_CONNECT_Disconnected

#define PWM_PSEL_OUT_CONNECT_Disconnected   (1UL)

Disconnect

◆ PWM_PSEL_OUT_CONNECT_Msk

#define PWM_PSEL_OUT_CONNECT_Msk   (0x1UL << PWM_PSEL_OUT_CONNECT_Pos)

Bit mask of CONNECT field.

◆ PWM_PSEL_OUT_CONNECT_Pos

#define PWM_PSEL_OUT_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ PWM_PSEL_OUT_PIN_Msk

#define PWM_PSEL_OUT_PIN_Msk   (0x1FUL << PWM_PSEL_OUT_PIN_Pos)

Bit mask of PIN field.

◆ PWM_PSEL_OUT_PIN_Pos

#define PWM_PSEL_OUT_PIN_Pos   (0UL)

Position of PIN field.

◆ PWM_SEQ_CNT_CNT_Disabled

#define PWM_SEQ_CNT_CNT_Disabled   (0UL)

Sequence is disabled, and shall not be started as it is empty

◆ PWM_SEQ_CNT_CNT_Msk

#define PWM_SEQ_CNT_CNT_Msk   (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos)

Bit mask of CNT field.

◆ PWM_SEQ_CNT_CNT_Pos

#define PWM_SEQ_CNT_CNT_Pos   (0UL)

Position of CNT field.

◆ PWM_SEQ_ENDDELAY_CNT_Msk

#define PWM_SEQ_ENDDELAY_CNT_Msk   (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos)

Bit mask of CNT field.

◆ PWM_SEQ_ENDDELAY_CNT_Pos

#define PWM_SEQ_ENDDELAY_CNT_Pos   (0UL)

Position of CNT field.

◆ PWM_SEQ_PTR_PTR_Msk

#define PWM_SEQ_PTR_PTR_Msk   (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos)

Bit mask of PTR field.

◆ PWM_SEQ_PTR_PTR_Pos

#define PWM_SEQ_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ PWM_SEQ_REFRESH_CNT_Continuous

#define PWM_SEQ_REFRESH_CNT_Continuous   (0UL)

Update every PWM period

◆ PWM_SEQ_REFRESH_CNT_Msk

#define PWM_SEQ_REFRESH_CNT_Msk   (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos)

Bit mask of CNT field.

◆ PWM_SEQ_REFRESH_CNT_Pos

#define PWM_SEQ_REFRESH_CNT_Pos   (0UL)

Position of CNT field.

◆ PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled

#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled   (0UL)

Disable shortcut

◆ PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled

#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled   (1UL)

Enable shortcut

◆ PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk

#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk   (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos)

Bit mask of LOOPSDONE_SEQSTART0 field.

◆ PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos

#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos   (2UL)

Position of LOOPSDONE_SEQSTART0 field.

◆ PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled

#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled   (0UL)

Disable shortcut

◆ PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled

#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled   (1UL)

Enable shortcut

◆ PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk

#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk   (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos)

Bit mask of LOOPSDONE_SEQSTART1 field.

◆ PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos

#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos   (3UL)

Position of LOOPSDONE_SEQSTART1 field.

◆ PWM_SHORTS_LOOPSDONE_STOP_Disabled

#define PWM_SHORTS_LOOPSDONE_STOP_Disabled   (0UL)

Disable shortcut

◆ PWM_SHORTS_LOOPSDONE_STOP_Enabled

#define PWM_SHORTS_LOOPSDONE_STOP_Enabled   (1UL)

Enable shortcut

◆ PWM_SHORTS_LOOPSDONE_STOP_Msk

#define PWM_SHORTS_LOOPSDONE_STOP_Msk   (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos)

Bit mask of LOOPSDONE_STOP field.

◆ PWM_SHORTS_LOOPSDONE_STOP_Pos

#define PWM_SHORTS_LOOPSDONE_STOP_Pos   (4UL)

Position of LOOPSDONE_STOP field.

◆ PWM_SHORTS_SEQEND0_STOP_Disabled

#define PWM_SHORTS_SEQEND0_STOP_Disabled   (0UL)

Disable shortcut

◆ PWM_SHORTS_SEQEND0_STOP_Enabled

#define PWM_SHORTS_SEQEND0_STOP_Enabled   (1UL)

Enable shortcut

◆ PWM_SHORTS_SEQEND0_STOP_Msk

#define PWM_SHORTS_SEQEND0_STOP_Msk   (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos)

Bit mask of SEQEND0_STOP field.

◆ PWM_SHORTS_SEQEND0_STOP_Pos

#define PWM_SHORTS_SEQEND0_STOP_Pos   (0UL)

Position of SEQEND0_STOP field.

◆ PWM_SHORTS_SEQEND1_STOP_Disabled

#define PWM_SHORTS_SEQEND1_STOP_Disabled   (0UL)

Disable shortcut

◆ PWM_SHORTS_SEQEND1_STOP_Enabled

#define PWM_SHORTS_SEQEND1_STOP_Enabled   (1UL)

Enable shortcut

◆ PWM_SHORTS_SEQEND1_STOP_Msk

#define PWM_SHORTS_SEQEND1_STOP_Msk   (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos)

Bit mask of SEQEND1_STOP field.

◆ PWM_SHORTS_SEQEND1_STOP_Pos

#define PWM_SHORTS_SEQEND1_STOP_Pos   (1UL)

Position of SEQEND1_STOP field.

◆ QDEC_ACC_ACC_Msk

#define QDEC_ACC_ACC_Msk   (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos)

Bit mask of ACC field.

◆ QDEC_ACC_ACC_Pos

#define QDEC_ACC_ACC_Pos   (0UL)

Position of ACC field.

◆ QDEC_ACCDBL_ACCDBL_Msk

#define QDEC_ACCDBL_ACCDBL_Msk   (0xFUL << QDEC_ACCDBL_ACCDBL_Pos)

Bit mask of ACCDBL field.

◆ QDEC_ACCDBL_ACCDBL_Pos

#define QDEC_ACCDBL_ACCDBL_Pos   (0UL)

Position of ACCDBL field.

◆ QDEC_ACCDBLREAD_ACCDBLREAD_Msk

#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk   (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos)

Bit mask of ACCDBLREAD field.

◆ QDEC_ACCDBLREAD_ACCDBLREAD_Pos

#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos   (0UL)

Position of ACCDBLREAD field.

◆ QDEC_ACCREAD_ACCREAD_Msk

#define QDEC_ACCREAD_ACCREAD_Msk   (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos)

Bit mask of ACCREAD field.

◆ QDEC_ACCREAD_ACCREAD_Pos

#define QDEC_ACCREAD_ACCREAD_Pos   (0UL)

Position of ACCREAD field.

◆ QDEC_DBFEN_DBFEN_Disabled

#define QDEC_DBFEN_DBFEN_Disabled   (0UL)

Debounce input filters disabled

◆ QDEC_DBFEN_DBFEN_Enabled

#define QDEC_DBFEN_DBFEN_Enabled   (1UL)

Debounce input filters enabled

◆ QDEC_DBFEN_DBFEN_Msk

#define QDEC_DBFEN_DBFEN_Msk   (0x1UL << QDEC_DBFEN_DBFEN_Pos)

Bit mask of DBFEN field.

◆ QDEC_DBFEN_DBFEN_Pos

#define QDEC_DBFEN_DBFEN_Pos   (0UL)

Position of DBFEN field.

◆ QDEC_ENABLE_ENABLE_Disabled

#define QDEC_ENABLE_ENABLE_Disabled   (0UL)

Disable

◆ QDEC_ENABLE_ENABLE_Enabled

#define QDEC_ENABLE_ENABLE_Enabled   (1UL)

Enable

◆ QDEC_ENABLE_ENABLE_Msk

#define QDEC_ENABLE_ENABLE_Msk   (0x1UL << QDEC_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ QDEC_ENABLE_ENABLE_Pos

#define QDEC_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ QDEC_INTENCLR_ACCOF_Clear

#define QDEC_INTENCLR_ACCOF_Clear   (1UL)

Disable

◆ QDEC_INTENCLR_ACCOF_Disabled

#define QDEC_INTENCLR_ACCOF_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENCLR_ACCOF_Enabled

#define QDEC_INTENCLR_ACCOF_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENCLR_ACCOF_Msk

#define QDEC_INTENCLR_ACCOF_Msk   (0x1UL << QDEC_INTENCLR_ACCOF_Pos)

Bit mask of ACCOF field.

◆ QDEC_INTENCLR_ACCOF_Pos

#define QDEC_INTENCLR_ACCOF_Pos   (2UL)

Position of ACCOF field.

◆ QDEC_INTENCLR_DBLRDY_Clear

#define QDEC_INTENCLR_DBLRDY_Clear   (1UL)

Disable

◆ QDEC_INTENCLR_DBLRDY_Disabled

#define QDEC_INTENCLR_DBLRDY_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENCLR_DBLRDY_Enabled

#define QDEC_INTENCLR_DBLRDY_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENCLR_DBLRDY_Msk

#define QDEC_INTENCLR_DBLRDY_Msk   (0x1UL << QDEC_INTENCLR_DBLRDY_Pos)

Bit mask of DBLRDY field.

◆ QDEC_INTENCLR_DBLRDY_Pos

#define QDEC_INTENCLR_DBLRDY_Pos   (3UL)

Position of DBLRDY field.

◆ QDEC_INTENCLR_REPORTRDY_Clear

#define QDEC_INTENCLR_REPORTRDY_Clear   (1UL)

Disable

◆ QDEC_INTENCLR_REPORTRDY_Disabled

#define QDEC_INTENCLR_REPORTRDY_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENCLR_REPORTRDY_Enabled

#define QDEC_INTENCLR_REPORTRDY_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENCLR_REPORTRDY_Msk

#define QDEC_INTENCLR_REPORTRDY_Msk   (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos)

Bit mask of REPORTRDY field.

◆ QDEC_INTENCLR_REPORTRDY_Pos

#define QDEC_INTENCLR_REPORTRDY_Pos   (1UL)

Position of REPORTRDY field.

◆ QDEC_INTENCLR_SAMPLERDY_Clear

#define QDEC_INTENCLR_SAMPLERDY_Clear   (1UL)

Disable

◆ QDEC_INTENCLR_SAMPLERDY_Disabled

#define QDEC_INTENCLR_SAMPLERDY_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENCLR_SAMPLERDY_Enabled

#define QDEC_INTENCLR_SAMPLERDY_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENCLR_SAMPLERDY_Msk

#define QDEC_INTENCLR_SAMPLERDY_Msk   (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos)

Bit mask of SAMPLERDY field.

◆ QDEC_INTENCLR_SAMPLERDY_Pos

#define QDEC_INTENCLR_SAMPLERDY_Pos   (0UL)

Position of SAMPLERDY field.

◆ QDEC_INTENCLR_STOPPED_Clear

#define QDEC_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ QDEC_INTENCLR_STOPPED_Disabled

#define QDEC_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENCLR_STOPPED_Enabled

#define QDEC_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENCLR_STOPPED_Msk

#define QDEC_INTENCLR_STOPPED_Msk   (0x1UL << QDEC_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ QDEC_INTENCLR_STOPPED_Pos

#define QDEC_INTENCLR_STOPPED_Pos   (4UL)

Position of STOPPED field.

◆ QDEC_INTENSET_ACCOF_Disabled

#define QDEC_INTENSET_ACCOF_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENSET_ACCOF_Enabled

#define QDEC_INTENSET_ACCOF_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENSET_ACCOF_Msk

#define QDEC_INTENSET_ACCOF_Msk   (0x1UL << QDEC_INTENSET_ACCOF_Pos)

Bit mask of ACCOF field.

◆ QDEC_INTENSET_ACCOF_Pos

#define QDEC_INTENSET_ACCOF_Pos   (2UL)

Position of ACCOF field.

◆ QDEC_INTENSET_ACCOF_Set

#define QDEC_INTENSET_ACCOF_Set   (1UL)

Enable

◆ QDEC_INTENSET_DBLRDY_Disabled

#define QDEC_INTENSET_DBLRDY_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENSET_DBLRDY_Enabled

#define QDEC_INTENSET_DBLRDY_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENSET_DBLRDY_Msk

#define QDEC_INTENSET_DBLRDY_Msk   (0x1UL << QDEC_INTENSET_DBLRDY_Pos)

Bit mask of DBLRDY field.

◆ QDEC_INTENSET_DBLRDY_Pos

#define QDEC_INTENSET_DBLRDY_Pos   (3UL)

Position of DBLRDY field.

◆ QDEC_INTENSET_DBLRDY_Set

#define QDEC_INTENSET_DBLRDY_Set   (1UL)

Enable

◆ QDEC_INTENSET_REPORTRDY_Disabled

#define QDEC_INTENSET_REPORTRDY_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENSET_REPORTRDY_Enabled

#define QDEC_INTENSET_REPORTRDY_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENSET_REPORTRDY_Msk

#define QDEC_INTENSET_REPORTRDY_Msk   (0x1UL << QDEC_INTENSET_REPORTRDY_Pos)

Bit mask of REPORTRDY field.

◆ QDEC_INTENSET_REPORTRDY_Pos

#define QDEC_INTENSET_REPORTRDY_Pos   (1UL)

Position of REPORTRDY field.

◆ QDEC_INTENSET_REPORTRDY_Set

#define QDEC_INTENSET_REPORTRDY_Set   (1UL)

Enable

◆ QDEC_INTENSET_SAMPLERDY_Disabled

#define QDEC_INTENSET_SAMPLERDY_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENSET_SAMPLERDY_Enabled

#define QDEC_INTENSET_SAMPLERDY_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENSET_SAMPLERDY_Msk

#define QDEC_INTENSET_SAMPLERDY_Msk   (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos)

Bit mask of SAMPLERDY field.

◆ QDEC_INTENSET_SAMPLERDY_Pos

#define QDEC_INTENSET_SAMPLERDY_Pos   (0UL)

Position of SAMPLERDY field.

◆ QDEC_INTENSET_SAMPLERDY_Set

#define QDEC_INTENSET_SAMPLERDY_Set   (1UL)

Enable

◆ QDEC_INTENSET_STOPPED_Disabled

#define QDEC_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ QDEC_INTENSET_STOPPED_Enabled

#define QDEC_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ QDEC_INTENSET_STOPPED_Msk

#define QDEC_INTENSET_STOPPED_Msk   (0x1UL << QDEC_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ QDEC_INTENSET_STOPPED_Pos

#define QDEC_INTENSET_STOPPED_Pos   (4UL)

Position of STOPPED field.

◆ QDEC_INTENSET_STOPPED_Set

#define QDEC_INTENSET_STOPPED_Set   (1UL)

Enable

◆ QDEC_LEDPOL_LEDPOL_ActiveHigh

#define QDEC_LEDPOL_LEDPOL_ActiveHigh   (1UL)

Led active on output pin high

◆ QDEC_LEDPOL_LEDPOL_ActiveLow

#define QDEC_LEDPOL_LEDPOL_ActiveLow   (0UL)

Led active on output pin low

◆ QDEC_LEDPOL_LEDPOL_Msk

#define QDEC_LEDPOL_LEDPOL_Msk   (0x1UL << QDEC_LEDPOL_LEDPOL_Pos)

Bit mask of LEDPOL field.

◆ QDEC_LEDPOL_LEDPOL_Pos

#define QDEC_LEDPOL_LEDPOL_Pos   (0UL)

Position of LEDPOL field.

◆ QDEC_LEDPRE_LEDPRE_Msk

#define QDEC_LEDPRE_LEDPRE_Msk   (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos)

Bit mask of LEDPRE field.

◆ QDEC_LEDPRE_LEDPRE_Pos

#define QDEC_LEDPRE_LEDPRE_Pos   (0UL)

Position of LEDPRE field.

◆ QDEC_PSEL_A_CONNECT_Connected

#define QDEC_PSEL_A_CONNECT_Connected   (0UL)

Connect

◆ QDEC_PSEL_A_CONNECT_Disconnected

#define QDEC_PSEL_A_CONNECT_Disconnected   (1UL)

Disconnect

◆ QDEC_PSEL_A_CONNECT_Msk

#define QDEC_PSEL_A_CONNECT_Msk   (0x1UL << QDEC_PSEL_A_CONNECT_Pos)

Bit mask of CONNECT field.

◆ QDEC_PSEL_A_CONNECT_Pos

#define QDEC_PSEL_A_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ QDEC_PSEL_A_PIN_Msk

#define QDEC_PSEL_A_PIN_Msk   (0x1FUL << QDEC_PSEL_A_PIN_Pos)

Bit mask of PIN field.

◆ QDEC_PSEL_A_PIN_Pos

#define QDEC_PSEL_A_PIN_Pos   (0UL)

Position of PIN field.

◆ QDEC_PSEL_B_CONNECT_Connected

#define QDEC_PSEL_B_CONNECT_Connected   (0UL)

Connect

◆ QDEC_PSEL_B_CONNECT_Disconnected

#define QDEC_PSEL_B_CONNECT_Disconnected   (1UL)

Disconnect

◆ QDEC_PSEL_B_CONNECT_Msk

#define QDEC_PSEL_B_CONNECT_Msk   (0x1UL << QDEC_PSEL_B_CONNECT_Pos)

Bit mask of CONNECT field.

◆ QDEC_PSEL_B_CONNECT_Pos

#define QDEC_PSEL_B_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ QDEC_PSEL_B_PIN_Msk

#define QDEC_PSEL_B_PIN_Msk   (0x1FUL << QDEC_PSEL_B_PIN_Pos)

Bit mask of PIN field.

◆ QDEC_PSEL_B_PIN_Pos

#define QDEC_PSEL_B_PIN_Pos   (0UL)

Position of PIN field.

◆ QDEC_PSEL_LED_CONNECT_Connected

#define QDEC_PSEL_LED_CONNECT_Connected   (0UL)

Connect

◆ QDEC_PSEL_LED_CONNECT_Disconnected

#define QDEC_PSEL_LED_CONNECT_Disconnected   (1UL)

Disconnect

◆ QDEC_PSEL_LED_CONNECT_Msk

#define QDEC_PSEL_LED_CONNECT_Msk   (0x1UL << QDEC_PSEL_LED_CONNECT_Pos)

Bit mask of CONNECT field.

◆ QDEC_PSEL_LED_CONNECT_Pos

#define QDEC_PSEL_LED_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ QDEC_PSEL_LED_PIN_Msk

#define QDEC_PSEL_LED_PIN_Msk   (0x1FUL << QDEC_PSEL_LED_PIN_Pos)

Bit mask of PIN field.

◆ QDEC_PSEL_LED_PIN_Pos

#define QDEC_PSEL_LED_PIN_Pos   (0UL)

Position of PIN field.

◆ QDEC_REPORTPER_REPORTPER_10Smpl

#define QDEC_REPORTPER_REPORTPER_10Smpl   (0UL)

10 samples / report

◆ QDEC_REPORTPER_REPORTPER_120Smpl

#define QDEC_REPORTPER_REPORTPER_120Smpl   (3UL)

120 samples / report

◆ QDEC_REPORTPER_REPORTPER_160Smpl

#define QDEC_REPORTPER_REPORTPER_160Smpl   (4UL)

160 samples / report

◆ QDEC_REPORTPER_REPORTPER_1Smpl

#define QDEC_REPORTPER_REPORTPER_1Smpl   (8UL)

1 sample / report

◆ QDEC_REPORTPER_REPORTPER_200Smpl

#define QDEC_REPORTPER_REPORTPER_200Smpl   (5UL)

200 samples / report

◆ QDEC_REPORTPER_REPORTPER_240Smpl

#define QDEC_REPORTPER_REPORTPER_240Smpl   (6UL)

240 samples / report

◆ QDEC_REPORTPER_REPORTPER_280Smpl

#define QDEC_REPORTPER_REPORTPER_280Smpl   (7UL)

280 samples / report

◆ QDEC_REPORTPER_REPORTPER_40Smpl

#define QDEC_REPORTPER_REPORTPER_40Smpl   (1UL)

40 samples / report

◆ QDEC_REPORTPER_REPORTPER_80Smpl

#define QDEC_REPORTPER_REPORTPER_80Smpl   (2UL)

80 samples / report

◆ QDEC_REPORTPER_REPORTPER_Msk

#define QDEC_REPORTPER_REPORTPER_Msk   (0xFUL << QDEC_REPORTPER_REPORTPER_Pos)

Bit mask of REPORTPER field.

◆ QDEC_REPORTPER_REPORTPER_Pos

#define QDEC_REPORTPER_REPORTPER_Pos   (0UL)

Position of REPORTPER field.

◆ QDEC_SAMPLE_SAMPLE_Msk

#define QDEC_SAMPLE_SAMPLE_Msk   (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos)

Bit mask of SAMPLE field.

◆ QDEC_SAMPLE_SAMPLE_Pos

#define QDEC_SAMPLE_SAMPLE_Pos   (0UL)

Position of SAMPLE field.

◆ QDEC_SAMPLEPER_SAMPLEPER_1024us

#define QDEC_SAMPLEPER_SAMPLEPER_1024us   (3UL)

1024 us

◆ QDEC_SAMPLEPER_SAMPLEPER_128us

#define QDEC_SAMPLEPER_SAMPLEPER_128us   (0UL)

128 us

◆ QDEC_SAMPLEPER_SAMPLEPER_131ms

#define QDEC_SAMPLEPER_SAMPLEPER_131ms   (10UL)

131072 us

◆ QDEC_SAMPLEPER_SAMPLEPER_16384us

#define QDEC_SAMPLEPER_SAMPLEPER_16384us   (7UL)

16384 us

◆ QDEC_SAMPLEPER_SAMPLEPER_2048us

#define QDEC_SAMPLEPER_SAMPLEPER_2048us   (4UL)

2048 us

◆ QDEC_SAMPLEPER_SAMPLEPER_256us

#define QDEC_SAMPLEPER_SAMPLEPER_256us   (1UL)

256 us

◆ QDEC_SAMPLEPER_SAMPLEPER_32ms

#define QDEC_SAMPLEPER_SAMPLEPER_32ms   (8UL)

32768 us

◆ QDEC_SAMPLEPER_SAMPLEPER_4096us

#define QDEC_SAMPLEPER_SAMPLEPER_4096us   (5UL)

4096 us

◆ QDEC_SAMPLEPER_SAMPLEPER_512us

#define QDEC_SAMPLEPER_SAMPLEPER_512us   (2UL)

512 us

◆ QDEC_SAMPLEPER_SAMPLEPER_65ms

#define QDEC_SAMPLEPER_SAMPLEPER_65ms   (9UL)

65536 us

◆ QDEC_SAMPLEPER_SAMPLEPER_8192us

#define QDEC_SAMPLEPER_SAMPLEPER_8192us   (6UL)

8192 us

◆ QDEC_SAMPLEPER_SAMPLEPER_Msk

#define QDEC_SAMPLEPER_SAMPLEPER_Msk   (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos)

Bit mask of SAMPLEPER field.

◆ QDEC_SAMPLEPER_SAMPLEPER_Pos

#define QDEC_SAMPLEPER_SAMPLEPER_Pos   (0UL)

Position of SAMPLEPER field.

◆ QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled

#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled   (0UL)

Disable shortcut

◆ QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled

#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled   (1UL)

Enable shortcut

◆ QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk

#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk   (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos)

Bit mask of DBLRDY_RDCLRDBL field.

◆ QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos

#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos   (4UL)

Position of DBLRDY_RDCLRDBL field.

◆ QDEC_SHORTS_DBLRDY_STOP_Disabled

#define QDEC_SHORTS_DBLRDY_STOP_Disabled   (0UL)

Disable shortcut

◆ QDEC_SHORTS_DBLRDY_STOP_Enabled

#define QDEC_SHORTS_DBLRDY_STOP_Enabled   (1UL)

Enable shortcut

◆ QDEC_SHORTS_DBLRDY_STOP_Msk

#define QDEC_SHORTS_DBLRDY_STOP_Msk   (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos)

Bit mask of DBLRDY_STOP field.

◆ QDEC_SHORTS_DBLRDY_STOP_Pos

#define QDEC_SHORTS_DBLRDY_STOP_Pos   (5UL)

Position of DBLRDY_STOP field.

◆ QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled

#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled   (0UL)

Disable shortcut

◆ QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled

#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled   (1UL)

Enable shortcut

◆ QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk

#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk   (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos)

Bit mask of REPORTRDY_RDCLRACC field.

◆ QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos

#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos   (2UL)

Position of REPORTRDY_RDCLRACC field.

◆ QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled

#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled   (0UL)

Disable shortcut

◆ QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled

#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled   (1UL)

Enable shortcut

◆ QDEC_SHORTS_REPORTRDY_READCLRACC_Msk

#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk   (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos)

Bit mask of REPORTRDY_READCLRACC field.

◆ QDEC_SHORTS_REPORTRDY_READCLRACC_Pos

#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos   (0UL)

Position of REPORTRDY_READCLRACC field.

◆ QDEC_SHORTS_REPORTRDY_STOP_Disabled

#define QDEC_SHORTS_REPORTRDY_STOP_Disabled   (0UL)

Disable shortcut

◆ QDEC_SHORTS_REPORTRDY_STOP_Enabled

#define QDEC_SHORTS_REPORTRDY_STOP_Enabled   (1UL)

Enable shortcut

◆ QDEC_SHORTS_REPORTRDY_STOP_Msk

#define QDEC_SHORTS_REPORTRDY_STOP_Msk   (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos)

Bit mask of REPORTRDY_STOP field.

◆ QDEC_SHORTS_REPORTRDY_STOP_Pos

#define QDEC_SHORTS_REPORTRDY_STOP_Pos   (3UL)

Position of REPORTRDY_STOP field.

◆ QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled

#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled   (0UL)

Disable shortcut

◆ QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled

#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled   (1UL)

Enable shortcut

◆ QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk

#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk   (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos)

Bit mask of SAMPLERDY_READCLRACC field.

◆ QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos

#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos   (6UL)

Position of SAMPLERDY_READCLRACC field.

◆ QDEC_SHORTS_SAMPLERDY_STOP_Disabled

#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled   (0UL)

Disable shortcut

◆ QDEC_SHORTS_SAMPLERDY_STOP_Enabled

#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled   (1UL)

Enable shortcut

◆ QDEC_SHORTS_SAMPLERDY_STOP_Msk

#define QDEC_SHORTS_SAMPLERDY_STOP_Msk   (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos)

Bit mask of SAMPLERDY_STOP field.

◆ QDEC_SHORTS_SAMPLERDY_STOP_Pos

#define QDEC_SHORTS_SAMPLERDY_STOP_Pos   (1UL)

Position of SAMPLERDY_STOP field.

◆ RADIO_BASE0_BASE0_Msk

#define RADIO_BASE0_BASE0_Msk   (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos)

Bit mask of BASE0 field.

◆ RADIO_BASE0_BASE0_Pos

#define RADIO_BASE0_BASE0_Pos   (0UL)

Position of BASE0 field.

◆ RADIO_BASE1_BASE1_Msk

#define RADIO_BASE1_BASE1_Msk   (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos)

Bit mask of BASE1 field.

◆ RADIO_BASE1_BASE1_Pos

#define RADIO_BASE1_BASE1_Pos   (0UL)

Position of BASE1 field.

◆ RADIO_BCC_BCC_Msk

#define RADIO_BCC_BCC_Msk   (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos)

Bit mask of BCC field.

◆ RADIO_BCC_BCC_Pos

#define RADIO_BCC_BCC_Pos   (0UL)

Position of BCC field.

◆ RADIO_CRCCNF_LEN_Disabled

#define RADIO_CRCCNF_LEN_Disabled   (0UL)

CRC length is zero and CRC calculation is disabled

◆ RADIO_CRCCNF_LEN_Msk

#define RADIO_CRCCNF_LEN_Msk   (0x3UL << RADIO_CRCCNF_LEN_Pos)

Bit mask of LEN field.

◆ RADIO_CRCCNF_LEN_One

#define RADIO_CRCCNF_LEN_One   (1UL)

CRC length is one byte and CRC calculation is enabled

◆ RADIO_CRCCNF_LEN_Pos

#define RADIO_CRCCNF_LEN_Pos   (0UL)

Position of LEN field.

◆ RADIO_CRCCNF_LEN_Three

#define RADIO_CRCCNF_LEN_Three   (3UL)

CRC length is three bytes and CRC calculation is enabled

◆ RADIO_CRCCNF_LEN_Two

#define RADIO_CRCCNF_LEN_Two   (2UL)

CRC length is two bytes and CRC calculation is enabled

◆ RADIO_CRCCNF_SKIPADDR_Include

#define RADIO_CRCCNF_SKIPADDR_Include   (0UL)

CRC calculation includes address field

◆ RADIO_CRCCNF_SKIPADDR_Msk

#define RADIO_CRCCNF_SKIPADDR_Msk   (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos)

Bit mask of SKIPADDR field.

◆ RADIO_CRCCNF_SKIPADDR_Pos

#define RADIO_CRCCNF_SKIPADDR_Pos   (8UL)

Position of SKIPADDR field.

◆ RADIO_CRCCNF_SKIPADDR_Skip

#define RADIO_CRCCNF_SKIPADDR_Skip   (1UL)

CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.

◆ RADIO_CRCINIT_CRCINIT_Msk

#define RADIO_CRCINIT_CRCINIT_Msk   (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos)

Bit mask of CRCINIT field.

◆ RADIO_CRCINIT_CRCINIT_Pos

#define RADIO_CRCINIT_CRCINIT_Pos   (0UL)

Position of CRCINIT field.

◆ RADIO_CRCPOLY_CRCPOLY_Msk

#define RADIO_CRCPOLY_CRCPOLY_Msk   (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos)

Bit mask of CRCPOLY field.

◆ RADIO_CRCPOLY_CRCPOLY_Pos

#define RADIO_CRCPOLY_CRCPOLY_Pos   (0UL)

Position of CRCPOLY field.

◆ RADIO_CRCSTATUS_CRCSTATUS_CRCError

#define RADIO_CRCSTATUS_CRCSTATUS_CRCError   (0UL)

Packet received with CRC error

◆ RADIO_CRCSTATUS_CRCSTATUS_CRCOk

#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk   (1UL)

Packet received with CRC ok

◆ RADIO_CRCSTATUS_CRCSTATUS_Msk

#define RADIO_CRCSTATUS_CRCSTATUS_Msk   (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos)

Bit mask of CRCSTATUS field.

◆ RADIO_CRCSTATUS_CRCSTATUS_Pos

#define RADIO_CRCSTATUS_CRCSTATUS_Pos   (0UL)

Position of CRCSTATUS field.

◆ RADIO_DAB_DAB_Msk

#define RADIO_DAB_DAB_Msk   (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos)

Bit mask of DAB field.

◆ RADIO_DAB_DAB_Pos

#define RADIO_DAB_DAB_Pos   (0UL)

Position of DAB field.

◆ RADIO_DACNF_ENA0_Disabled

#define RADIO_DACNF_ENA0_Disabled   (0UL)

Disabled

◆ RADIO_DACNF_ENA0_Enabled

#define RADIO_DACNF_ENA0_Enabled   (1UL)

Enabled

◆ RADIO_DACNF_ENA0_Msk

#define RADIO_DACNF_ENA0_Msk   (0x1UL << RADIO_DACNF_ENA0_Pos)

Bit mask of ENA0 field.

◆ RADIO_DACNF_ENA0_Pos

#define RADIO_DACNF_ENA0_Pos   (0UL)

Position of ENA0 field.

◆ RADIO_DACNF_ENA1_Disabled

#define RADIO_DACNF_ENA1_Disabled   (0UL)

Disabled

◆ RADIO_DACNF_ENA1_Enabled

#define RADIO_DACNF_ENA1_Enabled   (1UL)

Enabled

◆ RADIO_DACNF_ENA1_Msk

#define RADIO_DACNF_ENA1_Msk   (0x1UL << RADIO_DACNF_ENA1_Pos)

Bit mask of ENA1 field.

◆ RADIO_DACNF_ENA1_Pos

#define RADIO_DACNF_ENA1_Pos   (1UL)

Position of ENA1 field.

◆ RADIO_DACNF_ENA2_Disabled

#define RADIO_DACNF_ENA2_Disabled   (0UL)

Disabled

◆ RADIO_DACNF_ENA2_Enabled

#define RADIO_DACNF_ENA2_Enabled   (1UL)

Enabled

◆ RADIO_DACNF_ENA2_Msk

#define RADIO_DACNF_ENA2_Msk   (0x1UL << RADIO_DACNF_ENA2_Pos)

Bit mask of ENA2 field.

◆ RADIO_DACNF_ENA2_Pos

#define RADIO_DACNF_ENA2_Pos   (2UL)

Position of ENA2 field.

◆ RADIO_DACNF_ENA3_Disabled

#define RADIO_DACNF_ENA3_Disabled   (0UL)

Disabled

◆ RADIO_DACNF_ENA3_Enabled

#define RADIO_DACNF_ENA3_Enabled   (1UL)

Enabled

◆ RADIO_DACNF_ENA3_Msk

#define RADIO_DACNF_ENA3_Msk   (0x1UL << RADIO_DACNF_ENA3_Pos)

Bit mask of ENA3 field.

◆ RADIO_DACNF_ENA3_Pos

#define RADIO_DACNF_ENA3_Pos   (3UL)

Position of ENA3 field.

◆ RADIO_DACNF_ENA4_Disabled

#define RADIO_DACNF_ENA4_Disabled   (0UL)

Disabled

◆ RADIO_DACNF_ENA4_Enabled

#define RADIO_DACNF_ENA4_Enabled   (1UL)

Enabled

◆ RADIO_DACNF_ENA4_Msk

#define RADIO_DACNF_ENA4_Msk   (0x1UL << RADIO_DACNF_ENA4_Pos)

Bit mask of ENA4 field.

◆ RADIO_DACNF_ENA4_Pos

#define RADIO_DACNF_ENA4_Pos   (4UL)

Position of ENA4 field.

◆ RADIO_DACNF_ENA5_Disabled

#define RADIO_DACNF_ENA5_Disabled   (0UL)

Disabled

◆ RADIO_DACNF_ENA5_Enabled

#define RADIO_DACNF_ENA5_Enabled   (1UL)

Enabled

◆ RADIO_DACNF_ENA5_Msk

#define RADIO_DACNF_ENA5_Msk   (0x1UL << RADIO_DACNF_ENA5_Pos)

Bit mask of ENA5 field.

◆ RADIO_DACNF_ENA5_Pos

#define RADIO_DACNF_ENA5_Pos   (5UL)

Position of ENA5 field.

◆ RADIO_DACNF_ENA6_Disabled

#define RADIO_DACNF_ENA6_Disabled   (0UL)

Disabled

◆ RADIO_DACNF_ENA6_Enabled

#define RADIO_DACNF_ENA6_Enabled   (1UL)

Enabled

◆ RADIO_DACNF_ENA6_Msk

#define RADIO_DACNF_ENA6_Msk   (0x1UL << RADIO_DACNF_ENA6_Pos)

Bit mask of ENA6 field.

◆ RADIO_DACNF_ENA6_Pos

#define RADIO_DACNF_ENA6_Pos   (6UL)

Position of ENA6 field.

◆ RADIO_DACNF_ENA7_Disabled

#define RADIO_DACNF_ENA7_Disabled   (0UL)

Disabled

◆ RADIO_DACNF_ENA7_Enabled

#define RADIO_DACNF_ENA7_Enabled   (1UL)

Enabled

◆ RADIO_DACNF_ENA7_Msk

#define RADIO_DACNF_ENA7_Msk   (0x1UL << RADIO_DACNF_ENA7_Pos)

Bit mask of ENA7 field.

◆ RADIO_DACNF_ENA7_Pos

#define RADIO_DACNF_ENA7_Pos   (7UL)

Position of ENA7 field.

◆ RADIO_DACNF_TXADD0_Msk

#define RADIO_DACNF_TXADD0_Msk   (0x1UL << RADIO_DACNF_TXADD0_Pos)

Bit mask of TXADD0 field.

◆ RADIO_DACNF_TXADD0_Pos

#define RADIO_DACNF_TXADD0_Pos   (8UL)

Position of TXADD0 field.

◆ RADIO_DACNF_TXADD1_Msk

#define RADIO_DACNF_TXADD1_Msk   (0x1UL << RADIO_DACNF_TXADD1_Pos)

Bit mask of TXADD1 field.

◆ RADIO_DACNF_TXADD1_Pos

#define RADIO_DACNF_TXADD1_Pos   (9UL)

Position of TXADD1 field.

◆ RADIO_DACNF_TXADD2_Msk

#define RADIO_DACNF_TXADD2_Msk   (0x1UL << RADIO_DACNF_TXADD2_Pos)

Bit mask of TXADD2 field.

◆ RADIO_DACNF_TXADD2_Pos

#define RADIO_DACNF_TXADD2_Pos   (10UL)

Position of TXADD2 field.

◆ RADIO_DACNF_TXADD3_Msk

#define RADIO_DACNF_TXADD3_Msk   (0x1UL << RADIO_DACNF_TXADD3_Pos)

Bit mask of TXADD3 field.

◆ RADIO_DACNF_TXADD3_Pos

#define RADIO_DACNF_TXADD3_Pos   (11UL)

Position of TXADD3 field.

◆ RADIO_DACNF_TXADD4_Msk

#define RADIO_DACNF_TXADD4_Msk   (0x1UL << RADIO_DACNF_TXADD4_Pos)

Bit mask of TXADD4 field.

◆ RADIO_DACNF_TXADD4_Pos

#define RADIO_DACNF_TXADD4_Pos   (12UL)

Position of TXADD4 field.

◆ RADIO_DACNF_TXADD5_Msk

#define RADIO_DACNF_TXADD5_Msk   (0x1UL << RADIO_DACNF_TXADD5_Pos)

Bit mask of TXADD5 field.

◆ RADIO_DACNF_TXADD5_Pos

#define RADIO_DACNF_TXADD5_Pos   (13UL)

Position of TXADD5 field.

◆ RADIO_DACNF_TXADD6_Msk

#define RADIO_DACNF_TXADD6_Msk   (0x1UL << RADIO_DACNF_TXADD6_Pos)

Bit mask of TXADD6 field.

◆ RADIO_DACNF_TXADD6_Pos

#define RADIO_DACNF_TXADD6_Pos   (14UL)

Position of TXADD6 field.

◆ RADIO_DACNF_TXADD7_Msk

#define RADIO_DACNF_TXADD7_Msk   (0x1UL << RADIO_DACNF_TXADD7_Pos)

Bit mask of TXADD7 field.

◆ RADIO_DACNF_TXADD7_Pos

#define RADIO_DACNF_TXADD7_Pos   (15UL)

Position of TXADD7 field.

◆ RADIO_DAI_DAI_Msk

#define RADIO_DAI_DAI_Msk   (0x7UL << RADIO_DAI_DAI_Pos)

Bit mask of DAI field.

◆ RADIO_DAI_DAI_Pos

#define RADIO_DAI_DAI_Pos   (0UL)

Position of DAI field.

◆ RADIO_DAP_DAP_Msk

#define RADIO_DAP_DAP_Msk   (0xFFFFUL << RADIO_DAP_DAP_Pos)

Bit mask of DAP field.

◆ RADIO_DAP_DAP_Pos

#define RADIO_DAP_DAP_Pos   (0UL)

Position of DAP field.

◆ RADIO_DATAWHITEIV_DATAWHITEIV_Msk

#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk   (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos)

Bit mask of DATAWHITEIV field.

◆ RADIO_DATAWHITEIV_DATAWHITEIV_Pos

#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos   (0UL)

Position of DATAWHITEIV field.

◆ RADIO_FREQUENCY_FREQUENCY_Msk

#define RADIO_FREQUENCY_FREQUENCY_Msk   (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

◆ RADIO_FREQUENCY_FREQUENCY_Pos

#define RADIO_FREQUENCY_FREQUENCY_Pos   (0UL)

Position of FREQUENCY field.

◆ RADIO_FREQUENCY_MAP_Default

#define RADIO_FREQUENCY_MAP_Default   (0UL)

Channel map between 2400 MHZ .. 2500 MHz

◆ RADIO_FREQUENCY_MAP_Low

#define RADIO_FREQUENCY_MAP_Low   (1UL)

Channel map between 2360 MHZ .. 2460 MHz

◆ RADIO_FREQUENCY_MAP_Msk

#define RADIO_FREQUENCY_MAP_Msk   (0x1UL << RADIO_FREQUENCY_MAP_Pos)

Bit mask of MAP field.

◆ RADIO_FREQUENCY_MAP_Pos

#define RADIO_FREQUENCY_MAP_Pos   (8UL)

Position of MAP field.

◆ RADIO_INTENCLR_ADDRESS_Clear

#define RADIO_INTENCLR_ADDRESS_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_ADDRESS_Disabled

#define RADIO_INTENCLR_ADDRESS_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_ADDRESS_Enabled

#define RADIO_INTENCLR_ADDRESS_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_ADDRESS_Msk

#define RADIO_INTENCLR_ADDRESS_Msk   (0x1UL << RADIO_INTENCLR_ADDRESS_Pos)

Bit mask of ADDRESS field.

◆ RADIO_INTENCLR_ADDRESS_Pos

#define RADIO_INTENCLR_ADDRESS_Pos   (1UL)

Position of ADDRESS field.

◆ RADIO_INTENCLR_BCMATCH_Clear

#define RADIO_INTENCLR_BCMATCH_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_BCMATCH_Disabled

#define RADIO_INTENCLR_BCMATCH_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_BCMATCH_Enabled

#define RADIO_INTENCLR_BCMATCH_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_BCMATCH_Msk

#define RADIO_INTENCLR_BCMATCH_Msk   (0x1UL << RADIO_INTENCLR_BCMATCH_Pos)

Bit mask of BCMATCH field.

◆ RADIO_INTENCLR_BCMATCH_Pos

#define RADIO_INTENCLR_BCMATCH_Pos   (10UL)

Position of BCMATCH field.

◆ RADIO_INTENCLR_CRCERROR_Clear

#define RADIO_INTENCLR_CRCERROR_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_CRCERROR_Disabled

#define RADIO_INTENCLR_CRCERROR_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_CRCERROR_Enabled

#define RADIO_INTENCLR_CRCERROR_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_CRCERROR_Msk

#define RADIO_INTENCLR_CRCERROR_Msk   (0x1UL << RADIO_INTENCLR_CRCERROR_Pos)

Bit mask of CRCERROR field.

◆ RADIO_INTENCLR_CRCERROR_Pos

#define RADIO_INTENCLR_CRCERROR_Pos   (13UL)

Position of CRCERROR field.

◆ RADIO_INTENCLR_CRCOK_Clear

#define RADIO_INTENCLR_CRCOK_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_CRCOK_Disabled

#define RADIO_INTENCLR_CRCOK_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_CRCOK_Enabled

#define RADIO_INTENCLR_CRCOK_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_CRCOK_Msk

#define RADIO_INTENCLR_CRCOK_Msk   (0x1UL << RADIO_INTENCLR_CRCOK_Pos)

Bit mask of CRCOK field.

◆ RADIO_INTENCLR_CRCOK_Pos

#define RADIO_INTENCLR_CRCOK_Pos   (12UL)

Position of CRCOK field.

◆ RADIO_INTENCLR_DEVMATCH_Clear

#define RADIO_INTENCLR_DEVMATCH_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_DEVMATCH_Disabled

#define RADIO_INTENCLR_DEVMATCH_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_DEVMATCH_Enabled

#define RADIO_INTENCLR_DEVMATCH_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_DEVMATCH_Msk

#define RADIO_INTENCLR_DEVMATCH_Msk   (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos)

Bit mask of DEVMATCH field.

◆ RADIO_INTENCLR_DEVMATCH_Pos

#define RADIO_INTENCLR_DEVMATCH_Pos   (5UL)

Position of DEVMATCH field.

◆ RADIO_INTENCLR_DEVMISS_Clear

#define RADIO_INTENCLR_DEVMISS_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_DEVMISS_Disabled

#define RADIO_INTENCLR_DEVMISS_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_DEVMISS_Enabled

#define RADIO_INTENCLR_DEVMISS_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_DEVMISS_Msk

#define RADIO_INTENCLR_DEVMISS_Msk   (0x1UL << RADIO_INTENCLR_DEVMISS_Pos)

Bit mask of DEVMISS field.

◆ RADIO_INTENCLR_DEVMISS_Pos

#define RADIO_INTENCLR_DEVMISS_Pos   (6UL)

Position of DEVMISS field.

◆ RADIO_INTENCLR_DISABLED_Clear

#define RADIO_INTENCLR_DISABLED_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_DISABLED_Disabled

#define RADIO_INTENCLR_DISABLED_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_DISABLED_Enabled

#define RADIO_INTENCLR_DISABLED_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_DISABLED_Msk

#define RADIO_INTENCLR_DISABLED_Msk   (0x1UL << RADIO_INTENCLR_DISABLED_Pos)

Bit mask of DISABLED field.

◆ RADIO_INTENCLR_DISABLED_Pos

#define RADIO_INTENCLR_DISABLED_Pos   (4UL)

Position of DISABLED field.

◆ RADIO_INTENCLR_END_Clear

#define RADIO_INTENCLR_END_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_END_Disabled

#define RADIO_INTENCLR_END_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_END_Enabled

#define RADIO_INTENCLR_END_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_END_Msk

#define RADIO_INTENCLR_END_Msk   (0x1UL << RADIO_INTENCLR_END_Pos)

Bit mask of END field.

◆ RADIO_INTENCLR_END_Pos

#define RADIO_INTENCLR_END_Pos   (3UL)

Position of END field.

◆ RADIO_INTENCLR_PAYLOAD_Clear

#define RADIO_INTENCLR_PAYLOAD_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_PAYLOAD_Disabled

#define RADIO_INTENCLR_PAYLOAD_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_PAYLOAD_Enabled

#define RADIO_INTENCLR_PAYLOAD_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_PAYLOAD_Msk

#define RADIO_INTENCLR_PAYLOAD_Msk   (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos)

Bit mask of PAYLOAD field.

◆ RADIO_INTENCLR_PAYLOAD_Pos

#define RADIO_INTENCLR_PAYLOAD_Pos   (2UL)

Position of PAYLOAD field.

◆ RADIO_INTENCLR_READY_Clear

#define RADIO_INTENCLR_READY_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_READY_Disabled

#define RADIO_INTENCLR_READY_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_READY_Enabled

#define RADIO_INTENCLR_READY_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_READY_Msk

#define RADIO_INTENCLR_READY_Msk   (0x1UL << RADIO_INTENCLR_READY_Pos)

Bit mask of READY field.

◆ RADIO_INTENCLR_READY_Pos

#define RADIO_INTENCLR_READY_Pos   (0UL)

Position of READY field.

◆ RADIO_INTENCLR_RSSIEND_Clear

#define RADIO_INTENCLR_RSSIEND_Clear   (1UL)

Disable

◆ RADIO_INTENCLR_RSSIEND_Disabled

#define RADIO_INTENCLR_RSSIEND_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENCLR_RSSIEND_Enabled

#define RADIO_INTENCLR_RSSIEND_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENCLR_RSSIEND_Msk

#define RADIO_INTENCLR_RSSIEND_Msk   (0x1UL << RADIO_INTENCLR_RSSIEND_Pos)

Bit mask of RSSIEND field.

◆ RADIO_INTENCLR_RSSIEND_Pos

#define RADIO_INTENCLR_RSSIEND_Pos   (7UL)

Position of RSSIEND field.

◆ RADIO_INTENSET_ADDRESS_Disabled

#define RADIO_INTENSET_ADDRESS_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_ADDRESS_Enabled

#define RADIO_INTENSET_ADDRESS_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_ADDRESS_Msk

#define RADIO_INTENSET_ADDRESS_Msk   (0x1UL << RADIO_INTENSET_ADDRESS_Pos)

Bit mask of ADDRESS field.

◆ RADIO_INTENSET_ADDRESS_Pos

#define RADIO_INTENSET_ADDRESS_Pos   (1UL)

Position of ADDRESS field.

◆ RADIO_INTENSET_ADDRESS_Set

#define RADIO_INTENSET_ADDRESS_Set   (1UL)

Enable

◆ RADIO_INTENSET_BCMATCH_Disabled

#define RADIO_INTENSET_BCMATCH_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_BCMATCH_Enabled

#define RADIO_INTENSET_BCMATCH_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_BCMATCH_Msk

#define RADIO_INTENSET_BCMATCH_Msk   (0x1UL << RADIO_INTENSET_BCMATCH_Pos)

Bit mask of BCMATCH field.

◆ RADIO_INTENSET_BCMATCH_Pos

#define RADIO_INTENSET_BCMATCH_Pos   (10UL)

Position of BCMATCH field.

◆ RADIO_INTENSET_BCMATCH_Set

#define RADIO_INTENSET_BCMATCH_Set   (1UL)

Enable

◆ RADIO_INTENSET_CRCERROR_Disabled

#define RADIO_INTENSET_CRCERROR_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_CRCERROR_Enabled

#define RADIO_INTENSET_CRCERROR_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_CRCERROR_Msk

#define RADIO_INTENSET_CRCERROR_Msk   (0x1UL << RADIO_INTENSET_CRCERROR_Pos)

Bit mask of CRCERROR field.

◆ RADIO_INTENSET_CRCERROR_Pos

#define RADIO_INTENSET_CRCERROR_Pos   (13UL)

Position of CRCERROR field.

◆ RADIO_INTENSET_CRCERROR_Set

#define RADIO_INTENSET_CRCERROR_Set   (1UL)

Enable

◆ RADIO_INTENSET_CRCOK_Disabled

#define RADIO_INTENSET_CRCOK_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_CRCOK_Enabled

#define RADIO_INTENSET_CRCOK_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_CRCOK_Msk

#define RADIO_INTENSET_CRCOK_Msk   (0x1UL << RADIO_INTENSET_CRCOK_Pos)

Bit mask of CRCOK field.

◆ RADIO_INTENSET_CRCOK_Pos

#define RADIO_INTENSET_CRCOK_Pos   (12UL)

Position of CRCOK field.

◆ RADIO_INTENSET_CRCOK_Set

#define RADIO_INTENSET_CRCOK_Set   (1UL)

Enable

◆ RADIO_INTENSET_DEVMATCH_Disabled

#define RADIO_INTENSET_DEVMATCH_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_DEVMATCH_Enabled

#define RADIO_INTENSET_DEVMATCH_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_DEVMATCH_Msk

#define RADIO_INTENSET_DEVMATCH_Msk   (0x1UL << RADIO_INTENSET_DEVMATCH_Pos)

Bit mask of DEVMATCH field.

◆ RADIO_INTENSET_DEVMATCH_Pos

#define RADIO_INTENSET_DEVMATCH_Pos   (5UL)

Position of DEVMATCH field.

◆ RADIO_INTENSET_DEVMATCH_Set

#define RADIO_INTENSET_DEVMATCH_Set   (1UL)

Enable

◆ RADIO_INTENSET_DEVMISS_Disabled

#define RADIO_INTENSET_DEVMISS_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_DEVMISS_Enabled

#define RADIO_INTENSET_DEVMISS_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_DEVMISS_Msk

#define RADIO_INTENSET_DEVMISS_Msk   (0x1UL << RADIO_INTENSET_DEVMISS_Pos)

Bit mask of DEVMISS field.

◆ RADIO_INTENSET_DEVMISS_Pos

#define RADIO_INTENSET_DEVMISS_Pos   (6UL)

Position of DEVMISS field.

◆ RADIO_INTENSET_DEVMISS_Set

#define RADIO_INTENSET_DEVMISS_Set   (1UL)

Enable

◆ RADIO_INTENSET_DISABLED_Disabled

#define RADIO_INTENSET_DISABLED_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_DISABLED_Enabled

#define RADIO_INTENSET_DISABLED_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_DISABLED_Msk

#define RADIO_INTENSET_DISABLED_Msk   (0x1UL << RADIO_INTENSET_DISABLED_Pos)

Bit mask of DISABLED field.

◆ RADIO_INTENSET_DISABLED_Pos

#define RADIO_INTENSET_DISABLED_Pos   (4UL)

Position of DISABLED field.

◆ RADIO_INTENSET_DISABLED_Set

#define RADIO_INTENSET_DISABLED_Set   (1UL)

Enable

◆ RADIO_INTENSET_END_Disabled

#define RADIO_INTENSET_END_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_END_Enabled

#define RADIO_INTENSET_END_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_END_Msk

#define RADIO_INTENSET_END_Msk   (0x1UL << RADIO_INTENSET_END_Pos)

Bit mask of END field.

◆ RADIO_INTENSET_END_Pos

#define RADIO_INTENSET_END_Pos   (3UL)

Position of END field.

◆ RADIO_INTENSET_END_Set

#define RADIO_INTENSET_END_Set   (1UL)

Enable

◆ RADIO_INTENSET_PAYLOAD_Disabled

#define RADIO_INTENSET_PAYLOAD_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_PAYLOAD_Enabled

#define RADIO_INTENSET_PAYLOAD_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_PAYLOAD_Msk

#define RADIO_INTENSET_PAYLOAD_Msk   (0x1UL << RADIO_INTENSET_PAYLOAD_Pos)

Bit mask of PAYLOAD field.

◆ RADIO_INTENSET_PAYLOAD_Pos

#define RADIO_INTENSET_PAYLOAD_Pos   (2UL)

Position of PAYLOAD field.

◆ RADIO_INTENSET_PAYLOAD_Set

#define RADIO_INTENSET_PAYLOAD_Set   (1UL)

Enable

◆ RADIO_INTENSET_READY_Disabled

#define RADIO_INTENSET_READY_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_READY_Enabled

#define RADIO_INTENSET_READY_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_READY_Msk

#define RADIO_INTENSET_READY_Msk   (0x1UL << RADIO_INTENSET_READY_Pos)

Bit mask of READY field.

◆ RADIO_INTENSET_READY_Pos

#define RADIO_INTENSET_READY_Pos   (0UL)

Position of READY field.

◆ RADIO_INTENSET_READY_Set

#define RADIO_INTENSET_READY_Set   (1UL)

Enable

◆ RADIO_INTENSET_RSSIEND_Disabled

#define RADIO_INTENSET_RSSIEND_Disabled   (0UL)

Read: Disabled

◆ RADIO_INTENSET_RSSIEND_Enabled

#define RADIO_INTENSET_RSSIEND_Enabled   (1UL)

Read: Enabled

◆ RADIO_INTENSET_RSSIEND_Msk

#define RADIO_INTENSET_RSSIEND_Msk   (0x1UL << RADIO_INTENSET_RSSIEND_Pos)

Bit mask of RSSIEND field.

◆ RADIO_INTENSET_RSSIEND_Pos

#define RADIO_INTENSET_RSSIEND_Pos   (7UL)

Position of RSSIEND field.

◆ RADIO_INTENSET_RSSIEND_Set

#define RADIO_INTENSET_RSSIEND_Set   (1UL)

Enable

◆ RADIO_MODE_MODE_Ble_1Mbit

#define RADIO_MODE_MODE_Ble_1Mbit   (3UL)

1 Mbit/s Bluetooth Low Energy

◆ RADIO_MODE_MODE_Ble_2Mbit

#define RADIO_MODE_MODE_Ble_2Mbit   (4UL)

2 Mbit/s Bluetooth Low Energy

◆ RADIO_MODE_MODE_Msk

#define RADIO_MODE_MODE_Msk   (0xFUL << RADIO_MODE_MODE_Pos)

Bit mask of MODE field.

◆ RADIO_MODE_MODE_Nrf_1Mbit

#define RADIO_MODE_MODE_Nrf_1Mbit   (0UL)

1 Mbit/s Nordic proprietary radio mode

◆ RADIO_MODE_MODE_Nrf_250Kbit

#define RADIO_MODE_MODE_Nrf_250Kbit   (2UL)

Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode

◆ RADIO_MODE_MODE_Nrf_2Mbit

#define RADIO_MODE_MODE_Nrf_2Mbit   (1UL)

2 Mbit/s Nordic proprietary radio mode

◆ RADIO_MODE_MODE_Pos

#define RADIO_MODE_MODE_Pos   (0UL)

Position of MODE field.

◆ RADIO_MODECNF0_DTX_B0

#define RADIO_MODECNF0_DTX_B0   (1UL)

Transmit '0'

◆ RADIO_MODECNF0_DTX_B1

#define RADIO_MODECNF0_DTX_B1   (0UL)

Transmit '1'

◆ RADIO_MODECNF0_DTX_Center

#define RADIO_MODECNF0_DTX_Center   (2UL)

Transmit center frequency

◆ RADIO_MODECNF0_DTX_Msk

#define RADIO_MODECNF0_DTX_Msk   (0x3UL << RADIO_MODECNF0_DTX_Pos)

Bit mask of DTX field.

◆ RADIO_MODECNF0_DTX_Pos

#define RADIO_MODECNF0_DTX_Pos   (8UL)

Position of DTX field.

◆ RADIO_MODECNF0_RU_Default

#define RADIO_MODECNF0_RU_Default   (0UL)

Default ramp-up time (tRXEN), compatible with firmware written for nRF51

◆ RADIO_MODECNF0_RU_Fast

#define RADIO_MODECNF0_RU_Fast   (1UL)

Fast ramp-up (tRXEN,FAST), see electrical specification for more information

◆ RADIO_MODECNF0_RU_Msk

#define RADIO_MODECNF0_RU_Msk   (0x1UL << RADIO_MODECNF0_RU_Pos)

Bit mask of RU field.

◆ RADIO_MODECNF0_RU_Pos

#define RADIO_MODECNF0_RU_Pos   (0UL)

Position of RU field.

◆ RADIO_PACKETPTR_PACKETPTR_Msk

#define RADIO_PACKETPTR_PACKETPTR_Msk   (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos)

Bit mask of PACKETPTR field.

◆ RADIO_PACKETPTR_PACKETPTR_Pos

#define RADIO_PACKETPTR_PACKETPTR_Pos   (0UL)

Position of PACKETPTR field.

◆ RADIO_PCNF0_LFLEN_Msk

#define RADIO_PCNF0_LFLEN_Msk   (0xFUL << RADIO_PCNF0_LFLEN_Pos)

Bit mask of LFLEN field.

◆ RADIO_PCNF0_LFLEN_Pos

#define RADIO_PCNF0_LFLEN_Pos   (0UL)

Position of LFLEN field.

◆ RADIO_PCNF0_PLEN_16bit

#define RADIO_PCNF0_PLEN_16bit   (1UL)

16-bit preamble

◆ RADIO_PCNF0_PLEN_8bit

#define RADIO_PCNF0_PLEN_8bit   (0UL)

8-bit preamble

◆ RADIO_PCNF0_PLEN_Msk

#define RADIO_PCNF0_PLEN_Msk   (0x1UL << RADIO_PCNF0_PLEN_Pos)

Bit mask of PLEN field.

◆ RADIO_PCNF0_PLEN_Pos

#define RADIO_PCNF0_PLEN_Pos   (24UL)

Position of PLEN field.

◆ RADIO_PCNF0_S0LEN_Msk

#define RADIO_PCNF0_S0LEN_Msk   (0x1UL << RADIO_PCNF0_S0LEN_Pos)

Bit mask of S0LEN field.

◆ RADIO_PCNF0_S0LEN_Pos

#define RADIO_PCNF0_S0LEN_Pos   (8UL)

Position of S0LEN field.

◆ RADIO_PCNF0_S1INCL_Automatic

#define RADIO_PCNF0_S1INCL_Automatic   (0UL)

Include S1 field in RAM only if S1LEN > 0

◆ RADIO_PCNF0_S1INCL_Include

#define RADIO_PCNF0_S1INCL_Include   (1UL)

Always include S1 field in RAM independent of S1LEN

◆ RADIO_PCNF0_S1INCL_Msk

#define RADIO_PCNF0_S1INCL_Msk   (0x1UL << RADIO_PCNF0_S1INCL_Pos)

Bit mask of S1INCL field.

◆ RADIO_PCNF0_S1INCL_Pos

#define RADIO_PCNF0_S1INCL_Pos   (20UL)

Position of S1INCL field.

◆ RADIO_PCNF0_S1LEN_Msk

#define RADIO_PCNF0_S1LEN_Msk   (0xFUL << RADIO_PCNF0_S1LEN_Pos)

Bit mask of S1LEN field.

◆ RADIO_PCNF0_S1LEN_Pos

#define RADIO_PCNF0_S1LEN_Pos   (16UL)

Position of S1LEN field.

◆ RADIO_PCNF1_BALEN_Msk

#define RADIO_PCNF1_BALEN_Msk   (0x7UL << RADIO_PCNF1_BALEN_Pos)

Bit mask of BALEN field.

◆ RADIO_PCNF1_BALEN_Pos

#define RADIO_PCNF1_BALEN_Pos   (16UL)

Position of BALEN field.

◆ RADIO_PCNF1_ENDIAN_Big

#define RADIO_PCNF1_ENDIAN_Big   (1UL)

Most significant bit on air first

◆ RADIO_PCNF1_ENDIAN_Little

#define RADIO_PCNF1_ENDIAN_Little   (0UL)

Least Significant bit on air first

◆ RADIO_PCNF1_ENDIAN_Msk

#define RADIO_PCNF1_ENDIAN_Msk   (0x1UL << RADIO_PCNF1_ENDIAN_Pos)

Bit mask of ENDIAN field.

◆ RADIO_PCNF1_ENDIAN_Pos

#define RADIO_PCNF1_ENDIAN_Pos   (24UL)

Position of ENDIAN field.

◆ RADIO_PCNF1_MAXLEN_Msk

#define RADIO_PCNF1_MAXLEN_Msk   (0xFFUL << RADIO_PCNF1_MAXLEN_Pos)

Bit mask of MAXLEN field.

◆ RADIO_PCNF1_MAXLEN_Pos

#define RADIO_PCNF1_MAXLEN_Pos   (0UL)

Position of MAXLEN field.

◆ RADIO_PCNF1_STATLEN_Msk

#define RADIO_PCNF1_STATLEN_Msk   (0xFFUL << RADIO_PCNF1_STATLEN_Pos)

Bit mask of STATLEN field.

◆ RADIO_PCNF1_STATLEN_Pos

#define RADIO_PCNF1_STATLEN_Pos   (8UL)

Position of STATLEN field.

◆ RADIO_PCNF1_WHITEEN_Disabled

#define RADIO_PCNF1_WHITEEN_Disabled   (0UL)

Disable

◆ RADIO_PCNF1_WHITEEN_Enabled

#define RADIO_PCNF1_WHITEEN_Enabled   (1UL)

Enable

◆ RADIO_PCNF1_WHITEEN_Msk

#define RADIO_PCNF1_WHITEEN_Msk   (0x1UL << RADIO_PCNF1_WHITEEN_Pos)

Bit mask of WHITEEN field.

◆ RADIO_PCNF1_WHITEEN_Pos

#define RADIO_PCNF1_WHITEEN_Pos   (25UL)

Position of WHITEEN field.

◆ RADIO_POWER_POWER_Disabled

#define RADIO_POWER_POWER_Disabled   (0UL)

Peripheral is powered off

◆ RADIO_POWER_POWER_Enabled

#define RADIO_POWER_POWER_Enabled   (1UL)

Peripheral is powered on

◆ RADIO_POWER_POWER_Msk

#define RADIO_POWER_POWER_Msk   (0x1UL << RADIO_POWER_POWER_Pos)

Bit mask of POWER field.

◆ RADIO_POWER_POWER_Pos

#define RADIO_POWER_POWER_Pos   (0UL)

Position of POWER field.

◆ RADIO_PREFIX0_AP0_Msk

#define RADIO_PREFIX0_AP0_Msk   (0xFFUL << RADIO_PREFIX0_AP0_Pos)

Bit mask of AP0 field.

◆ RADIO_PREFIX0_AP0_Pos

#define RADIO_PREFIX0_AP0_Pos   (0UL)

Position of AP0 field.

◆ RADIO_PREFIX0_AP1_Msk

#define RADIO_PREFIX0_AP1_Msk   (0xFFUL << RADIO_PREFIX0_AP1_Pos)

Bit mask of AP1 field.

◆ RADIO_PREFIX0_AP1_Pos

#define RADIO_PREFIX0_AP1_Pos   (8UL)

Position of AP1 field.

◆ RADIO_PREFIX0_AP2_Msk

#define RADIO_PREFIX0_AP2_Msk   (0xFFUL << RADIO_PREFIX0_AP2_Pos)

Bit mask of AP2 field.

◆ RADIO_PREFIX0_AP2_Pos

#define RADIO_PREFIX0_AP2_Pos   (16UL)

Position of AP2 field.

◆ RADIO_PREFIX0_AP3_Msk

#define RADIO_PREFIX0_AP3_Msk   (0xFFUL << RADIO_PREFIX0_AP3_Pos)

Bit mask of AP3 field.

◆ RADIO_PREFIX0_AP3_Pos

#define RADIO_PREFIX0_AP3_Pos   (24UL)

Position of AP3 field.

◆ RADIO_PREFIX1_AP4_Msk

#define RADIO_PREFIX1_AP4_Msk   (0xFFUL << RADIO_PREFIX1_AP4_Pos)

Bit mask of AP4 field.

◆ RADIO_PREFIX1_AP4_Pos

#define RADIO_PREFIX1_AP4_Pos   (0UL)

Position of AP4 field.

◆ RADIO_PREFIX1_AP5_Msk

#define RADIO_PREFIX1_AP5_Msk   (0xFFUL << RADIO_PREFIX1_AP5_Pos)

Bit mask of AP5 field.

◆ RADIO_PREFIX1_AP5_Pos

#define RADIO_PREFIX1_AP5_Pos   (8UL)

Position of AP5 field.

◆ RADIO_PREFIX1_AP6_Msk

#define RADIO_PREFIX1_AP6_Msk   (0xFFUL << RADIO_PREFIX1_AP6_Pos)

Bit mask of AP6 field.

◆ RADIO_PREFIX1_AP6_Pos

#define RADIO_PREFIX1_AP6_Pos   (16UL)

Position of AP6 field.

◆ RADIO_PREFIX1_AP7_Msk

#define RADIO_PREFIX1_AP7_Msk   (0xFFUL << RADIO_PREFIX1_AP7_Pos)

Bit mask of AP7 field.

◆ RADIO_PREFIX1_AP7_Pos

#define RADIO_PREFIX1_AP7_Pos   (24UL)

Position of AP7 field.

◆ RADIO_RSSISAMPLE_RSSISAMPLE_Msk

#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk   (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos)

Bit mask of RSSISAMPLE field.

◆ RADIO_RSSISAMPLE_RSSISAMPLE_Pos

#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos   (0UL)

Position of RSSISAMPLE field.

◆ RADIO_RXADDRESSES_ADDR0_Disabled

#define RADIO_RXADDRESSES_ADDR0_Disabled   (0UL)

Disable

◆ RADIO_RXADDRESSES_ADDR0_Enabled

#define RADIO_RXADDRESSES_ADDR0_Enabled   (1UL)

Enable

◆ RADIO_RXADDRESSES_ADDR0_Msk

#define RADIO_RXADDRESSES_ADDR0_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos)

Bit mask of ADDR0 field.

◆ RADIO_RXADDRESSES_ADDR0_Pos

#define RADIO_RXADDRESSES_ADDR0_Pos   (0UL)

Position of ADDR0 field.

◆ RADIO_RXADDRESSES_ADDR1_Disabled

#define RADIO_RXADDRESSES_ADDR1_Disabled   (0UL)

Disable

◆ RADIO_RXADDRESSES_ADDR1_Enabled

#define RADIO_RXADDRESSES_ADDR1_Enabled   (1UL)

Enable

◆ RADIO_RXADDRESSES_ADDR1_Msk

#define RADIO_RXADDRESSES_ADDR1_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos)

Bit mask of ADDR1 field.

◆ RADIO_RXADDRESSES_ADDR1_Pos

#define RADIO_RXADDRESSES_ADDR1_Pos   (1UL)

Position of ADDR1 field.

◆ RADIO_RXADDRESSES_ADDR2_Disabled

#define RADIO_RXADDRESSES_ADDR2_Disabled   (0UL)

Disable

◆ RADIO_RXADDRESSES_ADDR2_Enabled

#define RADIO_RXADDRESSES_ADDR2_Enabled   (1UL)

Enable

◆ RADIO_RXADDRESSES_ADDR2_Msk

#define RADIO_RXADDRESSES_ADDR2_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos)

Bit mask of ADDR2 field.

◆ RADIO_RXADDRESSES_ADDR2_Pos

#define RADIO_RXADDRESSES_ADDR2_Pos   (2UL)

Position of ADDR2 field.

◆ RADIO_RXADDRESSES_ADDR3_Disabled

#define RADIO_RXADDRESSES_ADDR3_Disabled   (0UL)

Disable

◆ RADIO_RXADDRESSES_ADDR3_Enabled

#define RADIO_RXADDRESSES_ADDR3_Enabled   (1UL)

Enable

◆ RADIO_RXADDRESSES_ADDR3_Msk

#define RADIO_RXADDRESSES_ADDR3_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos)

Bit mask of ADDR3 field.

◆ RADIO_RXADDRESSES_ADDR3_Pos

#define RADIO_RXADDRESSES_ADDR3_Pos   (3UL)

Position of ADDR3 field.

◆ RADIO_RXADDRESSES_ADDR4_Disabled

#define RADIO_RXADDRESSES_ADDR4_Disabled   (0UL)

Disable

◆ RADIO_RXADDRESSES_ADDR4_Enabled

#define RADIO_RXADDRESSES_ADDR4_Enabled   (1UL)

Enable

◆ RADIO_RXADDRESSES_ADDR4_Msk

#define RADIO_RXADDRESSES_ADDR4_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos)

Bit mask of ADDR4 field.

◆ RADIO_RXADDRESSES_ADDR4_Pos

#define RADIO_RXADDRESSES_ADDR4_Pos   (4UL)

Position of ADDR4 field.

◆ RADIO_RXADDRESSES_ADDR5_Disabled

#define RADIO_RXADDRESSES_ADDR5_Disabled   (0UL)

Disable

◆ RADIO_RXADDRESSES_ADDR5_Enabled

#define RADIO_RXADDRESSES_ADDR5_Enabled   (1UL)

Enable

◆ RADIO_RXADDRESSES_ADDR5_Msk

#define RADIO_RXADDRESSES_ADDR5_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos)

Bit mask of ADDR5 field.

◆ RADIO_RXADDRESSES_ADDR5_Pos

#define RADIO_RXADDRESSES_ADDR5_Pos   (5UL)

Position of ADDR5 field.

◆ RADIO_RXADDRESSES_ADDR6_Disabled

#define RADIO_RXADDRESSES_ADDR6_Disabled   (0UL)

Disable

◆ RADIO_RXADDRESSES_ADDR6_Enabled

#define RADIO_RXADDRESSES_ADDR6_Enabled   (1UL)

Enable

◆ RADIO_RXADDRESSES_ADDR6_Msk

#define RADIO_RXADDRESSES_ADDR6_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos)

Bit mask of ADDR6 field.

◆ RADIO_RXADDRESSES_ADDR6_Pos

#define RADIO_RXADDRESSES_ADDR6_Pos   (6UL)

Position of ADDR6 field.

◆ RADIO_RXADDRESSES_ADDR7_Disabled

#define RADIO_RXADDRESSES_ADDR7_Disabled   (0UL)

Disable

◆ RADIO_RXADDRESSES_ADDR7_Enabled

#define RADIO_RXADDRESSES_ADDR7_Enabled   (1UL)

Enable

◆ RADIO_RXADDRESSES_ADDR7_Msk

#define RADIO_RXADDRESSES_ADDR7_Msk   (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos)

Bit mask of ADDR7 field.

◆ RADIO_RXADDRESSES_ADDR7_Pos

#define RADIO_RXADDRESSES_ADDR7_Pos   (7UL)

Position of ADDR7 field.

◆ RADIO_RXCRC_RXCRC_Msk

#define RADIO_RXCRC_RXCRC_Msk   (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos)

Bit mask of RXCRC field.

◆ RADIO_RXCRC_RXCRC_Pos

#define RADIO_RXCRC_RXCRC_Pos   (0UL)

Position of RXCRC field.

◆ RADIO_RXMATCH_RXMATCH_Msk

#define RADIO_RXMATCH_RXMATCH_Msk   (0x7UL << RADIO_RXMATCH_RXMATCH_Pos)

Bit mask of RXMATCH field.

◆ RADIO_RXMATCH_RXMATCH_Pos

#define RADIO_RXMATCH_RXMATCH_Pos   (0UL)

Position of RXMATCH field.

◆ RADIO_SHORTS_ADDRESS_BCSTART_Disabled

#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled   (0UL)

Disable shortcut

◆ RADIO_SHORTS_ADDRESS_BCSTART_Enabled

#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled   (1UL)

Enable shortcut

◆ RADIO_SHORTS_ADDRESS_BCSTART_Msk

#define RADIO_SHORTS_ADDRESS_BCSTART_Msk   (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos)

Bit mask of ADDRESS_BCSTART field.

◆ RADIO_SHORTS_ADDRESS_BCSTART_Pos

#define RADIO_SHORTS_ADDRESS_BCSTART_Pos   (6UL)

Position of ADDRESS_BCSTART field.

◆ RADIO_SHORTS_ADDRESS_RSSISTART_Disabled

#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled   (0UL)

Disable shortcut

◆ RADIO_SHORTS_ADDRESS_RSSISTART_Enabled

#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled   (1UL)

Enable shortcut

◆ RADIO_SHORTS_ADDRESS_RSSISTART_Msk

#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk   (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos)

Bit mask of ADDRESS_RSSISTART field.

◆ RADIO_SHORTS_ADDRESS_RSSISTART_Pos

#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos   (4UL)

Position of ADDRESS_RSSISTART field.

◆ RADIO_SHORTS_DISABLED_RSSISTOP_Disabled

#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled   (0UL)

Disable shortcut

◆ RADIO_SHORTS_DISABLED_RSSISTOP_Enabled

#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled   (1UL)

Enable shortcut

◆ RADIO_SHORTS_DISABLED_RSSISTOP_Msk

#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk   (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos)

Bit mask of DISABLED_RSSISTOP field.

◆ RADIO_SHORTS_DISABLED_RSSISTOP_Pos

#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos   (8UL)

Position of DISABLED_RSSISTOP field.

◆ RADIO_SHORTS_DISABLED_RXEN_Disabled

#define RADIO_SHORTS_DISABLED_RXEN_Disabled   (0UL)

Disable shortcut

◆ RADIO_SHORTS_DISABLED_RXEN_Enabled

#define RADIO_SHORTS_DISABLED_RXEN_Enabled   (1UL)

Enable shortcut

◆ RADIO_SHORTS_DISABLED_RXEN_Msk

#define RADIO_SHORTS_DISABLED_RXEN_Msk   (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos)

Bit mask of DISABLED_RXEN field.

◆ RADIO_SHORTS_DISABLED_RXEN_Pos

#define RADIO_SHORTS_DISABLED_RXEN_Pos   (3UL)

Position of DISABLED_RXEN field.

◆ RADIO_SHORTS_DISABLED_TXEN_Disabled

#define RADIO_SHORTS_DISABLED_TXEN_Disabled   (0UL)

Disable shortcut

◆ RADIO_SHORTS_DISABLED_TXEN_Enabled

#define RADIO_SHORTS_DISABLED_TXEN_Enabled   (1UL)

Enable shortcut

◆ RADIO_SHORTS_DISABLED_TXEN_Msk

#define RADIO_SHORTS_DISABLED_TXEN_Msk   (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos)

Bit mask of DISABLED_TXEN field.

◆ RADIO_SHORTS_DISABLED_TXEN_Pos

#define RADIO_SHORTS_DISABLED_TXEN_Pos   (2UL)

Position of DISABLED_TXEN field.

◆ RADIO_SHORTS_END_DISABLE_Disabled

#define RADIO_SHORTS_END_DISABLE_Disabled   (0UL)

Disable shortcut

◆ RADIO_SHORTS_END_DISABLE_Enabled

#define RADIO_SHORTS_END_DISABLE_Enabled   (1UL)

Enable shortcut

◆ RADIO_SHORTS_END_DISABLE_Msk

#define RADIO_SHORTS_END_DISABLE_Msk   (0x1UL << RADIO_SHORTS_END_DISABLE_Pos)

Bit mask of END_DISABLE field.

◆ RADIO_SHORTS_END_DISABLE_Pos

#define RADIO_SHORTS_END_DISABLE_Pos   (1UL)

Position of END_DISABLE field.

◆ RADIO_SHORTS_END_START_Disabled

#define RADIO_SHORTS_END_START_Disabled   (0UL)

Disable shortcut

◆ RADIO_SHORTS_END_START_Enabled

#define RADIO_SHORTS_END_START_Enabled   (1UL)

Enable shortcut

◆ RADIO_SHORTS_END_START_Msk

#define RADIO_SHORTS_END_START_Msk   (0x1UL << RADIO_SHORTS_END_START_Pos)

Bit mask of END_START field.

◆ RADIO_SHORTS_END_START_Pos

#define RADIO_SHORTS_END_START_Pos   (5UL)

Position of END_START field.

◆ RADIO_SHORTS_READY_START_Disabled

#define RADIO_SHORTS_READY_START_Disabled   (0UL)

Disable shortcut

◆ RADIO_SHORTS_READY_START_Enabled

#define RADIO_SHORTS_READY_START_Enabled   (1UL)

Enable shortcut

◆ RADIO_SHORTS_READY_START_Msk

#define RADIO_SHORTS_READY_START_Msk   (0x1UL << RADIO_SHORTS_READY_START_Pos)

Bit mask of READY_START field.

◆ RADIO_SHORTS_READY_START_Pos

#define RADIO_SHORTS_READY_START_Pos   (0UL)

Position of READY_START field.

◆ RADIO_STATE_STATE_Disabled

#define RADIO_STATE_STATE_Disabled   (0UL)

RADIO is in the Disabled state

◆ RADIO_STATE_STATE_Msk

#define RADIO_STATE_STATE_Msk   (0xFUL << RADIO_STATE_STATE_Pos)

Bit mask of STATE field.

◆ RADIO_STATE_STATE_Pos

#define RADIO_STATE_STATE_Pos   (0UL)

Position of STATE field.

◆ RADIO_STATE_STATE_Rx

#define RADIO_STATE_STATE_Rx   (3UL)

RADIO is in the RX state

◆ RADIO_STATE_STATE_RxDisable

#define RADIO_STATE_STATE_RxDisable   (4UL)

RADIO is in the RXDISABLED state

◆ RADIO_STATE_STATE_RxIdle

#define RADIO_STATE_STATE_RxIdle   (2UL)

RADIO is in the RXIDLE state

◆ RADIO_STATE_STATE_RxRu

#define RADIO_STATE_STATE_RxRu   (1UL)

RADIO is in the RXRU state

◆ RADIO_STATE_STATE_Tx

#define RADIO_STATE_STATE_Tx   (11UL)

RADIO is in the TX state

◆ RADIO_STATE_STATE_TxDisable

#define RADIO_STATE_STATE_TxDisable   (12UL)

RADIO is in the TXDISABLED state

◆ RADIO_STATE_STATE_TxIdle

#define RADIO_STATE_STATE_TxIdle   (10UL)

RADIO is in the TXIDLE state

◆ RADIO_STATE_STATE_TxRu

#define RADIO_STATE_STATE_TxRu   (9UL)

RADIO is in the TXRU state

◆ RADIO_TIFS_TIFS_Msk

#define RADIO_TIFS_TIFS_Msk   (0xFFUL << RADIO_TIFS_TIFS_Pos)

Bit mask of TIFS field.

◆ RADIO_TIFS_TIFS_Pos

#define RADIO_TIFS_TIFS_Pos   (0UL)

Position of TIFS field.

◆ RADIO_TXADDRESS_TXADDRESS_Msk

#define RADIO_TXADDRESS_TXADDRESS_Msk   (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos)

Bit mask of TXADDRESS field.

◆ RADIO_TXADDRESS_TXADDRESS_Pos

#define RADIO_TXADDRESS_TXADDRESS_Pos   (0UL)

Position of TXADDRESS field.

◆ RADIO_TXPOWER_TXPOWER_0dBm

#define RADIO_TXPOWER_TXPOWER_0dBm   (0x00UL)

0 dBm

◆ RADIO_TXPOWER_TXPOWER_Msk

#define RADIO_TXPOWER_TXPOWER_Msk   (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos)

Bit mask of TXPOWER field.

◆ RADIO_TXPOWER_TXPOWER_Neg12dBm

#define RADIO_TXPOWER_TXPOWER_Neg12dBm   (0xF4UL)

-12 dBm

◆ RADIO_TXPOWER_TXPOWER_Neg16dBm

#define RADIO_TXPOWER_TXPOWER_Neg16dBm   (0xF0UL)

-16 dBm

◆ RADIO_TXPOWER_TXPOWER_Neg20dBm

#define RADIO_TXPOWER_TXPOWER_Neg20dBm   (0xECUL)

-20 dBm

◆ RADIO_TXPOWER_TXPOWER_Neg30dBm

#define RADIO_TXPOWER_TXPOWER_Neg30dBm   (0xFFUL)

Deprecated enumerator - -40 dBm

◆ RADIO_TXPOWER_TXPOWER_Neg40dBm

#define RADIO_TXPOWER_TXPOWER_Neg40dBm   (0xD8UL)

-40 dBm

◆ RADIO_TXPOWER_TXPOWER_Neg4dBm

#define RADIO_TXPOWER_TXPOWER_Neg4dBm   (0xFCUL)

-4 dBm

◆ RADIO_TXPOWER_TXPOWER_Neg8dBm

#define RADIO_TXPOWER_TXPOWER_Neg8dBm   (0xF8UL)

-8 dBm

◆ RADIO_TXPOWER_TXPOWER_Pos

#define RADIO_TXPOWER_TXPOWER_Pos   (0UL)

Position of TXPOWER field.

◆ RADIO_TXPOWER_TXPOWER_Pos3dBm

#define RADIO_TXPOWER_TXPOWER_Pos3dBm   (0x03UL)

+3 dBm

◆ RADIO_TXPOWER_TXPOWER_Pos4dBm

#define RADIO_TXPOWER_TXPOWER_Pos4dBm   (0x04UL)

+4 dBm

◆ RNG_CONFIG_DERCEN_Disabled

#define RNG_CONFIG_DERCEN_Disabled   (0UL)

Disabled

◆ RNG_CONFIG_DERCEN_Enabled

#define RNG_CONFIG_DERCEN_Enabled   (1UL)

Enabled

◆ RNG_CONFIG_DERCEN_Msk

#define RNG_CONFIG_DERCEN_Msk   (0x1UL << RNG_CONFIG_DERCEN_Pos)

Bit mask of DERCEN field.

◆ RNG_CONFIG_DERCEN_Pos

#define RNG_CONFIG_DERCEN_Pos   (0UL)

Position of DERCEN field.

◆ RNG_INTENCLR_VALRDY_Clear

#define RNG_INTENCLR_VALRDY_Clear   (1UL)

Disable

◆ RNG_INTENCLR_VALRDY_Disabled

#define RNG_INTENCLR_VALRDY_Disabled   (0UL)

Read: Disabled

◆ RNG_INTENCLR_VALRDY_Enabled

#define RNG_INTENCLR_VALRDY_Enabled   (1UL)

Read: Enabled

◆ RNG_INTENCLR_VALRDY_Msk

#define RNG_INTENCLR_VALRDY_Msk   (0x1UL << RNG_INTENCLR_VALRDY_Pos)

Bit mask of VALRDY field.

◆ RNG_INTENCLR_VALRDY_Pos

#define RNG_INTENCLR_VALRDY_Pos   (0UL)

Position of VALRDY field.

◆ RNG_INTENSET_VALRDY_Disabled

#define RNG_INTENSET_VALRDY_Disabled   (0UL)

Read: Disabled

◆ RNG_INTENSET_VALRDY_Enabled

#define RNG_INTENSET_VALRDY_Enabled   (1UL)

Read: Enabled

◆ RNG_INTENSET_VALRDY_Msk

#define RNG_INTENSET_VALRDY_Msk   (0x1UL << RNG_INTENSET_VALRDY_Pos)

Bit mask of VALRDY field.

◆ RNG_INTENSET_VALRDY_Pos

#define RNG_INTENSET_VALRDY_Pos   (0UL)

Position of VALRDY field.

◆ RNG_INTENSET_VALRDY_Set

#define RNG_INTENSET_VALRDY_Set   (1UL)

Enable

◆ RNG_SHORTS_VALRDY_STOP_Disabled

#define RNG_SHORTS_VALRDY_STOP_Disabled   (0UL)

Disable shortcut

◆ RNG_SHORTS_VALRDY_STOP_Enabled

#define RNG_SHORTS_VALRDY_STOP_Enabled   (1UL)

Enable shortcut

◆ RNG_SHORTS_VALRDY_STOP_Msk

#define RNG_SHORTS_VALRDY_STOP_Msk   (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos)

Bit mask of VALRDY_STOP field.

◆ RNG_SHORTS_VALRDY_STOP_Pos

#define RNG_SHORTS_VALRDY_STOP_Pos   (0UL)

Position of VALRDY_STOP field.

◆ RNG_VALUE_VALUE_Msk

#define RNG_VALUE_VALUE_Msk   (0xFFUL << RNG_VALUE_VALUE_Pos)

Bit mask of VALUE field.

◆ RNG_VALUE_VALUE_Pos

#define RNG_VALUE_VALUE_Pos   (0UL)

Position of VALUE field.

◆ RTC_CC_COMPARE_Msk

#define RTC_CC_COMPARE_Msk   (0xFFFFFFUL << RTC_CC_COMPARE_Pos)

Bit mask of COMPARE field.

◆ RTC_CC_COMPARE_Pos

#define RTC_CC_COMPARE_Pos   (0UL)

Position of COMPARE field.

◆ RTC_COUNTER_COUNTER_Msk

#define RTC_COUNTER_COUNTER_Msk   (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos)

Bit mask of COUNTER field.

◆ RTC_COUNTER_COUNTER_Pos

#define RTC_COUNTER_COUNTER_Pos   (0UL)

Position of COUNTER field.

◆ RTC_EVTEN_COMPARE0_Disabled

#define RTC_EVTEN_COMPARE0_Disabled   (0UL)

Disable

◆ RTC_EVTEN_COMPARE0_Enabled

#define RTC_EVTEN_COMPARE0_Enabled   (1UL)

Enable

◆ RTC_EVTEN_COMPARE0_Msk

#define RTC_EVTEN_COMPARE0_Msk   (0x1UL << RTC_EVTEN_COMPARE0_Pos)

Bit mask of COMPARE0 field.

◆ RTC_EVTEN_COMPARE0_Pos

#define RTC_EVTEN_COMPARE0_Pos   (16UL)

Position of COMPARE0 field.

◆ RTC_EVTEN_COMPARE1_Disabled

#define RTC_EVTEN_COMPARE1_Disabled   (0UL)

Disable

◆ RTC_EVTEN_COMPARE1_Enabled

#define RTC_EVTEN_COMPARE1_Enabled   (1UL)

Enable

◆ RTC_EVTEN_COMPARE1_Msk

#define RTC_EVTEN_COMPARE1_Msk   (0x1UL << RTC_EVTEN_COMPARE1_Pos)

Bit mask of COMPARE1 field.

◆ RTC_EVTEN_COMPARE1_Pos

#define RTC_EVTEN_COMPARE1_Pos   (17UL)

Position of COMPARE1 field.

◆ RTC_EVTEN_COMPARE2_Disabled

#define RTC_EVTEN_COMPARE2_Disabled   (0UL)

Disable

◆ RTC_EVTEN_COMPARE2_Enabled

#define RTC_EVTEN_COMPARE2_Enabled   (1UL)

Enable

◆ RTC_EVTEN_COMPARE2_Msk

#define RTC_EVTEN_COMPARE2_Msk   (0x1UL << RTC_EVTEN_COMPARE2_Pos)

Bit mask of COMPARE2 field.

◆ RTC_EVTEN_COMPARE2_Pos

#define RTC_EVTEN_COMPARE2_Pos   (18UL)

Position of COMPARE2 field.

◆ RTC_EVTEN_COMPARE3_Disabled

#define RTC_EVTEN_COMPARE3_Disabled   (0UL)

Disable

◆ RTC_EVTEN_COMPARE3_Enabled

#define RTC_EVTEN_COMPARE3_Enabled   (1UL)

Enable

◆ RTC_EVTEN_COMPARE3_Msk

#define RTC_EVTEN_COMPARE3_Msk   (0x1UL << RTC_EVTEN_COMPARE3_Pos)

Bit mask of COMPARE3 field.

◆ RTC_EVTEN_COMPARE3_Pos

#define RTC_EVTEN_COMPARE3_Pos   (19UL)

Position of COMPARE3 field.

◆ RTC_EVTEN_OVRFLW_Disabled

#define RTC_EVTEN_OVRFLW_Disabled   (0UL)

Disable

◆ RTC_EVTEN_OVRFLW_Enabled

#define RTC_EVTEN_OVRFLW_Enabled   (1UL)

Enable

◆ RTC_EVTEN_OVRFLW_Msk

#define RTC_EVTEN_OVRFLW_Msk   (0x1UL << RTC_EVTEN_OVRFLW_Pos)

Bit mask of OVRFLW field.

◆ RTC_EVTEN_OVRFLW_Pos

#define RTC_EVTEN_OVRFLW_Pos   (1UL)

Position of OVRFLW field.

◆ RTC_EVTEN_TICK_Disabled

#define RTC_EVTEN_TICK_Disabled   (0UL)

Disable

◆ RTC_EVTEN_TICK_Enabled

#define RTC_EVTEN_TICK_Enabled   (1UL)

Enable

◆ RTC_EVTEN_TICK_Msk

#define RTC_EVTEN_TICK_Msk   (0x1UL << RTC_EVTEN_TICK_Pos)

Bit mask of TICK field.

◆ RTC_EVTEN_TICK_Pos

#define RTC_EVTEN_TICK_Pos   (0UL)

Position of TICK field.

◆ RTC_EVTENCLR_COMPARE0_Clear

#define RTC_EVTENCLR_COMPARE0_Clear   (1UL)

Disable

◆ RTC_EVTENCLR_COMPARE0_Disabled

#define RTC_EVTENCLR_COMPARE0_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENCLR_COMPARE0_Enabled

#define RTC_EVTENCLR_COMPARE0_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENCLR_COMPARE0_Msk

#define RTC_EVTENCLR_COMPARE0_Msk   (0x1UL << RTC_EVTENCLR_COMPARE0_Pos)

Bit mask of COMPARE0 field.

◆ RTC_EVTENCLR_COMPARE0_Pos

#define RTC_EVTENCLR_COMPARE0_Pos   (16UL)

Position of COMPARE0 field.

◆ RTC_EVTENCLR_COMPARE1_Clear

#define RTC_EVTENCLR_COMPARE1_Clear   (1UL)

Disable

◆ RTC_EVTENCLR_COMPARE1_Disabled

#define RTC_EVTENCLR_COMPARE1_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENCLR_COMPARE1_Enabled

#define RTC_EVTENCLR_COMPARE1_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENCLR_COMPARE1_Msk

#define RTC_EVTENCLR_COMPARE1_Msk   (0x1UL << RTC_EVTENCLR_COMPARE1_Pos)

Bit mask of COMPARE1 field.

◆ RTC_EVTENCLR_COMPARE1_Pos

#define RTC_EVTENCLR_COMPARE1_Pos   (17UL)

Position of COMPARE1 field.

◆ RTC_EVTENCLR_COMPARE2_Clear

#define RTC_EVTENCLR_COMPARE2_Clear   (1UL)

Disable

◆ RTC_EVTENCLR_COMPARE2_Disabled

#define RTC_EVTENCLR_COMPARE2_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENCLR_COMPARE2_Enabled

#define RTC_EVTENCLR_COMPARE2_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENCLR_COMPARE2_Msk

#define RTC_EVTENCLR_COMPARE2_Msk   (0x1UL << RTC_EVTENCLR_COMPARE2_Pos)

Bit mask of COMPARE2 field.

◆ RTC_EVTENCLR_COMPARE2_Pos

#define RTC_EVTENCLR_COMPARE2_Pos   (18UL)

Position of COMPARE2 field.

◆ RTC_EVTENCLR_COMPARE3_Clear

#define RTC_EVTENCLR_COMPARE3_Clear   (1UL)

Disable

◆ RTC_EVTENCLR_COMPARE3_Disabled

#define RTC_EVTENCLR_COMPARE3_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENCLR_COMPARE3_Enabled

#define RTC_EVTENCLR_COMPARE3_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENCLR_COMPARE3_Msk

#define RTC_EVTENCLR_COMPARE3_Msk   (0x1UL << RTC_EVTENCLR_COMPARE3_Pos)

Bit mask of COMPARE3 field.

◆ RTC_EVTENCLR_COMPARE3_Pos

#define RTC_EVTENCLR_COMPARE3_Pos   (19UL)

Position of COMPARE3 field.

◆ RTC_EVTENCLR_OVRFLW_Clear

#define RTC_EVTENCLR_OVRFLW_Clear   (1UL)

Disable

◆ RTC_EVTENCLR_OVRFLW_Disabled

#define RTC_EVTENCLR_OVRFLW_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENCLR_OVRFLW_Enabled

#define RTC_EVTENCLR_OVRFLW_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENCLR_OVRFLW_Msk

#define RTC_EVTENCLR_OVRFLW_Msk   (0x1UL << RTC_EVTENCLR_OVRFLW_Pos)

Bit mask of OVRFLW field.

◆ RTC_EVTENCLR_OVRFLW_Pos

#define RTC_EVTENCLR_OVRFLW_Pos   (1UL)

Position of OVRFLW field.

◆ RTC_EVTENCLR_TICK_Clear

#define RTC_EVTENCLR_TICK_Clear   (1UL)

Disable

◆ RTC_EVTENCLR_TICK_Disabled

#define RTC_EVTENCLR_TICK_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENCLR_TICK_Enabled

#define RTC_EVTENCLR_TICK_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENCLR_TICK_Msk

#define RTC_EVTENCLR_TICK_Msk   (0x1UL << RTC_EVTENCLR_TICK_Pos)

Bit mask of TICK field.

◆ RTC_EVTENCLR_TICK_Pos

#define RTC_EVTENCLR_TICK_Pos   (0UL)

Position of TICK field.

◆ RTC_EVTENSET_COMPARE0_Disabled

#define RTC_EVTENSET_COMPARE0_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENSET_COMPARE0_Enabled

#define RTC_EVTENSET_COMPARE0_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENSET_COMPARE0_Msk

#define RTC_EVTENSET_COMPARE0_Msk   (0x1UL << RTC_EVTENSET_COMPARE0_Pos)

Bit mask of COMPARE0 field.

◆ RTC_EVTENSET_COMPARE0_Pos

#define RTC_EVTENSET_COMPARE0_Pos   (16UL)

Position of COMPARE0 field.

◆ RTC_EVTENSET_COMPARE0_Set

#define RTC_EVTENSET_COMPARE0_Set   (1UL)

Enable

◆ RTC_EVTENSET_COMPARE1_Disabled

#define RTC_EVTENSET_COMPARE1_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENSET_COMPARE1_Enabled

#define RTC_EVTENSET_COMPARE1_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENSET_COMPARE1_Msk

#define RTC_EVTENSET_COMPARE1_Msk   (0x1UL << RTC_EVTENSET_COMPARE1_Pos)

Bit mask of COMPARE1 field.

◆ RTC_EVTENSET_COMPARE1_Pos

#define RTC_EVTENSET_COMPARE1_Pos   (17UL)

Position of COMPARE1 field.

◆ RTC_EVTENSET_COMPARE1_Set

#define RTC_EVTENSET_COMPARE1_Set   (1UL)

Enable

◆ RTC_EVTENSET_COMPARE2_Disabled

#define RTC_EVTENSET_COMPARE2_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENSET_COMPARE2_Enabled

#define RTC_EVTENSET_COMPARE2_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENSET_COMPARE2_Msk

#define RTC_EVTENSET_COMPARE2_Msk   (0x1UL << RTC_EVTENSET_COMPARE2_Pos)

Bit mask of COMPARE2 field.

◆ RTC_EVTENSET_COMPARE2_Pos

#define RTC_EVTENSET_COMPARE2_Pos   (18UL)

Position of COMPARE2 field.

◆ RTC_EVTENSET_COMPARE2_Set

#define RTC_EVTENSET_COMPARE2_Set   (1UL)

Enable

◆ RTC_EVTENSET_COMPARE3_Disabled

#define RTC_EVTENSET_COMPARE3_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENSET_COMPARE3_Enabled

#define RTC_EVTENSET_COMPARE3_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENSET_COMPARE3_Msk

#define RTC_EVTENSET_COMPARE3_Msk   (0x1UL << RTC_EVTENSET_COMPARE3_Pos)

Bit mask of COMPARE3 field.

◆ RTC_EVTENSET_COMPARE3_Pos

#define RTC_EVTENSET_COMPARE3_Pos   (19UL)

Position of COMPARE3 field.

◆ RTC_EVTENSET_COMPARE3_Set

#define RTC_EVTENSET_COMPARE3_Set   (1UL)

Enable

◆ RTC_EVTENSET_OVRFLW_Disabled

#define RTC_EVTENSET_OVRFLW_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENSET_OVRFLW_Enabled

#define RTC_EVTENSET_OVRFLW_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENSET_OVRFLW_Msk

#define RTC_EVTENSET_OVRFLW_Msk   (0x1UL << RTC_EVTENSET_OVRFLW_Pos)

Bit mask of OVRFLW field.

◆ RTC_EVTENSET_OVRFLW_Pos

#define RTC_EVTENSET_OVRFLW_Pos   (1UL)

Position of OVRFLW field.

◆ RTC_EVTENSET_OVRFLW_Set

#define RTC_EVTENSET_OVRFLW_Set   (1UL)

Enable

◆ RTC_EVTENSET_TICK_Disabled

#define RTC_EVTENSET_TICK_Disabled   (0UL)

Read: Disabled

◆ RTC_EVTENSET_TICK_Enabled

#define RTC_EVTENSET_TICK_Enabled   (1UL)

Read: Enabled

◆ RTC_EVTENSET_TICK_Msk

#define RTC_EVTENSET_TICK_Msk   (0x1UL << RTC_EVTENSET_TICK_Pos)

Bit mask of TICK field.

◆ RTC_EVTENSET_TICK_Pos

#define RTC_EVTENSET_TICK_Pos   (0UL)

Position of TICK field.

◆ RTC_EVTENSET_TICK_Set

#define RTC_EVTENSET_TICK_Set   (1UL)

Enable

◆ RTC_INTENCLR_COMPARE0_Clear

#define RTC_INTENCLR_COMPARE0_Clear   (1UL)

Disable

◆ RTC_INTENCLR_COMPARE0_Disabled

#define RTC_INTENCLR_COMPARE0_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENCLR_COMPARE0_Enabled

#define RTC_INTENCLR_COMPARE0_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENCLR_COMPARE0_Msk

#define RTC_INTENCLR_COMPARE0_Msk   (0x1UL << RTC_INTENCLR_COMPARE0_Pos)

Bit mask of COMPARE0 field.

◆ RTC_INTENCLR_COMPARE0_Pos

#define RTC_INTENCLR_COMPARE0_Pos   (16UL)

Position of COMPARE0 field.

◆ RTC_INTENCLR_COMPARE1_Clear

#define RTC_INTENCLR_COMPARE1_Clear   (1UL)

Disable

◆ RTC_INTENCLR_COMPARE1_Disabled

#define RTC_INTENCLR_COMPARE1_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENCLR_COMPARE1_Enabled

#define RTC_INTENCLR_COMPARE1_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENCLR_COMPARE1_Msk

#define RTC_INTENCLR_COMPARE1_Msk   (0x1UL << RTC_INTENCLR_COMPARE1_Pos)

Bit mask of COMPARE1 field.

◆ RTC_INTENCLR_COMPARE1_Pos

#define RTC_INTENCLR_COMPARE1_Pos   (17UL)

Position of COMPARE1 field.

◆ RTC_INTENCLR_COMPARE2_Clear

#define RTC_INTENCLR_COMPARE2_Clear   (1UL)

Disable

◆ RTC_INTENCLR_COMPARE2_Disabled

#define RTC_INTENCLR_COMPARE2_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENCLR_COMPARE2_Enabled

#define RTC_INTENCLR_COMPARE2_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENCLR_COMPARE2_Msk

#define RTC_INTENCLR_COMPARE2_Msk   (0x1UL << RTC_INTENCLR_COMPARE2_Pos)

Bit mask of COMPARE2 field.

◆ RTC_INTENCLR_COMPARE2_Pos

#define RTC_INTENCLR_COMPARE2_Pos   (18UL)

Position of COMPARE2 field.

◆ RTC_INTENCLR_COMPARE3_Clear

#define RTC_INTENCLR_COMPARE3_Clear   (1UL)

Disable

◆ RTC_INTENCLR_COMPARE3_Disabled

#define RTC_INTENCLR_COMPARE3_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENCLR_COMPARE3_Enabled

#define RTC_INTENCLR_COMPARE3_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENCLR_COMPARE3_Msk

#define RTC_INTENCLR_COMPARE3_Msk   (0x1UL << RTC_INTENCLR_COMPARE3_Pos)

Bit mask of COMPARE3 field.

◆ RTC_INTENCLR_COMPARE3_Pos

#define RTC_INTENCLR_COMPARE3_Pos   (19UL)

Position of COMPARE3 field.

◆ RTC_INTENCLR_OVRFLW_Clear

#define RTC_INTENCLR_OVRFLW_Clear   (1UL)

Disable

◆ RTC_INTENCLR_OVRFLW_Disabled

#define RTC_INTENCLR_OVRFLW_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENCLR_OVRFLW_Enabled

#define RTC_INTENCLR_OVRFLW_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENCLR_OVRFLW_Msk

#define RTC_INTENCLR_OVRFLW_Msk   (0x1UL << RTC_INTENCLR_OVRFLW_Pos)

Bit mask of OVRFLW field.

◆ RTC_INTENCLR_OVRFLW_Pos

#define RTC_INTENCLR_OVRFLW_Pos   (1UL)

Position of OVRFLW field.

◆ RTC_INTENCLR_TICK_Clear

#define RTC_INTENCLR_TICK_Clear   (1UL)

Disable

◆ RTC_INTENCLR_TICK_Disabled

#define RTC_INTENCLR_TICK_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENCLR_TICK_Enabled

#define RTC_INTENCLR_TICK_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENCLR_TICK_Msk

#define RTC_INTENCLR_TICK_Msk   (0x1UL << RTC_INTENCLR_TICK_Pos)

Bit mask of TICK field.

◆ RTC_INTENCLR_TICK_Pos

#define RTC_INTENCLR_TICK_Pos   (0UL)

Position of TICK field.

◆ RTC_INTENSET_COMPARE0_Disabled

#define RTC_INTENSET_COMPARE0_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENSET_COMPARE0_Enabled

#define RTC_INTENSET_COMPARE0_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENSET_COMPARE0_Msk

#define RTC_INTENSET_COMPARE0_Msk   (0x1UL << RTC_INTENSET_COMPARE0_Pos)

Bit mask of COMPARE0 field.

◆ RTC_INTENSET_COMPARE0_Pos

#define RTC_INTENSET_COMPARE0_Pos   (16UL)

Position of COMPARE0 field.

◆ RTC_INTENSET_COMPARE0_Set

#define RTC_INTENSET_COMPARE0_Set   (1UL)

Enable

◆ RTC_INTENSET_COMPARE1_Disabled

#define RTC_INTENSET_COMPARE1_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENSET_COMPARE1_Enabled

#define RTC_INTENSET_COMPARE1_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENSET_COMPARE1_Msk

#define RTC_INTENSET_COMPARE1_Msk   (0x1UL << RTC_INTENSET_COMPARE1_Pos)

Bit mask of COMPARE1 field.

◆ RTC_INTENSET_COMPARE1_Pos

#define RTC_INTENSET_COMPARE1_Pos   (17UL)

Position of COMPARE1 field.

◆ RTC_INTENSET_COMPARE1_Set

#define RTC_INTENSET_COMPARE1_Set   (1UL)

Enable

◆ RTC_INTENSET_COMPARE2_Disabled

#define RTC_INTENSET_COMPARE2_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENSET_COMPARE2_Enabled

#define RTC_INTENSET_COMPARE2_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENSET_COMPARE2_Msk

#define RTC_INTENSET_COMPARE2_Msk   (0x1UL << RTC_INTENSET_COMPARE2_Pos)

Bit mask of COMPARE2 field.

◆ RTC_INTENSET_COMPARE2_Pos

#define RTC_INTENSET_COMPARE2_Pos   (18UL)

Position of COMPARE2 field.

◆ RTC_INTENSET_COMPARE2_Set

#define RTC_INTENSET_COMPARE2_Set   (1UL)

Enable

◆ RTC_INTENSET_COMPARE3_Disabled

#define RTC_INTENSET_COMPARE3_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENSET_COMPARE3_Enabled

#define RTC_INTENSET_COMPARE3_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENSET_COMPARE3_Msk

#define RTC_INTENSET_COMPARE3_Msk   (0x1UL << RTC_INTENSET_COMPARE3_Pos)

Bit mask of COMPARE3 field.

◆ RTC_INTENSET_COMPARE3_Pos

#define RTC_INTENSET_COMPARE3_Pos   (19UL)

Position of COMPARE3 field.

◆ RTC_INTENSET_COMPARE3_Set

#define RTC_INTENSET_COMPARE3_Set   (1UL)

Enable

◆ RTC_INTENSET_OVRFLW_Disabled

#define RTC_INTENSET_OVRFLW_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENSET_OVRFLW_Enabled

#define RTC_INTENSET_OVRFLW_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENSET_OVRFLW_Msk

#define RTC_INTENSET_OVRFLW_Msk   (0x1UL << RTC_INTENSET_OVRFLW_Pos)

Bit mask of OVRFLW field.

◆ RTC_INTENSET_OVRFLW_Pos

#define RTC_INTENSET_OVRFLW_Pos   (1UL)

Position of OVRFLW field.

◆ RTC_INTENSET_OVRFLW_Set

#define RTC_INTENSET_OVRFLW_Set   (1UL)

Enable

◆ RTC_INTENSET_TICK_Disabled

#define RTC_INTENSET_TICK_Disabled   (0UL)

Read: Disabled

◆ RTC_INTENSET_TICK_Enabled

#define RTC_INTENSET_TICK_Enabled   (1UL)

Read: Enabled

◆ RTC_INTENSET_TICK_Msk

#define RTC_INTENSET_TICK_Msk   (0x1UL << RTC_INTENSET_TICK_Pos)

Bit mask of TICK field.

◆ RTC_INTENSET_TICK_Pos

#define RTC_INTENSET_TICK_Pos   (0UL)

Position of TICK field.

◆ RTC_INTENSET_TICK_Set

#define RTC_INTENSET_TICK_Set   (1UL)

Enable

◆ RTC_PRESCALER_PRESCALER_Msk

#define RTC_PRESCALER_PRESCALER_Msk   (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos)

Bit mask of PRESCALER field.

◆ RTC_PRESCALER_PRESCALER_Pos

#define RTC_PRESCALER_PRESCALER_Pos   (0UL)

Position of PRESCALER field.

◆ SAADC_CH_CONFIG_BURST_Disabled

#define SAADC_CH_CONFIG_BURST_Disabled   (0UL)

Burst mode is disabled (normal operation)

◆ SAADC_CH_CONFIG_BURST_Enabled

#define SAADC_CH_CONFIG_BURST_Enabled   (1UL)

Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.

◆ SAADC_CH_CONFIG_BURST_Msk

#define SAADC_CH_CONFIG_BURST_Msk   (0x1UL << SAADC_CH_CONFIG_BURST_Pos)

Bit mask of BURST field.

◆ SAADC_CH_CONFIG_BURST_Pos

#define SAADC_CH_CONFIG_BURST_Pos   (24UL)

Position of BURST field.

◆ SAADC_CH_CONFIG_GAIN_Gain1

#define SAADC_CH_CONFIG_GAIN_Gain1   (5UL)

1

◆ SAADC_CH_CONFIG_GAIN_Gain1_2

#define SAADC_CH_CONFIG_GAIN_Gain1_2   (4UL)

1/2

◆ SAADC_CH_CONFIG_GAIN_Gain1_3

#define SAADC_CH_CONFIG_GAIN_Gain1_3   (3UL)

1/3

◆ SAADC_CH_CONFIG_GAIN_Gain1_4

#define SAADC_CH_CONFIG_GAIN_Gain1_4   (2UL)

1/4

◆ SAADC_CH_CONFIG_GAIN_Gain1_5

#define SAADC_CH_CONFIG_GAIN_Gain1_5   (1UL)

1/5

◆ SAADC_CH_CONFIG_GAIN_Gain1_6

#define SAADC_CH_CONFIG_GAIN_Gain1_6   (0UL)

1/6

◆ SAADC_CH_CONFIG_GAIN_Gain2

#define SAADC_CH_CONFIG_GAIN_Gain2   (6UL)

2

◆ SAADC_CH_CONFIG_GAIN_Gain4

#define SAADC_CH_CONFIG_GAIN_Gain4   (7UL)

4

◆ SAADC_CH_CONFIG_GAIN_Msk

#define SAADC_CH_CONFIG_GAIN_Msk   (0x7UL << SAADC_CH_CONFIG_GAIN_Pos)

Bit mask of GAIN field.

◆ SAADC_CH_CONFIG_GAIN_Pos

#define SAADC_CH_CONFIG_GAIN_Pos   (8UL)

Position of GAIN field.

◆ SAADC_CH_CONFIG_MODE_Diff

#define SAADC_CH_CONFIG_MODE_Diff   (1UL)

Differential

◆ SAADC_CH_CONFIG_MODE_Msk

#define SAADC_CH_CONFIG_MODE_Msk   (0x1UL << SAADC_CH_CONFIG_MODE_Pos)

Bit mask of MODE field.

◆ SAADC_CH_CONFIG_MODE_Pos

#define SAADC_CH_CONFIG_MODE_Pos   (20UL)

Position of MODE field.

◆ SAADC_CH_CONFIG_MODE_SE

#define SAADC_CH_CONFIG_MODE_SE   (0UL)

Single ended, PSELN will be ignored, negative input to ADC shorted to GND

◆ SAADC_CH_CONFIG_REFSEL_Internal

#define SAADC_CH_CONFIG_REFSEL_Internal   (0UL)

Internal reference (0.6 V)

◆ SAADC_CH_CONFIG_REFSEL_Msk

#define SAADC_CH_CONFIG_REFSEL_Msk   (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos)

Bit mask of REFSEL field.

◆ SAADC_CH_CONFIG_REFSEL_Pos

#define SAADC_CH_CONFIG_REFSEL_Pos   (12UL)

Position of REFSEL field.

◆ SAADC_CH_CONFIG_REFSEL_VDD1_4

#define SAADC_CH_CONFIG_REFSEL_VDD1_4   (1UL)

VDD/4 as reference

◆ SAADC_CH_CONFIG_RESN_Bypass

#define SAADC_CH_CONFIG_RESN_Bypass   (0UL)

Bypass resistor ladder

◆ SAADC_CH_CONFIG_RESN_Msk

#define SAADC_CH_CONFIG_RESN_Msk   (0x3UL << SAADC_CH_CONFIG_RESN_Pos)

Bit mask of RESN field.

◆ SAADC_CH_CONFIG_RESN_Pos

#define SAADC_CH_CONFIG_RESN_Pos   (4UL)

Position of RESN field.

◆ SAADC_CH_CONFIG_RESN_Pulldown

#define SAADC_CH_CONFIG_RESN_Pulldown   (1UL)

Pull-down to GND

◆ SAADC_CH_CONFIG_RESN_Pullup

#define SAADC_CH_CONFIG_RESN_Pullup   (2UL)

Pull-up to VDD

◆ SAADC_CH_CONFIG_RESN_VDD1_2

#define SAADC_CH_CONFIG_RESN_VDD1_2   (3UL)

Set input at VDD/2

◆ SAADC_CH_CONFIG_RESP_Bypass

#define SAADC_CH_CONFIG_RESP_Bypass   (0UL)

Bypass resistor ladder

◆ SAADC_CH_CONFIG_RESP_Msk

#define SAADC_CH_CONFIG_RESP_Msk   (0x3UL << SAADC_CH_CONFIG_RESP_Pos)

Bit mask of RESP field.

◆ SAADC_CH_CONFIG_RESP_Pos

#define SAADC_CH_CONFIG_RESP_Pos   (0UL)

Position of RESP field.

◆ SAADC_CH_CONFIG_RESP_Pulldown

#define SAADC_CH_CONFIG_RESP_Pulldown   (1UL)

Pull-down to GND

◆ SAADC_CH_CONFIG_RESP_Pullup

#define SAADC_CH_CONFIG_RESP_Pullup   (2UL)

Pull-up to VDD

◆ SAADC_CH_CONFIG_RESP_VDD1_2

#define SAADC_CH_CONFIG_RESP_VDD1_2   (3UL)

Set input at VDD/2

◆ SAADC_CH_CONFIG_TACQ_10us

#define SAADC_CH_CONFIG_TACQ_10us   (2UL)

10 us

◆ SAADC_CH_CONFIG_TACQ_15us

#define SAADC_CH_CONFIG_TACQ_15us   (3UL)

15 us

◆ SAADC_CH_CONFIG_TACQ_20us

#define SAADC_CH_CONFIG_TACQ_20us   (4UL)

20 us

◆ SAADC_CH_CONFIG_TACQ_3us

#define SAADC_CH_CONFIG_TACQ_3us   (0UL)

3 us

◆ SAADC_CH_CONFIG_TACQ_40us

#define SAADC_CH_CONFIG_TACQ_40us   (5UL)

40 us

◆ SAADC_CH_CONFIG_TACQ_5us

#define SAADC_CH_CONFIG_TACQ_5us   (1UL)

5 us

◆ SAADC_CH_CONFIG_TACQ_Msk

#define SAADC_CH_CONFIG_TACQ_Msk   (0x7UL << SAADC_CH_CONFIG_TACQ_Pos)

Bit mask of TACQ field.

◆ SAADC_CH_CONFIG_TACQ_Pos

#define SAADC_CH_CONFIG_TACQ_Pos   (16UL)

Position of TACQ field.

◆ SAADC_CH_LIMIT_HIGH_Msk

#define SAADC_CH_LIMIT_HIGH_Msk   (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos)

Bit mask of HIGH field.

◆ SAADC_CH_LIMIT_HIGH_Pos

#define SAADC_CH_LIMIT_HIGH_Pos   (16UL)

Position of HIGH field.

◆ SAADC_CH_LIMIT_LOW_Msk

#define SAADC_CH_LIMIT_LOW_Msk   (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos)

Bit mask of LOW field.

◆ SAADC_CH_LIMIT_LOW_Pos

#define SAADC_CH_LIMIT_LOW_Pos   (0UL)

Position of LOW field.

◆ SAADC_CH_PSELN_PSELN_AnalogInput0

#define SAADC_CH_PSELN_PSELN_AnalogInput0   (1UL)

AIN0

◆ SAADC_CH_PSELN_PSELN_AnalogInput1

#define SAADC_CH_PSELN_PSELN_AnalogInput1   (2UL)

AIN1

◆ SAADC_CH_PSELN_PSELN_AnalogInput2

#define SAADC_CH_PSELN_PSELN_AnalogInput2   (3UL)

AIN2

◆ SAADC_CH_PSELN_PSELN_AnalogInput3

#define SAADC_CH_PSELN_PSELN_AnalogInput3   (4UL)

AIN3

◆ SAADC_CH_PSELN_PSELN_AnalogInput4

#define SAADC_CH_PSELN_PSELN_AnalogInput4   (5UL)

AIN4

◆ SAADC_CH_PSELN_PSELN_AnalogInput5

#define SAADC_CH_PSELN_PSELN_AnalogInput5   (6UL)

AIN5

◆ SAADC_CH_PSELN_PSELN_AnalogInput6

#define SAADC_CH_PSELN_PSELN_AnalogInput6   (7UL)

AIN6

◆ SAADC_CH_PSELN_PSELN_AnalogInput7

#define SAADC_CH_PSELN_PSELN_AnalogInput7   (8UL)

AIN7

◆ SAADC_CH_PSELN_PSELN_Msk

#define SAADC_CH_PSELN_PSELN_Msk   (0x1FUL << SAADC_CH_PSELN_PSELN_Pos)

Bit mask of PSELN field.

◆ SAADC_CH_PSELN_PSELN_NC

#define SAADC_CH_PSELN_PSELN_NC   (0UL)

Not connected

◆ SAADC_CH_PSELN_PSELN_Pos

#define SAADC_CH_PSELN_PSELN_Pos   (0UL)

Position of PSELN field.

◆ SAADC_CH_PSELN_PSELN_VDD

#define SAADC_CH_PSELN_PSELN_VDD   (9UL)

VDD

◆ SAADC_CH_PSELP_PSELP_AnalogInput0

#define SAADC_CH_PSELP_PSELP_AnalogInput0   (1UL)

AIN0

◆ SAADC_CH_PSELP_PSELP_AnalogInput1

#define SAADC_CH_PSELP_PSELP_AnalogInput1   (2UL)

AIN1

◆ SAADC_CH_PSELP_PSELP_AnalogInput2

#define SAADC_CH_PSELP_PSELP_AnalogInput2   (3UL)

AIN2

◆ SAADC_CH_PSELP_PSELP_AnalogInput3

#define SAADC_CH_PSELP_PSELP_AnalogInput3   (4UL)

AIN3

◆ SAADC_CH_PSELP_PSELP_AnalogInput4

#define SAADC_CH_PSELP_PSELP_AnalogInput4   (5UL)

AIN4

◆ SAADC_CH_PSELP_PSELP_AnalogInput5

#define SAADC_CH_PSELP_PSELP_AnalogInput5   (6UL)

AIN5

◆ SAADC_CH_PSELP_PSELP_AnalogInput6

#define SAADC_CH_PSELP_PSELP_AnalogInput6   (7UL)

AIN6

◆ SAADC_CH_PSELP_PSELP_AnalogInput7

#define SAADC_CH_PSELP_PSELP_AnalogInput7   (8UL)

AIN7

◆ SAADC_CH_PSELP_PSELP_Msk

#define SAADC_CH_PSELP_PSELP_Msk   (0x1FUL << SAADC_CH_PSELP_PSELP_Pos)

Bit mask of PSELP field.

◆ SAADC_CH_PSELP_PSELP_NC

#define SAADC_CH_PSELP_PSELP_NC   (0UL)

Not connected

◆ SAADC_CH_PSELP_PSELP_Pos

#define SAADC_CH_PSELP_PSELP_Pos   (0UL)

Position of PSELP field.

◆ SAADC_CH_PSELP_PSELP_VDD

#define SAADC_CH_PSELP_PSELP_VDD   (9UL)

VDD

◆ SAADC_ENABLE_ENABLE_Disabled

#define SAADC_ENABLE_ENABLE_Disabled   (0UL)

Disable ADC

◆ SAADC_ENABLE_ENABLE_Enabled

#define SAADC_ENABLE_ENABLE_Enabled   (1UL)

Enable ADC

◆ SAADC_ENABLE_ENABLE_Msk

#define SAADC_ENABLE_ENABLE_Msk   (0x1UL << SAADC_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ SAADC_ENABLE_ENABLE_Pos

#define SAADC_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ SAADC_INTEN_CALIBRATEDONE_Disabled

#define SAADC_INTEN_CALIBRATEDONE_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CALIBRATEDONE_Enabled

#define SAADC_INTEN_CALIBRATEDONE_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CALIBRATEDONE_Msk

#define SAADC_INTEN_CALIBRATEDONE_Msk   (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos)

Bit mask of CALIBRATEDONE field.

◆ SAADC_INTEN_CALIBRATEDONE_Pos

#define SAADC_INTEN_CALIBRATEDONE_Pos   (4UL)

Position of CALIBRATEDONE field.

◆ SAADC_INTEN_CH0LIMITH_Disabled

#define SAADC_INTEN_CH0LIMITH_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH0LIMITH_Enabled

#define SAADC_INTEN_CH0LIMITH_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH0LIMITH_Msk

#define SAADC_INTEN_CH0LIMITH_Msk   (0x1UL << SAADC_INTEN_CH0LIMITH_Pos)

Bit mask of CH0LIMITH field.

◆ SAADC_INTEN_CH0LIMITH_Pos

#define SAADC_INTEN_CH0LIMITH_Pos   (6UL)

Position of CH0LIMITH field.

◆ SAADC_INTEN_CH0LIMITL_Disabled

#define SAADC_INTEN_CH0LIMITL_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH0LIMITL_Enabled

#define SAADC_INTEN_CH0LIMITL_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH0LIMITL_Msk

#define SAADC_INTEN_CH0LIMITL_Msk   (0x1UL << SAADC_INTEN_CH0LIMITL_Pos)

Bit mask of CH0LIMITL field.

◆ SAADC_INTEN_CH0LIMITL_Pos

#define SAADC_INTEN_CH0LIMITL_Pos   (7UL)

Position of CH0LIMITL field.

◆ SAADC_INTEN_CH1LIMITH_Disabled

#define SAADC_INTEN_CH1LIMITH_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH1LIMITH_Enabled

#define SAADC_INTEN_CH1LIMITH_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH1LIMITH_Msk

#define SAADC_INTEN_CH1LIMITH_Msk   (0x1UL << SAADC_INTEN_CH1LIMITH_Pos)

Bit mask of CH1LIMITH field.

◆ SAADC_INTEN_CH1LIMITH_Pos

#define SAADC_INTEN_CH1LIMITH_Pos   (8UL)

Position of CH1LIMITH field.

◆ SAADC_INTEN_CH1LIMITL_Disabled

#define SAADC_INTEN_CH1LIMITL_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH1LIMITL_Enabled

#define SAADC_INTEN_CH1LIMITL_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH1LIMITL_Msk

#define SAADC_INTEN_CH1LIMITL_Msk   (0x1UL << SAADC_INTEN_CH1LIMITL_Pos)

Bit mask of CH1LIMITL field.

◆ SAADC_INTEN_CH1LIMITL_Pos

#define SAADC_INTEN_CH1LIMITL_Pos   (9UL)

Position of CH1LIMITL field.

◆ SAADC_INTEN_CH2LIMITH_Disabled

#define SAADC_INTEN_CH2LIMITH_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH2LIMITH_Enabled

#define SAADC_INTEN_CH2LIMITH_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH2LIMITH_Msk

#define SAADC_INTEN_CH2LIMITH_Msk   (0x1UL << SAADC_INTEN_CH2LIMITH_Pos)

Bit mask of CH2LIMITH field.

◆ SAADC_INTEN_CH2LIMITH_Pos

#define SAADC_INTEN_CH2LIMITH_Pos   (10UL)

Position of CH2LIMITH field.

◆ SAADC_INTEN_CH2LIMITL_Disabled

#define SAADC_INTEN_CH2LIMITL_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH2LIMITL_Enabled

#define SAADC_INTEN_CH2LIMITL_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH2LIMITL_Msk

#define SAADC_INTEN_CH2LIMITL_Msk   (0x1UL << SAADC_INTEN_CH2LIMITL_Pos)

Bit mask of CH2LIMITL field.

◆ SAADC_INTEN_CH2LIMITL_Pos

#define SAADC_INTEN_CH2LIMITL_Pos   (11UL)

Position of CH2LIMITL field.

◆ SAADC_INTEN_CH3LIMITH_Disabled

#define SAADC_INTEN_CH3LIMITH_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH3LIMITH_Enabled

#define SAADC_INTEN_CH3LIMITH_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH3LIMITH_Msk

#define SAADC_INTEN_CH3LIMITH_Msk   (0x1UL << SAADC_INTEN_CH3LIMITH_Pos)

Bit mask of CH3LIMITH field.

◆ SAADC_INTEN_CH3LIMITH_Pos

#define SAADC_INTEN_CH3LIMITH_Pos   (12UL)

Position of CH3LIMITH field.

◆ SAADC_INTEN_CH3LIMITL_Disabled

#define SAADC_INTEN_CH3LIMITL_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH3LIMITL_Enabled

#define SAADC_INTEN_CH3LIMITL_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH3LIMITL_Msk

#define SAADC_INTEN_CH3LIMITL_Msk   (0x1UL << SAADC_INTEN_CH3LIMITL_Pos)

Bit mask of CH3LIMITL field.

◆ SAADC_INTEN_CH3LIMITL_Pos

#define SAADC_INTEN_CH3LIMITL_Pos   (13UL)

Position of CH3LIMITL field.

◆ SAADC_INTEN_CH4LIMITH_Disabled

#define SAADC_INTEN_CH4LIMITH_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH4LIMITH_Enabled

#define SAADC_INTEN_CH4LIMITH_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH4LIMITH_Msk

#define SAADC_INTEN_CH4LIMITH_Msk   (0x1UL << SAADC_INTEN_CH4LIMITH_Pos)

Bit mask of CH4LIMITH field.

◆ SAADC_INTEN_CH4LIMITH_Pos

#define SAADC_INTEN_CH4LIMITH_Pos   (14UL)

Position of CH4LIMITH field.

◆ SAADC_INTEN_CH4LIMITL_Disabled

#define SAADC_INTEN_CH4LIMITL_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH4LIMITL_Enabled

#define SAADC_INTEN_CH4LIMITL_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH4LIMITL_Msk

#define SAADC_INTEN_CH4LIMITL_Msk   (0x1UL << SAADC_INTEN_CH4LIMITL_Pos)

Bit mask of CH4LIMITL field.

◆ SAADC_INTEN_CH4LIMITL_Pos

#define SAADC_INTEN_CH4LIMITL_Pos   (15UL)

Position of CH4LIMITL field.

◆ SAADC_INTEN_CH5LIMITH_Disabled

#define SAADC_INTEN_CH5LIMITH_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH5LIMITH_Enabled

#define SAADC_INTEN_CH5LIMITH_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH5LIMITH_Msk

#define SAADC_INTEN_CH5LIMITH_Msk   (0x1UL << SAADC_INTEN_CH5LIMITH_Pos)

Bit mask of CH5LIMITH field.

◆ SAADC_INTEN_CH5LIMITH_Pos

#define SAADC_INTEN_CH5LIMITH_Pos   (16UL)

Position of CH5LIMITH field.

◆ SAADC_INTEN_CH5LIMITL_Disabled

#define SAADC_INTEN_CH5LIMITL_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH5LIMITL_Enabled

#define SAADC_INTEN_CH5LIMITL_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH5LIMITL_Msk

#define SAADC_INTEN_CH5LIMITL_Msk   (0x1UL << SAADC_INTEN_CH5LIMITL_Pos)

Bit mask of CH5LIMITL field.

◆ SAADC_INTEN_CH5LIMITL_Pos

#define SAADC_INTEN_CH5LIMITL_Pos   (17UL)

Position of CH5LIMITL field.

◆ SAADC_INTEN_CH6LIMITH_Disabled

#define SAADC_INTEN_CH6LIMITH_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH6LIMITH_Enabled

#define SAADC_INTEN_CH6LIMITH_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH6LIMITH_Msk

#define SAADC_INTEN_CH6LIMITH_Msk   (0x1UL << SAADC_INTEN_CH6LIMITH_Pos)

Bit mask of CH6LIMITH field.

◆ SAADC_INTEN_CH6LIMITH_Pos

#define SAADC_INTEN_CH6LIMITH_Pos   (18UL)

Position of CH6LIMITH field.

◆ SAADC_INTEN_CH6LIMITL_Disabled

#define SAADC_INTEN_CH6LIMITL_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH6LIMITL_Enabled

#define SAADC_INTEN_CH6LIMITL_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH6LIMITL_Msk

#define SAADC_INTEN_CH6LIMITL_Msk   (0x1UL << SAADC_INTEN_CH6LIMITL_Pos)

Bit mask of CH6LIMITL field.

◆ SAADC_INTEN_CH6LIMITL_Pos

#define SAADC_INTEN_CH6LIMITL_Pos   (19UL)

Position of CH6LIMITL field.

◆ SAADC_INTEN_CH7LIMITH_Disabled

#define SAADC_INTEN_CH7LIMITH_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH7LIMITH_Enabled

#define SAADC_INTEN_CH7LIMITH_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH7LIMITH_Msk

#define SAADC_INTEN_CH7LIMITH_Msk   (0x1UL << SAADC_INTEN_CH7LIMITH_Pos)

Bit mask of CH7LIMITH field.

◆ SAADC_INTEN_CH7LIMITH_Pos

#define SAADC_INTEN_CH7LIMITH_Pos   (20UL)

Position of CH7LIMITH field.

◆ SAADC_INTEN_CH7LIMITL_Disabled

#define SAADC_INTEN_CH7LIMITL_Disabled   (0UL)

Disable

◆ SAADC_INTEN_CH7LIMITL_Enabled

#define SAADC_INTEN_CH7LIMITL_Enabled   (1UL)

Enable

◆ SAADC_INTEN_CH7LIMITL_Msk

#define SAADC_INTEN_CH7LIMITL_Msk   (0x1UL << SAADC_INTEN_CH7LIMITL_Pos)

Bit mask of CH7LIMITL field.

◆ SAADC_INTEN_CH7LIMITL_Pos

#define SAADC_INTEN_CH7LIMITL_Pos   (21UL)

Position of CH7LIMITL field.

◆ SAADC_INTEN_DONE_Disabled

#define SAADC_INTEN_DONE_Disabled   (0UL)

Disable

◆ SAADC_INTEN_DONE_Enabled

#define SAADC_INTEN_DONE_Enabled   (1UL)

Enable

◆ SAADC_INTEN_DONE_Msk

#define SAADC_INTEN_DONE_Msk   (0x1UL << SAADC_INTEN_DONE_Pos)

Bit mask of DONE field.

◆ SAADC_INTEN_DONE_Pos

#define SAADC_INTEN_DONE_Pos   (2UL)

Position of DONE field.

◆ SAADC_INTEN_END_Disabled

#define SAADC_INTEN_END_Disabled   (0UL)

Disable

◆ SAADC_INTEN_END_Enabled

#define SAADC_INTEN_END_Enabled   (1UL)

Enable

◆ SAADC_INTEN_END_Msk

#define SAADC_INTEN_END_Msk   (0x1UL << SAADC_INTEN_END_Pos)

Bit mask of END field.

◆ SAADC_INTEN_END_Pos

#define SAADC_INTEN_END_Pos   (1UL)

Position of END field.

◆ SAADC_INTEN_RESULTDONE_Disabled

#define SAADC_INTEN_RESULTDONE_Disabled   (0UL)

Disable

◆ SAADC_INTEN_RESULTDONE_Enabled

#define SAADC_INTEN_RESULTDONE_Enabled   (1UL)

Enable

◆ SAADC_INTEN_RESULTDONE_Msk

#define SAADC_INTEN_RESULTDONE_Msk   (0x1UL << SAADC_INTEN_RESULTDONE_Pos)

Bit mask of RESULTDONE field.

◆ SAADC_INTEN_RESULTDONE_Pos

#define SAADC_INTEN_RESULTDONE_Pos   (3UL)

Position of RESULTDONE field.

◆ SAADC_INTEN_STARTED_Disabled

#define SAADC_INTEN_STARTED_Disabled   (0UL)

Disable

◆ SAADC_INTEN_STARTED_Enabled

#define SAADC_INTEN_STARTED_Enabled   (1UL)

Enable

◆ SAADC_INTEN_STARTED_Msk

#define SAADC_INTEN_STARTED_Msk   (0x1UL << SAADC_INTEN_STARTED_Pos)

Bit mask of STARTED field.

◆ SAADC_INTEN_STARTED_Pos

#define SAADC_INTEN_STARTED_Pos   (0UL)

Position of STARTED field.

◆ SAADC_INTEN_STOPPED_Disabled

#define SAADC_INTEN_STOPPED_Disabled   (0UL)

Disable

◆ SAADC_INTEN_STOPPED_Enabled

#define SAADC_INTEN_STOPPED_Enabled   (1UL)

Enable

◆ SAADC_INTEN_STOPPED_Msk

#define SAADC_INTEN_STOPPED_Msk   (0x1UL << SAADC_INTEN_STOPPED_Pos)

Bit mask of STOPPED field.

◆ SAADC_INTEN_STOPPED_Pos

#define SAADC_INTEN_STOPPED_Pos   (5UL)

Position of STOPPED field.

◆ SAADC_INTENCLR_CALIBRATEDONE_Clear

#define SAADC_INTENCLR_CALIBRATEDONE_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CALIBRATEDONE_Disabled

#define SAADC_INTENCLR_CALIBRATEDONE_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CALIBRATEDONE_Enabled

#define SAADC_INTENCLR_CALIBRATEDONE_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CALIBRATEDONE_Msk

#define SAADC_INTENCLR_CALIBRATEDONE_Msk   (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos)

Bit mask of CALIBRATEDONE field.

◆ SAADC_INTENCLR_CALIBRATEDONE_Pos

#define SAADC_INTENCLR_CALIBRATEDONE_Pos   (4UL)

Position of CALIBRATEDONE field.

◆ SAADC_INTENCLR_CH0LIMITH_Clear

#define SAADC_INTENCLR_CH0LIMITH_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH0LIMITH_Disabled

#define SAADC_INTENCLR_CH0LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH0LIMITH_Enabled

#define SAADC_INTENCLR_CH0LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH0LIMITH_Msk

#define SAADC_INTENCLR_CH0LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos)

Bit mask of CH0LIMITH field.

◆ SAADC_INTENCLR_CH0LIMITH_Pos

#define SAADC_INTENCLR_CH0LIMITH_Pos   (6UL)

Position of CH0LIMITH field.

◆ SAADC_INTENCLR_CH0LIMITL_Clear

#define SAADC_INTENCLR_CH0LIMITL_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH0LIMITL_Disabled

#define SAADC_INTENCLR_CH0LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH0LIMITL_Enabled

#define SAADC_INTENCLR_CH0LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH0LIMITL_Msk

#define SAADC_INTENCLR_CH0LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos)

Bit mask of CH0LIMITL field.

◆ SAADC_INTENCLR_CH0LIMITL_Pos

#define SAADC_INTENCLR_CH0LIMITL_Pos   (7UL)

Position of CH0LIMITL field.

◆ SAADC_INTENCLR_CH1LIMITH_Clear

#define SAADC_INTENCLR_CH1LIMITH_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH1LIMITH_Disabled

#define SAADC_INTENCLR_CH1LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH1LIMITH_Enabled

#define SAADC_INTENCLR_CH1LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH1LIMITH_Msk

#define SAADC_INTENCLR_CH1LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos)

Bit mask of CH1LIMITH field.

◆ SAADC_INTENCLR_CH1LIMITH_Pos

#define SAADC_INTENCLR_CH1LIMITH_Pos   (8UL)

Position of CH1LIMITH field.

◆ SAADC_INTENCLR_CH1LIMITL_Clear

#define SAADC_INTENCLR_CH1LIMITL_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH1LIMITL_Disabled

#define SAADC_INTENCLR_CH1LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH1LIMITL_Enabled

#define SAADC_INTENCLR_CH1LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH1LIMITL_Msk

#define SAADC_INTENCLR_CH1LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos)

Bit mask of CH1LIMITL field.

◆ SAADC_INTENCLR_CH1LIMITL_Pos

#define SAADC_INTENCLR_CH1LIMITL_Pos   (9UL)

Position of CH1LIMITL field.

◆ SAADC_INTENCLR_CH2LIMITH_Clear

#define SAADC_INTENCLR_CH2LIMITH_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH2LIMITH_Disabled

#define SAADC_INTENCLR_CH2LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH2LIMITH_Enabled

#define SAADC_INTENCLR_CH2LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH2LIMITH_Msk

#define SAADC_INTENCLR_CH2LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos)

Bit mask of CH2LIMITH field.

◆ SAADC_INTENCLR_CH2LIMITH_Pos

#define SAADC_INTENCLR_CH2LIMITH_Pos   (10UL)

Position of CH2LIMITH field.

◆ SAADC_INTENCLR_CH2LIMITL_Clear

#define SAADC_INTENCLR_CH2LIMITL_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH2LIMITL_Disabled

#define SAADC_INTENCLR_CH2LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH2LIMITL_Enabled

#define SAADC_INTENCLR_CH2LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH2LIMITL_Msk

#define SAADC_INTENCLR_CH2LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos)

Bit mask of CH2LIMITL field.

◆ SAADC_INTENCLR_CH2LIMITL_Pos

#define SAADC_INTENCLR_CH2LIMITL_Pos   (11UL)

Position of CH2LIMITL field.

◆ SAADC_INTENCLR_CH3LIMITH_Clear

#define SAADC_INTENCLR_CH3LIMITH_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH3LIMITH_Disabled

#define SAADC_INTENCLR_CH3LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH3LIMITH_Enabled

#define SAADC_INTENCLR_CH3LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH3LIMITH_Msk

#define SAADC_INTENCLR_CH3LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos)

Bit mask of CH3LIMITH field.

◆ SAADC_INTENCLR_CH3LIMITH_Pos

#define SAADC_INTENCLR_CH3LIMITH_Pos   (12UL)

Position of CH3LIMITH field.

◆ SAADC_INTENCLR_CH3LIMITL_Clear

#define SAADC_INTENCLR_CH3LIMITL_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH3LIMITL_Disabled

#define SAADC_INTENCLR_CH3LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH3LIMITL_Enabled

#define SAADC_INTENCLR_CH3LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH3LIMITL_Msk

#define SAADC_INTENCLR_CH3LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos)

Bit mask of CH3LIMITL field.

◆ SAADC_INTENCLR_CH3LIMITL_Pos

#define SAADC_INTENCLR_CH3LIMITL_Pos   (13UL)

Position of CH3LIMITL field.

◆ SAADC_INTENCLR_CH4LIMITH_Clear

#define SAADC_INTENCLR_CH4LIMITH_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH4LIMITH_Disabled

#define SAADC_INTENCLR_CH4LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH4LIMITH_Enabled

#define SAADC_INTENCLR_CH4LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH4LIMITH_Msk

#define SAADC_INTENCLR_CH4LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos)

Bit mask of CH4LIMITH field.

◆ SAADC_INTENCLR_CH4LIMITH_Pos

#define SAADC_INTENCLR_CH4LIMITH_Pos   (14UL)

Position of CH4LIMITH field.

◆ SAADC_INTENCLR_CH4LIMITL_Clear

#define SAADC_INTENCLR_CH4LIMITL_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH4LIMITL_Disabled

#define SAADC_INTENCLR_CH4LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH4LIMITL_Enabled

#define SAADC_INTENCLR_CH4LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH4LIMITL_Msk

#define SAADC_INTENCLR_CH4LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos)

Bit mask of CH4LIMITL field.

◆ SAADC_INTENCLR_CH4LIMITL_Pos

#define SAADC_INTENCLR_CH4LIMITL_Pos   (15UL)

Position of CH4LIMITL field.

◆ SAADC_INTENCLR_CH5LIMITH_Clear

#define SAADC_INTENCLR_CH5LIMITH_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH5LIMITH_Disabled

#define SAADC_INTENCLR_CH5LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH5LIMITH_Enabled

#define SAADC_INTENCLR_CH5LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH5LIMITH_Msk

#define SAADC_INTENCLR_CH5LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos)

Bit mask of CH5LIMITH field.

◆ SAADC_INTENCLR_CH5LIMITH_Pos

#define SAADC_INTENCLR_CH5LIMITH_Pos   (16UL)

Position of CH5LIMITH field.

◆ SAADC_INTENCLR_CH5LIMITL_Clear

#define SAADC_INTENCLR_CH5LIMITL_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH5LIMITL_Disabled

#define SAADC_INTENCLR_CH5LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH5LIMITL_Enabled

#define SAADC_INTENCLR_CH5LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH5LIMITL_Msk

#define SAADC_INTENCLR_CH5LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos)

Bit mask of CH5LIMITL field.

◆ SAADC_INTENCLR_CH5LIMITL_Pos

#define SAADC_INTENCLR_CH5LIMITL_Pos   (17UL)

Position of CH5LIMITL field.

◆ SAADC_INTENCLR_CH6LIMITH_Clear

#define SAADC_INTENCLR_CH6LIMITH_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH6LIMITH_Disabled

#define SAADC_INTENCLR_CH6LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH6LIMITH_Enabled

#define SAADC_INTENCLR_CH6LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH6LIMITH_Msk

#define SAADC_INTENCLR_CH6LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos)

Bit mask of CH6LIMITH field.

◆ SAADC_INTENCLR_CH6LIMITH_Pos

#define SAADC_INTENCLR_CH6LIMITH_Pos   (18UL)

Position of CH6LIMITH field.

◆ SAADC_INTENCLR_CH6LIMITL_Clear

#define SAADC_INTENCLR_CH6LIMITL_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH6LIMITL_Disabled

#define SAADC_INTENCLR_CH6LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH6LIMITL_Enabled

#define SAADC_INTENCLR_CH6LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH6LIMITL_Msk

#define SAADC_INTENCLR_CH6LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos)

Bit mask of CH6LIMITL field.

◆ SAADC_INTENCLR_CH6LIMITL_Pos

#define SAADC_INTENCLR_CH6LIMITL_Pos   (19UL)

Position of CH6LIMITL field.

◆ SAADC_INTENCLR_CH7LIMITH_Clear

#define SAADC_INTENCLR_CH7LIMITH_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH7LIMITH_Disabled

#define SAADC_INTENCLR_CH7LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH7LIMITH_Enabled

#define SAADC_INTENCLR_CH7LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH7LIMITH_Msk

#define SAADC_INTENCLR_CH7LIMITH_Msk   (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos)

Bit mask of CH7LIMITH field.

◆ SAADC_INTENCLR_CH7LIMITH_Pos

#define SAADC_INTENCLR_CH7LIMITH_Pos   (20UL)

Position of CH7LIMITH field.

◆ SAADC_INTENCLR_CH7LIMITL_Clear

#define SAADC_INTENCLR_CH7LIMITL_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_CH7LIMITL_Disabled

#define SAADC_INTENCLR_CH7LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_CH7LIMITL_Enabled

#define SAADC_INTENCLR_CH7LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_CH7LIMITL_Msk

#define SAADC_INTENCLR_CH7LIMITL_Msk   (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos)

Bit mask of CH7LIMITL field.

◆ SAADC_INTENCLR_CH7LIMITL_Pos

#define SAADC_INTENCLR_CH7LIMITL_Pos   (21UL)

Position of CH7LIMITL field.

◆ SAADC_INTENCLR_DONE_Clear

#define SAADC_INTENCLR_DONE_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_DONE_Disabled

#define SAADC_INTENCLR_DONE_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_DONE_Enabled

#define SAADC_INTENCLR_DONE_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_DONE_Msk

#define SAADC_INTENCLR_DONE_Msk   (0x1UL << SAADC_INTENCLR_DONE_Pos)

Bit mask of DONE field.

◆ SAADC_INTENCLR_DONE_Pos

#define SAADC_INTENCLR_DONE_Pos   (2UL)

Position of DONE field.

◆ SAADC_INTENCLR_END_Clear

#define SAADC_INTENCLR_END_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_END_Disabled

#define SAADC_INTENCLR_END_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_END_Enabled

#define SAADC_INTENCLR_END_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_END_Msk

#define SAADC_INTENCLR_END_Msk   (0x1UL << SAADC_INTENCLR_END_Pos)

Bit mask of END field.

◆ SAADC_INTENCLR_END_Pos

#define SAADC_INTENCLR_END_Pos   (1UL)

Position of END field.

◆ SAADC_INTENCLR_RESULTDONE_Clear

#define SAADC_INTENCLR_RESULTDONE_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_RESULTDONE_Disabled

#define SAADC_INTENCLR_RESULTDONE_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_RESULTDONE_Enabled

#define SAADC_INTENCLR_RESULTDONE_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_RESULTDONE_Msk

#define SAADC_INTENCLR_RESULTDONE_Msk   (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos)

Bit mask of RESULTDONE field.

◆ SAADC_INTENCLR_RESULTDONE_Pos

#define SAADC_INTENCLR_RESULTDONE_Pos   (3UL)

Position of RESULTDONE field.

◆ SAADC_INTENCLR_STARTED_Clear

#define SAADC_INTENCLR_STARTED_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_STARTED_Disabled

#define SAADC_INTENCLR_STARTED_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_STARTED_Enabled

#define SAADC_INTENCLR_STARTED_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_STARTED_Msk

#define SAADC_INTENCLR_STARTED_Msk   (0x1UL << SAADC_INTENCLR_STARTED_Pos)

Bit mask of STARTED field.

◆ SAADC_INTENCLR_STARTED_Pos

#define SAADC_INTENCLR_STARTED_Pos   (0UL)

Position of STARTED field.

◆ SAADC_INTENCLR_STOPPED_Clear

#define SAADC_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ SAADC_INTENCLR_STOPPED_Disabled

#define SAADC_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENCLR_STOPPED_Enabled

#define SAADC_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENCLR_STOPPED_Msk

#define SAADC_INTENCLR_STOPPED_Msk   (0x1UL << SAADC_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ SAADC_INTENCLR_STOPPED_Pos

#define SAADC_INTENCLR_STOPPED_Pos   (5UL)

Position of STOPPED field.

◆ SAADC_INTENSET_CALIBRATEDONE_Disabled

#define SAADC_INTENSET_CALIBRATEDONE_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CALIBRATEDONE_Enabled

#define SAADC_INTENSET_CALIBRATEDONE_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CALIBRATEDONE_Msk

#define SAADC_INTENSET_CALIBRATEDONE_Msk   (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos)

Bit mask of CALIBRATEDONE field.

◆ SAADC_INTENSET_CALIBRATEDONE_Pos

#define SAADC_INTENSET_CALIBRATEDONE_Pos   (4UL)

Position of CALIBRATEDONE field.

◆ SAADC_INTENSET_CALIBRATEDONE_Set

#define SAADC_INTENSET_CALIBRATEDONE_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH0LIMITH_Disabled

#define SAADC_INTENSET_CH0LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH0LIMITH_Enabled

#define SAADC_INTENSET_CH0LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH0LIMITH_Msk

#define SAADC_INTENSET_CH0LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos)

Bit mask of CH0LIMITH field.

◆ SAADC_INTENSET_CH0LIMITH_Pos

#define SAADC_INTENSET_CH0LIMITH_Pos   (6UL)

Position of CH0LIMITH field.

◆ SAADC_INTENSET_CH0LIMITH_Set

#define SAADC_INTENSET_CH0LIMITH_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH0LIMITL_Disabled

#define SAADC_INTENSET_CH0LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH0LIMITL_Enabled

#define SAADC_INTENSET_CH0LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH0LIMITL_Msk

#define SAADC_INTENSET_CH0LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos)

Bit mask of CH0LIMITL field.

◆ SAADC_INTENSET_CH0LIMITL_Pos

#define SAADC_INTENSET_CH0LIMITL_Pos   (7UL)

Position of CH0LIMITL field.

◆ SAADC_INTENSET_CH0LIMITL_Set

#define SAADC_INTENSET_CH0LIMITL_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH1LIMITH_Disabled

#define SAADC_INTENSET_CH1LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH1LIMITH_Enabled

#define SAADC_INTENSET_CH1LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH1LIMITH_Msk

#define SAADC_INTENSET_CH1LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos)

Bit mask of CH1LIMITH field.

◆ SAADC_INTENSET_CH1LIMITH_Pos

#define SAADC_INTENSET_CH1LIMITH_Pos   (8UL)

Position of CH1LIMITH field.

◆ SAADC_INTENSET_CH1LIMITH_Set

#define SAADC_INTENSET_CH1LIMITH_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH1LIMITL_Disabled

#define SAADC_INTENSET_CH1LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH1LIMITL_Enabled

#define SAADC_INTENSET_CH1LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH1LIMITL_Msk

#define SAADC_INTENSET_CH1LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos)

Bit mask of CH1LIMITL field.

◆ SAADC_INTENSET_CH1LIMITL_Pos

#define SAADC_INTENSET_CH1LIMITL_Pos   (9UL)

Position of CH1LIMITL field.

◆ SAADC_INTENSET_CH1LIMITL_Set

#define SAADC_INTENSET_CH1LIMITL_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH2LIMITH_Disabled

#define SAADC_INTENSET_CH2LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH2LIMITH_Enabled

#define SAADC_INTENSET_CH2LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH2LIMITH_Msk

#define SAADC_INTENSET_CH2LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos)

Bit mask of CH2LIMITH field.

◆ SAADC_INTENSET_CH2LIMITH_Pos

#define SAADC_INTENSET_CH2LIMITH_Pos   (10UL)

Position of CH2LIMITH field.

◆ SAADC_INTENSET_CH2LIMITH_Set

#define SAADC_INTENSET_CH2LIMITH_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH2LIMITL_Disabled

#define SAADC_INTENSET_CH2LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH2LIMITL_Enabled

#define SAADC_INTENSET_CH2LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH2LIMITL_Msk

#define SAADC_INTENSET_CH2LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos)

Bit mask of CH2LIMITL field.

◆ SAADC_INTENSET_CH2LIMITL_Pos

#define SAADC_INTENSET_CH2LIMITL_Pos   (11UL)

Position of CH2LIMITL field.

◆ SAADC_INTENSET_CH2LIMITL_Set

#define SAADC_INTENSET_CH2LIMITL_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH3LIMITH_Disabled

#define SAADC_INTENSET_CH3LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH3LIMITH_Enabled

#define SAADC_INTENSET_CH3LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH3LIMITH_Msk

#define SAADC_INTENSET_CH3LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos)

Bit mask of CH3LIMITH field.

◆ SAADC_INTENSET_CH3LIMITH_Pos

#define SAADC_INTENSET_CH3LIMITH_Pos   (12UL)

Position of CH3LIMITH field.

◆ SAADC_INTENSET_CH3LIMITH_Set

#define SAADC_INTENSET_CH3LIMITH_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH3LIMITL_Disabled

#define SAADC_INTENSET_CH3LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH3LIMITL_Enabled

#define SAADC_INTENSET_CH3LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH3LIMITL_Msk

#define SAADC_INTENSET_CH3LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos)

Bit mask of CH3LIMITL field.

◆ SAADC_INTENSET_CH3LIMITL_Pos

#define SAADC_INTENSET_CH3LIMITL_Pos   (13UL)

Position of CH3LIMITL field.

◆ SAADC_INTENSET_CH3LIMITL_Set

#define SAADC_INTENSET_CH3LIMITL_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH4LIMITH_Disabled

#define SAADC_INTENSET_CH4LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH4LIMITH_Enabled

#define SAADC_INTENSET_CH4LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH4LIMITH_Msk

#define SAADC_INTENSET_CH4LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos)

Bit mask of CH4LIMITH field.

◆ SAADC_INTENSET_CH4LIMITH_Pos

#define SAADC_INTENSET_CH4LIMITH_Pos   (14UL)

Position of CH4LIMITH field.

◆ SAADC_INTENSET_CH4LIMITH_Set

#define SAADC_INTENSET_CH4LIMITH_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH4LIMITL_Disabled

#define SAADC_INTENSET_CH4LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH4LIMITL_Enabled

#define SAADC_INTENSET_CH4LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH4LIMITL_Msk

#define SAADC_INTENSET_CH4LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos)

Bit mask of CH4LIMITL field.

◆ SAADC_INTENSET_CH4LIMITL_Pos

#define SAADC_INTENSET_CH4LIMITL_Pos   (15UL)

Position of CH4LIMITL field.

◆ SAADC_INTENSET_CH4LIMITL_Set

#define SAADC_INTENSET_CH4LIMITL_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH5LIMITH_Disabled

#define SAADC_INTENSET_CH5LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH5LIMITH_Enabled

#define SAADC_INTENSET_CH5LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH5LIMITH_Msk

#define SAADC_INTENSET_CH5LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos)

Bit mask of CH5LIMITH field.

◆ SAADC_INTENSET_CH5LIMITH_Pos

#define SAADC_INTENSET_CH5LIMITH_Pos   (16UL)

Position of CH5LIMITH field.

◆ SAADC_INTENSET_CH5LIMITH_Set

#define SAADC_INTENSET_CH5LIMITH_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH5LIMITL_Disabled

#define SAADC_INTENSET_CH5LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH5LIMITL_Enabled

#define SAADC_INTENSET_CH5LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH5LIMITL_Msk

#define SAADC_INTENSET_CH5LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos)

Bit mask of CH5LIMITL field.

◆ SAADC_INTENSET_CH5LIMITL_Pos

#define SAADC_INTENSET_CH5LIMITL_Pos   (17UL)

Position of CH5LIMITL field.

◆ SAADC_INTENSET_CH5LIMITL_Set

#define SAADC_INTENSET_CH5LIMITL_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH6LIMITH_Disabled

#define SAADC_INTENSET_CH6LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH6LIMITH_Enabled

#define SAADC_INTENSET_CH6LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH6LIMITH_Msk

#define SAADC_INTENSET_CH6LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos)

Bit mask of CH6LIMITH field.

◆ SAADC_INTENSET_CH6LIMITH_Pos

#define SAADC_INTENSET_CH6LIMITH_Pos   (18UL)

Position of CH6LIMITH field.

◆ SAADC_INTENSET_CH6LIMITH_Set

#define SAADC_INTENSET_CH6LIMITH_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH6LIMITL_Disabled

#define SAADC_INTENSET_CH6LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH6LIMITL_Enabled

#define SAADC_INTENSET_CH6LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH6LIMITL_Msk

#define SAADC_INTENSET_CH6LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos)

Bit mask of CH6LIMITL field.

◆ SAADC_INTENSET_CH6LIMITL_Pos

#define SAADC_INTENSET_CH6LIMITL_Pos   (19UL)

Position of CH6LIMITL field.

◆ SAADC_INTENSET_CH6LIMITL_Set

#define SAADC_INTENSET_CH6LIMITL_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH7LIMITH_Disabled

#define SAADC_INTENSET_CH7LIMITH_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH7LIMITH_Enabled

#define SAADC_INTENSET_CH7LIMITH_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH7LIMITH_Msk

#define SAADC_INTENSET_CH7LIMITH_Msk   (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos)

Bit mask of CH7LIMITH field.

◆ SAADC_INTENSET_CH7LIMITH_Pos

#define SAADC_INTENSET_CH7LIMITH_Pos   (20UL)

Position of CH7LIMITH field.

◆ SAADC_INTENSET_CH7LIMITH_Set

#define SAADC_INTENSET_CH7LIMITH_Set   (1UL)

Enable

◆ SAADC_INTENSET_CH7LIMITL_Disabled

#define SAADC_INTENSET_CH7LIMITL_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_CH7LIMITL_Enabled

#define SAADC_INTENSET_CH7LIMITL_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_CH7LIMITL_Msk

#define SAADC_INTENSET_CH7LIMITL_Msk   (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos)

Bit mask of CH7LIMITL field.

◆ SAADC_INTENSET_CH7LIMITL_Pos

#define SAADC_INTENSET_CH7LIMITL_Pos   (21UL)

Position of CH7LIMITL field.

◆ SAADC_INTENSET_CH7LIMITL_Set

#define SAADC_INTENSET_CH7LIMITL_Set   (1UL)

Enable

◆ SAADC_INTENSET_DONE_Disabled

#define SAADC_INTENSET_DONE_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_DONE_Enabled

#define SAADC_INTENSET_DONE_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_DONE_Msk

#define SAADC_INTENSET_DONE_Msk   (0x1UL << SAADC_INTENSET_DONE_Pos)

Bit mask of DONE field.

◆ SAADC_INTENSET_DONE_Pos

#define SAADC_INTENSET_DONE_Pos   (2UL)

Position of DONE field.

◆ SAADC_INTENSET_DONE_Set

#define SAADC_INTENSET_DONE_Set   (1UL)

Enable

◆ SAADC_INTENSET_END_Disabled

#define SAADC_INTENSET_END_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_END_Enabled

#define SAADC_INTENSET_END_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_END_Msk

#define SAADC_INTENSET_END_Msk   (0x1UL << SAADC_INTENSET_END_Pos)

Bit mask of END field.

◆ SAADC_INTENSET_END_Pos

#define SAADC_INTENSET_END_Pos   (1UL)

Position of END field.

◆ SAADC_INTENSET_END_Set

#define SAADC_INTENSET_END_Set   (1UL)

Enable

◆ SAADC_INTENSET_RESULTDONE_Disabled

#define SAADC_INTENSET_RESULTDONE_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_RESULTDONE_Enabled

#define SAADC_INTENSET_RESULTDONE_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_RESULTDONE_Msk

#define SAADC_INTENSET_RESULTDONE_Msk   (0x1UL << SAADC_INTENSET_RESULTDONE_Pos)

Bit mask of RESULTDONE field.

◆ SAADC_INTENSET_RESULTDONE_Pos

#define SAADC_INTENSET_RESULTDONE_Pos   (3UL)

Position of RESULTDONE field.

◆ SAADC_INTENSET_RESULTDONE_Set

#define SAADC_INTENSET_RESULTDONE_Set   (1UL)

Enable

◆ SAADC_INTENSET_STARTED_Disabled

#define SAADC_INTENSET_STARTED_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_STARTED_Enabled

#define SAADC_INTENSET_STARTED_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_STARTED_Msk

#define SAADC_INTENSET_STARTED_Msk   (0x1UL << SAADC_INTENSET_STARTED_Pos)

Bit mask of STARTED field.

◆ SAADC_INTENSET_STARTED_Pos

#define SAADC_INTENSET_STARTED_Pos   (0UL)

Position of STARTED field.

◆ SAADC_INTENSET_STARTED_Set

#define SAADC_INTENSET_STARTED_Set   (1UL)

Enable

◆ SAADC_INTENSET_STOPPED_Disabled

#define SAADC_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ SAADC_INTENSET_STOPPED_Enabled

#define SAADC_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ SAADC_INTENSET_STOPPED_Msk

#define SAADC_INTENSET_STOPPED_Msk   (0x1UL << SAADC_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ SAADC_INTENSET_STOPPED_Pos

#define SAADC_INTENSET_STOPPED_Pos   (5UL)

Position of STOPPED field.

◆ SAADC_INTENSET_STOPPED_Set

#define SAADC_INTENSET_STOPPED_Set   (1UL)

Enable

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Bypass

#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass   (0UL)

Bypass oversampling

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Msk

#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk   (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos)

Bit mask of OVERSAMPLE field.

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Over128x

#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x   (7UL)

Oversample 128x

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Over16x

#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x   (4UL)

Oversample 16x

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Over256x

#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x   (8UL)

Oversample 256x

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Over2x

#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x   (1UL)

Oversample 2x

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Over32x

#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x   (5UL)

Oversample 32x

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Over4x

#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x   (2UL)

Oversample 4x

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Over64x

#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x   (6UL)

Oversample 64x

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Over8x

#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x   (3UL)

Oversample 8x

◆ SAADC_OVERSAMPLE_OVERSAMPLE_Pos

#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos   (0UL)

Position of OVERSAMPLE field.

◆ SAADC_RESOLUTION_VAL_10bit

#define SAADC_RESOLUTION_VAL_10bit   (1UL)

10 bit

◆ SAADC_RESOLUTION_VAL_12bit

#define SAADC_RESOLUTION_VAL_12bit   (2UL)

12 bit

◆ SAADC_RESOLUTION_VAL_14bit

#define SAADC_RESOLUTION_VAL_14bit   (3UL)

14 bit

◆ SAADC_RESOLUTION_VAL_8bit

#define SAADC_RESOLUTION_VAL_8bit   (0UL)

8 bit

◆ SAADC_RESOLUTION_VAL_Msk

#define SAADC_RESOLUTION_VAL_Msk   (0x7UL << SAADC_RESOLUTION_VAL_Pos)

Bit mask of VAL field.

◆ SAADC_RESOLUTION_VAL_Pos

#define SAADC_RESOLUTION_VAL_Pos   (0UL)

Position of VAL field.

◆ SAADC_RESULT_AMOUNT_AMOUNT_Msk

#define SAADC_RESULT_AMOUNT_AMOUNT_Msk   (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ SAADC_RESULT_AMOUNT_AMOUNT_Pos

#define SAADC_RESULT_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ SAADC_RESULT_MAXCNT_MAXCNT_Msk

#define SAADC_RESULT_MAXCNT_MAXCNT_Msk   (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ SAADC_RESULT_MAXCNT_MAXCNT_Pos

#define SAADC_RESULT_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ SAADC_RESULT_PTR_PTR_Msk

#define SAADC_RESULT_PTR_PTR_Msk   (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos)

Bit mask of PTR field.

◆ SAADC_RESULT_PTR_PTR_Pos

#define SAADC_RESULT_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ SAADC_SAMPLERATE_CC_Msk

#define SAADC_SAMPLERATE_CC_Msk   (0x7FFUL << SAADC_SAMPLERATE_CC_Pos)

Bit mask of CC field.

◆ SAADC_SAMPLERATE_CC_Pos

#define SAADC_SAMPLERATE_CC_Pos   (0UL)

Position of CC field.

◆ SAADC_SAMPLERATE_MODE_Msk

#define SAADC_SAMPLERATE_MODE_Msk   (0x1UL << SAADC_SAMPLERATE_MODE_Pos)

Bit mask of MODE field.

◆ SAADC_SAMPLERATE_MODE_Pos

#define SAADC_SAMPLERATE_MODE_Pos   (12UL)

Position of MODE field.

◆ SAADC_SAMPLERATE_MODE_Task

#define SAADC_SAMPLERATE_MODE_Task   (0UL)

Rate is controlled from SAMPLE task

◆ SAADC_SAMPLERATE_MODE_Timers

#define SAADC_SAMPLERATE_MODE_Timers   (1UL)

Rate is controlled from local timer (use CC to control the rate)

◆ SAADC_STATUS_STATUS_Busy

#define SAADC_STATUS_STATUS_Busy   (1UL)

ADC is busy. Conversion in progress.

◆ SAADC_STATUS_STATUS_Msk

#define SAADC_STATUS_STATUS_Msk   (0x1UL << SAADC_STATUS_STATUS_Pos)

Bit mask of STATUS field.

◆ SAADC_STATUS_STATUS_Pos

#define SAADC_STATUS_STATUS_Pos   (0UL)

Position of STATUS field.

◆ SAADC_STATUS_STATUS_Ready

#define SAADC_STATUS_STATUS_Ready   (0UL)

ADC is ready. No on-going conversion.

◆ SPI_CONFIG_CPHA_Leading

#define SPI_CONFIG_CPHA_Leading   (0UL)

Sample on leading edge of clock, shift serial data on trailing edge

◆ SPI_CONFIG_CPHA_Msk

#define SPI_CONFIG_CPHA_Msk   (0x1UL << SPI_CONFIG_CPHA_Pos)

Bit mask of CPHA field.

◆ SPI_CONFIG_CPHA_Pos

#define SPI_CONFIG_CPHA_Pos   (1UL)

Position of CPHA field.

◆ SPI_CONFIG_CPHA_Trailing

#define SPI_CONFIG_CPHA_Trailing   (1UL)

Sample on trailing edge of clock, shift serial data on leading edge

◆ SPI_CONFIG_CPOL_ActiveHigh

#define SPI_CONFIG_CPOL_ActiveHigh   (0UL)

Active high

◆ SPI_CONFIG_CPOL_ActiveLow

#define SPI_CONFIG_CPOL_ActiveLow   (1UL)

Active low

◆ SPI_CONFIG_CPOL_Msk

#define SPI_CONFIG_CPOL_Msk   (0x1UL << SPI_CONFIG_CPOL_Pos)

Bit mask of CPOL field.

◆ SPI_CONFIG_CPOL_Pos

#define SPI_CONFIG_CPOL_Pos   (2UL)

Position of CPOL field.

◆ SPI_CONFIG_ORDER_LsbFirst

#define SPI_CONFIG_ORDER_LsbFirst   (1UL)

Least significant bit shifted out first

◆ SPI_CONFIG_ORDER_MsbFirst

#define SPI_CONFIG_ORDER_MsbFirst   (0UL)

Most significant bit shifted out first

◆ SPI_CONFIG_ORDER_Msk

#define SPI_CONFIG_ORDER_Msk   (0x1UL << SPI_CONFIG_ORDER_Pos)

Bit mask of ORDER field.

◆ SPI_CONFIG_ORDER_Pos

#define SPI_CONFIG_ORDER_Pos   (0UL)

Position of ORDER field.

◆ SPI_ENABLE_ENABLE_Disabled

#define SPI_ENABLE_ENABLE_Disabled   (0UL)

Disable SPI

◆ SPI_ENABLE_ENABLE_Enabled

#define SPI_ENABLE_ENABLE_Enabled   (1UL)

Enable SPI

◆ SPI_ENABLE_ENABLE_Msk

#define SPI_ENABLE_ENABLE_Msk   (0xFUL << SPI_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ SPI_ENABLE_ENABLE_Pos

#define SPI_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ SPI_FREQUENCY_FREQUENCY_K125

#define SPI_FREQUENCY_FREQUENCY_K125   (0x02000000UL)

125 kbps

◆ SPI_FREQUENCY_FREQUENCY_K250

#define SPI_FREQUENCY_FREQUENCY_K250   (0x04000000UL)

250 kbps

◆ SPI_FREQUENCY_FREQUENCY_K500

#define SPI_FREQUENCY_FREQUENCY_K500   (0x08000000UL)

500 kbps

◆ SPI_FREQUENCY_FREQUENCY_M1

#define SPI_FREQUENCY_FREQUENCY_M1   (0x10000000UL)

1 Mbps

◆ SPI_FREQUENCY_FREQUENCY_M2

#define SPI_FREQUENCY_FREQUENCY_M2   (0x20000000UL)

2 Mbps

◆ SPI_FREQUENCY_FREQUENCY_M4

#define SPI_FREQUENCY_FREQUENCY_M4   (0x40000000UL)

4 Mbps

◆ SPI_FREQUENCY_FREQUENCY_M8

#define SPI_FREQUENCY_FREQUENCY_M8   (0x80000000UL)

8 Mbps

◆ SPI_FREQUENCY_FREQUENCY_Msk

#define SPI_FREQUENCY_FREQUENCY_Msk   (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

◆ SPI_FREQUENCY_FREQUENCY_Pos

#define SPI_FREQUENCY_FREQUENCY_Pos   (0UL)

Position of FREQUENCY field.

◆ SPI_INTENCLR_READY_Clear

#define SPI_INTENCLR_READY_Clear   (1UL)

Disable

◆ SPI_INTENCLR_READY_Disabled

#define SPI_INTENCLR_READY_Disabled   (0UL)

Read: Disabled

◆ SPI_INTENCLR_READY_Enabled

#define SPI_INTENCLR_READY_Enabled   (1UL)

Read: Enabled

◆ SPI_INTENCLR_READY_Msk

#define SPI_INTENCLR_READY_Msk   (0x1UL << SPI_INTENCLR_READY_Pos)

Bit mask of READY field.

◆ SPI_INTENCLR_READY_Pos

#define SPI_INTENCLR_READY_Pos   (2UL)

Position of READY field.

◆ SPI_INTENSET_READY_Disabled

#define SPI_INTENSET_READY_Disabled   (0UL)

Read: Disabled

◆ SPI_INTENSET_READY_Enabled

#define SPI_INTENSET_READY_Enabled   (1UL)

Read: Enabled

◆ SPI_INTENSET_READY_Msk

#define SPI_INTENSET_READY_Msk   (0x1UL << SPI_INTENSET_READY_Pos)

Bit mask of READY field.

◆ SPI_INTENSET_READY_Pos

#define SPI_INTENSET_READY_Pos   (2UL)

Position of READY field.

◆ SPI_INTENSET_READY_Set

#define SPI_INTENSET_READY_Set   (1UL)

Enable

◆ SPI_PSEL_MISO_PSELMISO_Disconnected

#define SPI_PSEL_MISO_PSELMISO_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ SPI_PSEL_MISO_PSELMISO_Msk

#define SPI_PSEL_MISO_PSELMISO_Msk   (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos)

Bit mask of PSELMISO field.

◆ SPI_PSEL_MISO_PSELMISO_Pos

#define SPI_PSEL_MISO_PSELMISO_Pos   (0UL)

Position of PSELMISO field.

◆ SPI_PSEL_MOSI_PSELMOSI_Disconnected

#define SPI_PSEL_MOSI_PSELMOSI_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ SPI_PSEL_MOSI_PSELMOSI_Msk

#define SPI_PSEL_MOSI_PSELMOSI_Msk   (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos)

Bit mask of PSELMOSI field.

◆ SPI_PSEL_MOSI_PSELMOSI_Pos

#define SPI_PSEL_MOSI_PSELMOSI_Pos   (0UL)

Position of PSELMOSI field.

◆ SPI_PSEL_SCK_PSELSCK_Disconnected

#define SPI_PSEL_SCK_PSELSCK_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ SPI_PSEL_SCK_PSELSCK_Msk

#define SPI_PSEL_SCK_PSELSCK_Msk   (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos)

Bit mask of PSELSCK field.

◆ SPI_PSEL_SCK_PSELSCK_Pos

#define SPI_PSEL_SCK_PSELSCK_Pos   (0UL)

Position of PSELSCK field.

◆ SPI_RXD_RXD_Msk

#define SPI_RXD_RXD_Msk   (0xFFUL << SPI_RXD_RXD_Pos)

Bit mask of RXD field.

◆ SPI_RXD_RXD_Pos

#define SPI_RXD_RXD_Pos   (0UL)

Position of RXD field.

◆ SPI_TXD_TXD_Msk

#define SPI_TXD_TXD_Msk   (0xFFUL << SPI_TXD_TXD_Pos)

Bit mask of TXD field.

◆ SPI_TXD_TXD_Pos

#define SPI_TXD_TXD_Pos   (0UL)

Position of TXD field.

◆ SPIM_CONFIG_CPHA_Leading

#define SPIM_CONFIG_CPHA_Leading   (0UL)

Sample on leading edge of clock, shift serial data on trailing edge

◆ SPIM_CONFIG_CPHA_Msk

#define SPIM_CONFIG_CPHA_Msk   (0x1UL << SPIM_CONFIG_CPHA_Pos)

Bit mask of CPHA field.

◆ SPIM_CONFIG_CPHA_Pos

#define SPIM_CONFIG_CPHA_Pos   (1UL)

Position of CPHA field.

◆ SPIM_CONFIG_CPHA_Trailing

#define SPIM_CONFIG_CPHA_Trailing   (1UL)

Sample on trailing edge of clock, shift serial data on leading edge

◆ SPIM_CONFIG_CPOL_ActiveHigh

#define SPIM_CONFIG_CPOL_ActiveHigh   (0UL)

Active high

◆ SPIM_CONFIG_CPOL_ActiveLow

#define SPIM_CONFIG_CPOL_ActiveLow   (1UL)

Active low

◆ SPIM_CONFIG_CPOL_Msk

#define SPIM_CONFIG_CPOL_Msk   (0x1UL << SPIM_CONFIG_CPOL_Pos)

Bit mask of CPOL field.

◆ SPIM_CONFIG_CPOL_Pos

#define SPIM_CONFIG_CPOL_Pos   (2UL)

Position of CPOL field.

◆ SPIM_CONFIG_ORDER_LsbFirst

#define SPIM_CONFIG_ORDER_LsbFirst   (1UL)

Least significant bit shifted out first

◆ SPIM_CONFIG_ORDER_MsbFirst

#define SPIM_CONFIG_ORDER_MsbFirst   (0UL)

Most significant bit shifted out first

◆ SPIM_CONFIG_ORDER_Msk

#define SPIM_CONFIG_ORDER_Msk   (0x1UL << SPIM_CONFIG_ORDER_Pos)

Bit mask of ORDER field.

◆ SPIM_CONFIG_ORDER_Pos

#define SPIM_CONFIG_ORDER_Pos   (0UL)

Position of ORDER field.

◆ SPIM_ENABLE_ENABLE_Disabled

#define SPIM_ENABLE_ENABLE_Disabled   (0UL)

Disable SPIM

◆ SPIM_ENABLE_ENABLE_Enabled

#define SPIM_ENABLE_ENABLE_Enabled   (7UL)

Enable SPIM

◆ SPIM_ENABLE_ENABLE_Msk

#define SPIM_ENABLE_ENABLE_Msk   (0xFUL << SPIM_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ SPIM_ENABLE_ENABLE_Pos

#define SPIM_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ SPIM_FREQUENCY_FREQUENCY_K125

#define SPIM_FREQUENCY_FREQUENCY_K125   (0x02000000UL)

125 kbps

◆ SPIM_FREQUENCY_FREQUENCY_K250

#define SPIM_FREQUENCY_FREQUENCY_K250   (0x04000000UL)

250 kbps

◆ SPIM_FREQUENCY_FREQUENCY_K500

#define SPIM_FREQUENCY_FREQUENCY_K500   (0x08000000UL)

500 kbps

◆ SPIM_FREQUENCY_FREQUENCY_M1

#define SPIM_FREQUENCY_FREQUENCY_M1   (0x10000000UL)

1 Mbps

◆ SPIM_FREQUENCY_FREQUENCY_M2

#define SPIM_FREQUENCY_FREQUENCY_M2   (0x20000000UL)

2 Mbps

◆ SPIM_FREQUENCY_FREQUENCY_M4

#define SPIM_FREQUENCY_FREQUENCY_M4   (0x40000000UL)

4 Mbps

◆ SPIM_FREQUENCY_FREQUENCY_M8

#define SPIM_FREQUENCY_FREQUENCY_M8   (0x80000000UL)

8 Mbps

◆ SPIM_FREQUENCY_FREQUENCY_Msk

#define SPIM_FREQUENCY_FREQUENCY_Msk   (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

◆ SPIM_FREQUENCY_FREQUENCY_Pos

#define SPIM_FREQUENCY_FREQUENCY_Pos   (0UL)

Position of FREQUENCY field.

◆ SPIM_INTENCLR_END_Clear

#define SPIM_INTENCLR_END_Clear   (1UL)

Disable

◆ SPIM_INTENCLR_END_Disabled

#define SPIM_INTENCLR_END_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENCLR_END_Enabled

#define SPIM_INTENCLR_END_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENCLR_END_Msk

#define SPIM_INTENCLR_END_Msk   (0x1UL << SPIM_INTENCLR_END_Pos)

Bit mask of END field.

◆ SPIM_INTENCLR_END_Pos

#define SPIM_INTENCLR_END_Pos   (6UL)

Position of END field.

◆ SPIM_INTENCLR_ENDRX_Clear

#define SPIM_INTENCLR_ENDRX_Clear   (1UL)

Disable

◆ SPIM_INTENCLR_ENDRX_Disabled

#define SPIM_INTENCLR_ENDRX_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENCLR_ENDRX_Enabled

#define SPIM_INTENCLR_ENDRX_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENCLR_ENDRX_Msk

#define SPIM_INTENCLR_ENDRX_Msk   (0x1UL << SPIM_INTENCLR_ENDRX_Pos)

Bit mask of ENDRX field.

◆ SPIM_INTENCLR_ENDRX_Pos

#define SPIM_INTENCLR_ENDRX_Pos   (4UL)

Position of ENDRX field.

◆ SPIM_INTENCLR_ENDTX_Clear

#define SPIM_INTENCLR_ENDTX_Clear   (1UL)

Disable

◆ SPIM_INTENCLR_ENDTX_Disabled

#define SPIM_INTENCLR_ENDTX_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENCLR_ENDTX_Enabled

#define SPIM_INTENCLR_ENDTX_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENCLR_ENDTX_Msk

#define SPIM_INTENCLR_ENDTX_Msk   (0x1UL << SPIM_INTENCLR_ENDTX_Pos)

Bit mask of ENDTX field.

◆ SPIM_INTENCLR_ENDTX_Pos

#define SPIM_INTENCLR_ENDTX_Pos   (8UL)

Position of ENDTX field.

◆ SPIM_INTENCLR_STARTED_Clear

#define SPIM_INTENCLR_STARTED_Clear   (1UL)

Disable

◆ SPIM_INTENCLR_STARTED_Disabled

#define SPIM_INTENCLR_STARTED_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENCLR_STARTED_Enabled

#define SPIM_INTENCLR_STARTED_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENCLR_STARTED_Msk

#define SPIM_INTENCLR_STARTED_Msk   (0x1UL << SPIM_INTENCLR_STARTED_Pos)

Bit mask of STARTED field.

◆ SPIM_INTENCLR_STARTED_Pos

#define SPIM_INTENCLR_STARTED_Pos   (19UL)

Position of STARTED field.

◆ SPIM_INTENCLR_STOPPED_Clear

#define SPIM_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ SPIM_INTENCLR_STOPPED_Disabled

#define SPIM_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENCLR_STOPPED_Enabled

#define SPIM_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENCLR_STOPPED_Msk

#define SPIM_INTENCLR_STOPPED_Msk   (0x1UL << SPIM_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ SPIM_INTENCLR_STOPPED_Pos

#define SPIM_INTENCLR_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ SPIM_INTENSET_END_Disabled

#define SPIM_INTENSET_END_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENSET_END_Enabled

#define SPIM_INTENSET_END_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENSET_END_Msk

#define SPIM_INTENSET_END_Msk   (0x1UL << SPIM_INTENSET_END_Pos)

Bit mask of END field.

◆ SPIM_INTENSET_END_Pos

#define SPIM_INTENSET_END_Pos   (6UL)

Position of END field.

◆ SPIM_INTENSET_END_Set

#define SPIM_INTENSET_END_Set   (1UL)

Enable

◆ SPIM_INTENSET_ENDRX_Disabled

#define SPIM_INTENSET_ENDRX_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENSET_ENDRX_Enabled

#define SPIM_INTENSET_ENDRX_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENSET_ENDRX_Msk

#define SPIM_INTENSET_ENDRX_Msk   (0x1UL << SPIM_INTENSET_ENDRX_Pos)

Bit mask of ENDRX field.

◆ SPIM_INTENSET_ENDRX_Pos

#define SPIM_INTENSET_ENDRX_Pos   (4UL)

Position of ENDRX field.

◆ SPIM_INTENSET_ENDRX_Set

#define SPIM_INTENSET_ENDRX_Set   (1UL)

Enable

◆ SPIM_INTENSET_ENDTX_Disabled

#define SPIM_INTENSET_ENDTX_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENSET_ENDTX_Enabled

#define SPIM_INTENSET_ENDTX_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENSET_ENDTX_Msk

#define SPIM_INTENSET_ENDTX_Msk   (0x1UL << SPIM_INTENSET_ENDTX_Pos)

Bit mask of ENDTX field.

◆ SPIM_INTENSET_ENDTX_Pos

#define SPIM_INTENSET_ENDTX_Pos   (8UL)

Position of ENDTX field.

◆ SPIM_INTENSET_ENDTX_Set

#define SPIM_INTENSET_ENDTX_Set   (1UL)

Enable

◆ SPIM_INTENSET_STARTED_Disabled

#define SPIM_INTENSET_STARTED_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENSET_STARTED_Enabled

#define SPIM_INTENSET_STARTED_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENSET_STARTED_Msk

#define SPIM_INTENSET_STARTED_Msk   (0x1UL << SPIM_INTENSET_STARTED_Pos)

Bit mask of STARTED field.

◆ SPIM_INTENSET_STARTED_Pos

#define SPIM_INTENSET_STARTED_Pos   (19UL)

Position of STARTED field.

◆ SPIM_INTENSET_STARTED_Set

#define SPIM_INTENSET_STARTED_Set   (1UL)

Enable

◆ SPIM_INTENSET_STOPPED_Disabled

#define SPIM_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ SPIM_INTENSET_STOPPED_Enabled

#define SPIM_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ SPIM_INTENSET_STOPPED_Msk

#define SPIM_INTENSET_STOPPED_Msk   (0x1UL << SPIM_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ SPIM_INTENSET_STOPPED_Pos

#define SPIM_INTENSET_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ SPIM_INTENSET_STOPPED_Set

#define SPIM_INTENSET_STOPPED_Set   (1UL)

Enable

◆ SPIM_ORC_ORC_Msk

#define SPIM_ORC_ORC_Msk   (0xFFUL << SPIM_ORC_ORC_Pos)

Bit mask of ORC field.

◆ SPIM_ORC_ORC_Pos

#define SPIM_ORC_ORC_Pos   (0UL)

Position of ORC field.

◆ SPIM_PSEL_MISO_CONNECT_Connected

#define SPIM_PSEL_MISO_CONNECT_Connected   (0UL)

Connect

◆ SPIM_PSEL_MISO_CONNECT_Disconnected

#define SPIM_PSEL_MISO_CONNECT_Disconnected   (1UL)

Disconnect

◆ SPIM_PSEL_MISO_CONNECT_Msk

#define SPIM_PSEL_MISO_CONNECT_Msk   (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos)

Bit mask of CONNECT field.

◆ SPIM_PSEL_MISO_CONNECT_Pos

#define SPIM_PSEL_MISO_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ SPIM_PSEL_MISO_PIN_Msk

#define SPIM_PSEL_MISO_PIN_Msk   (0x1FUL << SPIM_PSEL_MISO_PIN_Pos)

Bit mask of PIN field.

◆ SPIM_PSEL_MISO_PIN_Pos

#define SPIM_PSEL_MISO_PIN_Pos   (0UL)

Position of PIN field.

◆ SPIM_PSEL_MOSI_CONNECT_Connected

#define SPIM_PSEL_MOSI_CONNECT_Connected   (0UL)

Connect

◆ SPIM_PSEL_MOSI_CONNECT_Disconnected

#define SPIM_PSEL_MOSI_CONNECT_Disconnected   (1UL)

Disconnect

◆ SPIM_PSEL_MOSI_CONNECT_Msk

#define SPIM_PSEL_MOSI_CONNECT_Msk   (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos)

Bit mask of CONNECT field.

◆ SPIM_PSEL_MOSI_CONNECT_Pos

#define SPIM_PSEL_MOSI_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ SPIM_PSEL_MOSI_PIN_Msk

#define SPIM_PSEL_MOSI_PIN_Msk   (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos)

Bit mask of PIN field.

◆ SPIM_PSEL_MOSI_PIN_Pos

#define SPIM_PSEL_MOSI_PIN_Pos   (0UL)

Position of PIN field.

◆ SPIM_PSEL_SCK_CONNECT_Connected

#define SPIM_PSEL_SCK_CONNECT_Connected   (0UL)

Connect

◆ SPIM_PSEL_SCK_CONNECT_Disconnected

#define SPIM_PSEL_SCK_CONNECT_Disconnected   (1UL)

Disconnect

◆ SPIM_PSEL_SCK_CONNECT_Msk

#define SPIM_PSEL_SCK_CONNECT_Msk   (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos)

Bit mask of CONNECT field.

◆ SPIM_PSEL_SCK_CONNECT_Pos

#define SPIM_PSEL_SCK_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ SPIM_PSEL_SCK_PIN_Msk

#define SPIM_PSEL_SCK_PIN_Msk   (0x1FUL << SPIM_PSEL_SCK_PIN_Pos)

Bit mask of PIN field.

◆ SPIM_PSEL_SCK_PIN_Pos

#define SPIM_PSEL_SCK_PIN_Pos   (0UL)

Position of PIN field.

◆ SPIM_RXD_AMOUNT_AMOUNT_Msk

#define SPIM_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ SPIM_RXD_AMOUNT_AMOUNT_Pos

#define SPIM_RXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ SPIM_RXD_LIST_LIST_ArrayList

#define SPIM_RXD_LIST_LIST_ArrayList   (1UL)

Use array list

◆ SPIM_RXD_LIST_LIST_Disabled

#define SPIM_RXD_LIST_LIST_Disabled   (0UL)

Disable EasyDMA list

◆ SPIM_RXD_LIST_LIST_Msk

#define SPIM_RXD_LIST_LIST_Msk   (0x7UL << SPIM_RXD_LIST_LIST_Pos)

Bit mask of LIST field.

◆ SPIM_RXD_LIST_LIST_Pos

#define SPIM_RXD_LIST_LIST_Pos   (0UL)

Position of LIST field.

◆ SPIM_RXD_MAXCNT_MAXCNT_Msk

#define SPIM_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ SPIM_RXD_MAXCNT_MAXCNT_Pos

#define SPIM_RXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ SPIM_RXD_PTR_PTR_Msk

#define SPIM_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ SPIM_RXD_PTR_PTR_Pos

#define SPIM_RXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ SPIM_SHORTS_END_START_Disabled

#define SPIM_SHORTS_END_START_Disabled   (0UL)

Disable shortcut

◆ SPIM_SHORTS_END_START_Enabled

#define SPIM_SHORTS_END_START_Enabled   (1UL)

Enable shortcut

◆ SPIM_SHORTS_END_START_Msk

#define SPIM_SHORTS_END_START_Msk   (0x1UL << SPIM_SHORTS_END_START_Pos)

Bit mask of END_START field.

◆ SPIM_SHORTS_END_START_Pos

#define SPIM_SHORTS_END_START_Pos   (17UL)

Position of END_START field.

◆ SPIM_TXD_AMOUNT_AMOUNT_Msk

#define SPIM_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ SPIM_TXD_AMOUNT_AMOUNT_Pos

#define SPIM_TXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ SPIM_TXD_LIST_LIST_ArrayList

#define SPIM_TXD_LIST_LIST_ArrayList   (1UL)

Use array list

◆ SPIM_TXD_LIST_LIST_Disabled

#define SPIM_TXD_LIST_LIST_Disabled   (0UL)

Disable EasyDMA list

◆ SPIM_TXD_LIST_LIST_Msk

#define SPIM_TXD_LIST_LIST_Msk   (0x7UL << SPIM_TXD_LIST_LIST_Pos)

Bit mask of LIST field.

◆ SPIM_TXD_LIST_LIST_Pos

#define SPIM_TXD_LIST_LIST_Pos   (0UL)

Position of LIST field.

◆ SPIM_TXD_MAXCNT_MAXCNT_Msk

#define SPIM_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ SPIM_TXD_MAXCNT_MAXCNT_Pos

#define SPIM_TXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ SPIM_TXD_PTR_PTR_Msk

#define SPIM_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ SPIM_TXD_PTR_PTR_Pos

#define SPIM_TXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ SPIS_CONFIG_CPHA_Leading

#define SPIS_CONFIG_CPHA_Leading   (0UL)

Sample on leading edge of clock, shift serial data on trailing edge

◆ SPIS_CONFIG_CPHA_Msk

#define SPIS_CONFIG_CPHA_Msk   (0x1UL << SPIS_CONFIG_CPHA_Pos)

Bit mask of CPHA field.

◆ SPIS_CONFIG_CPHA_Pos

#define SPIS_CONFIG_CPHA_Pos   (1UL)

Position of CPHA field.

◆ SPIS_CONFIG_CPHA_Trailing

#define SPIS_CONFIG_CPHA_Trailing   (1UL)

Sample on trailing edge of clock, shift serial data on leading edge

◆ SPIS_CONFIG_CPOL_ActiveHigh

#define SPIS_CONFIG_CPOL_ActiveHigh   (0UL)

Active high

◆ SPIS_CONFIG_CPOL_ActiveLow

#define SPIS_CONFIG_CPOL_ActiveLow   (1UL)

Active low

◆ SPIS_CONFIG_CPOL_Msk

#define SPIS_CONFIG_CPOL_Msk   (0x1UL << SPIS_CONFIG_CPOL_Pos)

Bit mask of CPOL field.

◆ SPIS_CONFIG_CPOL_Pos

#define SPIS_CONFIG_CPOL_Pos   (2UL)

Position of CPOL field.

◆ SPIS_CONFIG_ORDER_LsbFirst

#define SPIS_CONFIG_ORDER_LsbFirst   (1UL)

Least significant bit shifted out first

◆ SPIS_CONFIG_ORDER_MsbFirst

#define SPIS_CONFIG_ORDER_MsbFirst   (0UL)

Most significant bit shifted out first

◆ SPIS_CONFIG_ORDER_Msk

#define SPIS_CONFIG_ORDER_Msk   (0x1UL << SPIS_CONFIG_ORDER_Pos)

Bit mask of ORDER field.

◆ SPIS_CONFIG_ORDER_Pos

#define SPIS_CONFIG_ORDER_Pos   (0UL)

Position of ORDER field.

◆ SPIS_DEF_DEF_Msk

#define SPIS_DEF_DEF_Msk   (0xFFUL << SPIS_DEF_DEF_Pos)

Bit mask of DEF field.

◆ SPIS_DEF_DEF_Pos

#define SPIS_DEF_DEF_Pos   (0UL)

Position of DEF field.

◆ SPIS_ENABLE_ENABLE_Disabled

#define SPIS_ENABLE_ENABLE_Disabled   (0UL)

Disable SPI slave

◆ SPIS_ENABLE_ENABLE_Enabled

#define SPIS_ENABLE_ENABLE_Enabled   (2UL)

Enable SPI slave

◆ SPIS_ENABLE_ENABLE_Msk

#define SPIS_ENABLE_ENABLE_Msk   (0xFUL << SPIS_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ SPIS_ENABLE_ENABLE_Pos

#define SPIS_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ SPIS_INTENCLR_ACQUIRED_Clear

#define SPIS_INTENCLR_ACQUIRED_Clear   (1UL)

Disable

◆ SPIS_INTENCLR_ACQUIRED_Disabled

#define SPIS_INTENCLR_ACQUIRED_Disabled   (0UL)

Read: Disabled

◆ SPIS_INTENCLR_ACQUIRED_Enabled

#define SPIS_INTENCLR_ACQUIRED_Enabled   (1UL)

Read: Enabled

◆ SPIS_INTENCLR_ACQUIRED_Msk

#define SPIS_INTENCLR_ACQUIRED_Msk   (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos)

Bit mask of ACQUIRED field.

◆ SPIS_INTENCLR_ACQUIRED_Pos

#define SPIS_INTENCLR_ACQUIRED_Pos   (10UL)

Position of ACQUIRED field.

◆ SPIS_INTENCLR_END_Clear

#define SPIS_INTENCLR_END_Clear   (1UL)

Disable

◆ SPIS_INTENCLR_END_Disabled

#define SPIS_INTENCLR_END_Disabled   (0UL)

Read: Disabled

◆ SPIS_INTENCLR_END_Enabled

#define SPIS_INTENCLR_END_Enabled   (1UL)

Read: Enabled

◆ SPIS_INTENCLR_END_Msk

#define SPIS_INTENCLR_END_Msk   (0x1UL << SPIS_INTENCLR_END_Pos)

Bit mask of END field.

◆ SPIS_INTENCLR_END_Pos

#define SPIS_INTENCLR_END_Pos   (1UL)

Position of END field.

◆ SPIS_INTENCLR_ENDRX_Clear

#define SPIS_INTENCLR_ENDRX_Clear   (1UL)

Disable

◆ SPIS_INTENCLR_ENDRX_Disabled

#define SPIS_INTENCLR_ENDRX_Disabled   (0UL)

Read: Disabled

◆ SPIS_INTENCLR_ENDRX_Enabled

#define SPIS_INTENCLR_ENDRX_Enabled   (1UL)

Read: Enabled

◆ SPIS_INTENCLR_ENDRX_Msk

#define SPIS_INTENCLR_ENDRX_Msk   (0x1UL << SPIS_INTENCLR_ENDRX_Pos)

Bit mask of ENDRX field.

◆ SPIS_INTENCLR_ENDRX_Pos

#define SPIS_INTENCLR_ENDRX_Pos   (4UL)

Position of ENDRX field.

◆ SPIS_INTENSET_ACQUIRED_Disabled

#define SPIS_INTENSET_ACQUIRED_Disabled   (0UL)

Read: Disabled

◆ SPIS_INTENSET_ACQUIRED_Enabled

#define SPIS_INTENSET_ACQUIRED_Enabled   (1UL)

Read: Enabled

◆ SPIS_INTENSET_ACQUIRED_Msk

#define SPIS_INTENSET_ACQUIRED_Msk   (0x1UL << SPIS_INTENSET_ACQUIRED_Pos)

Bit mask of ACQUIRED field.

◆ SPIS_INTENSET_ACQUIRED_Pos

#define SPIS_INTENSET_ACQUIRED_Pos   (10UL)

Position of ACQUIRED field.

◆ SPIS_INTENSET_ACQUIRED_Set

#define SPIS_INTENSET_ACQUIRED_Set   (1UL)

Enable

◆ SPIS_INTENSET_END_Disabled

#define SPIS_INTENSET_END_Disabled   (0UL)

Read: Disabled

◆ SPIS_INTENSET_END_Enabled

#define SPIS_INTENSET_END_Enabled   (1UL)

Read: Enabled

◆ SPIS_INTENSET_END_Msk

#define SPIS_INTENSET_END_Msk   (0x1UL << SPIS_INTENSET_END_Pos)

Bit mask of END field.

◆ SPIS_INTENSET_END_Pos

#define SPIS_INTENSET_END_Pos   (1UL)

Position of END field.

◆ SPIS_INTENSET_END_Set

#define SPIS_INTENSET_END_Set   (1UL)

Enable

◆ SPIS_INTENSET_ENDRX_Disabled

#define SPIS_INTENSET_ENDRX_Disabled   (0UL)

Read: Disabled

◆ SPIS_INTENSET_ENDRX_Enabled

#define SPIS_INTENSET_ENDRX_Enabled   (1UL)

Read: Enabled

◆ SPIS_INTENSET_ENDRX_Msk

#define SPIS_INTENSET_ENDRX_Msk   (0x1UL << SPIS_INTENSET_ENDRX_Pos)

Bit mask of ENDRX field.

◆ SPIS_INTENSET_ENDRX_Pos

#define SPIS_INTENSET_ENDRX_Pos   (4UL)

Position of ENDRX field.

◆ SPIS_INTENSET_ENDRX_Set

#define SPIS_INTENSET_ENDRX_Set   (1UL)

Enable

◆ SPIS_ORC_ORC_Msk

#define SPIS_ORC_ORC_Msk   (0xFFUL << SPIS_ORC_ORC_Pos)

Bit mask of ORC field.

◆ SPIS_ORC_ORC_Pos

#define SPIS_ORC_ORC_Pos   (0UL)

Position of ORC field.

◆ SPIS_PSEL_CSN_CONNECT_Connected

#define SPIS_PSEL_CSN_CONNECT_Connected   (0UL)

Connect

◆ SPIS_PSEL_CSN_CONNECT_Disconnected

#define SPIS_PSEL_CSN_CONNECT_Disconnected   (1UL)

Disconnect

◆ SPIS_PSEL_CSN_CONNECT_Msk

#define SPIS_PSEL_CSN_CONNECT_Msk   (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos)

Bit mask of CONNECT field.

◆ SPIS_PSEL_CSN_CONNECT_Pos

#define SPIS_PSEL_CSN_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ SPIS_PSEL_CSN_PIN_Msk

#define SPIS_PSEL_CSN_PIN_Msk   (0x1FUL << SPIS_PSEL_CSN_PIN_Pos)

Bit mask of PIN field.

◆ SPIS_PSEL_CSN_PIN_Pos

#define SPIS_PSEL_CSN_PIN_Pos   (0UL)

Position of PIN field.

◆ SPIS_PSEL_MISO_CONNECT_Connected

#define SPIS_PSEL_MISO_CONNECT_Connected   (0UL)

Connect

◆ SPIS_PSEL_MISO_CONNECT_Disconnected

#define SPIS_PSEL_MISO_CONNECT_Disconnected   (1UL)

Disconnect

◆ SPIS_PSEL_MISO_CONNECT_Msk

#define SPIS_PSEL_MISO_CONNECT_Msk   (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos)

Bit mask of CONNECT field.

◆ SPIS_PSEL_MISO_CONNECT_Pos

#define SPIS_PSEL_MISO_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ SPIS_PSEL_MISO_PIN_Msk

#define SPIS_PSEL_MISO_PIN_Msk   (0x1FUL << SPIS_PSEL_MISO_PIN_Pos)

Bit mask of PIN field.

◆ SPIS_PSEL_MISO_PIN_Pos

#define SPIS_PSEL_MISO_PIN_Pos   (0UL)

Position of PIN field.

◆ SPIS_PSEL_MOSI_CONNECT_Connected

#define SPIS_PSEL_MOSI_CONNECT_Connected   (0UL)

Connect

◆ SPIS_PSEL_MOSI_CONNECT_Disconnected

#define SPIS_PSEL_MOSI_CONNECT_Disconnected   (1UL)

Disconnect

◆ SPIS_PSEL_MOSI_CONNECT_Msk

#define SPIS_PSEL_MOSI_CONNECT_Msk   (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos)

Bit mask of CONNECT field.

◆ SPIS_PSEL_MOSI_CONNECT_Pos

#define SPIS_PSEL_MOSI_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ SPIS_PSEL_MOSI_PIN_Msk

#define SPIS_PSEL_MOSI_PIN_Msk   (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos)

Bit mask of PIN field.

◆ SPIS_PSEL_MOSI_PIN_Pos

#define SPIS_PSEL_MOSI_PIN_Pos   (0UL)

Position of PIN field.

◆ SPIS_PSEL_SCK_CONNECT_Connected

#define SPIS_PSEL_SCK_CONNECT_Connected   (0UL)

Connect

◆ SPIS_PSEL_SCK_CONNECT_Disconnected

#define SPIS_PSEL_SCK_CONNECT_Disconnected   (1UL)

Disconnect

◆ SPIS_PSEL_SCK_CONNECT_Msk

#define SPIS_PSEL_SCK_CONNECT_Msk   (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos)

Bit mask of CONNECT field.

◆ SPIS_PSEL_SCK_CONNECT_Pos

#define SPIS_PSEL_SCK_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ SPIS_PSEL_SCK_PIN_Msk

#define SPIS_PSEL_SCK_PIN_Msk   (0x1FUL << SPIS_PSEL_SCK_PIN_Pos)

Bit mask of PIN field.

◆ SPIS_PSEL_SCK_PIN_Pos

#define SPIS_PSEL_SCK_PIN_Pos   (0UL)

Position of PIN field.

◆ SPIS_RXD_AMOUNT_AMOUNT_Msk

#define SPIS_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ SPIS_RXD_AMOUNT_AMOUNT_Pos

#define SPIS_RXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ SPIS_RXD_MAXCNT_MAXCNT_Msk

#define SPIS_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ SPIS_RXD_MAXCNT_MAXCNT_Pos

#define SPIS_RXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ SPIS_RXD_PTR_PTR_Msk

#define SPIS_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ SPIS_RXD_PTR_PTR_Pos

#define SPIS_RXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ SPIS_SEMSTAT_SEMSTAT_CPU

#define SPIS_SEMSTAT_SEMSTAT_CPU   (1UL)

Semaphore is assigned to CPU

◆ SPIS_SEMSTAT_SEMSTAT_CPUPending

#define SPIS_SEMSTAT_SEMSTAT_CPUPending   (3UL)

Semaphore is assigned to SPI but a handover to the CPU is pending

◆ SPIS_SEMSTAT_SEMSTAT_Free

#define SPIS_SEMSTAT_SEMSTAT_Free   (0UL)

Semaphore is free

◆ SPIS_SEMSTAT_SEMSTAT_Msk

#define SPIS_SEMSTAT_SEMSTAT_Msk   (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos)

Bit mask of SEMSTAT field.

◆ SPIS_SEMSTAT_SEMSTAT_Pos

#define SPIS_SEMSTAT_SEMSTAT_Pos   (0UL)

Position of SEMSTAT field.

◆ SPIS_SEMSTAT_SEMSTAT_SPIS

#define SPIS_SEMSTAT_SEMSTAT_SPIS   (2UL)

Semaphore is assigned to SPI slave

◆ SPIS_SHORTS_END_ACQUIRE_Disabled

#define SPIS_SHORTS_END_ACQUIRE_Disabled   (0UL)

Disable shortcut

◆ SPIS_SHORTS_END_ACQUIRE_Enabled

#define SPIS_SHORTS_END_ACQUIRE_Enabled   (1UL)

Enable shortcut

◆ SPIS_SHORTS_END_ACQUIRE_Msk

#define SPIS_SHORTS_END_ACQUIRE_Msk   (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos)

Bit mask of END_ACQUIRE field.

◆ SPIS_SHORTS_END_ACQUIRE_Pos

#define SPIS_SHORTS_END_ACQUIRE_Pos   (2UL)

Position of END_ACQUIRE field.

◆ SPIS_STATUS_OVERFLOW_Clear

#define SPIS_STATUS_OVERFLOW_Clear   (1UL)

Write: clear error on writing '1'

◆ SPIS_STATUS_OVERFLOW_Msk

#define SPIS_STATUS_OVERFLOW_Msk   (0x1UL << SPIS_STATUS_OVERFLOW_Pos)

Bit mask of OVERFLOW field.

◆ SPIS_STATUS_OVERFLOW_NotPresent

#define SPIS_STATUS_OVERFLOW_NotPresent   (0UL)

Read: error not present

◆ SPIS_STATUS_OVERFLOW_Pos

#define SPIS_STATUS_OVERFLOW_Pos   (1UL)

Position of OVERFLOW field.

◆ SPIS_STATUS_OVERFLOW_Present

#define SPIS_STATUS_OVERFLOW_Present   (1UL)

Read: error present

◆ SPIS_STATUS_OVERREAD_Clear

#define SPIS_STATUS_OVERREAD_Clear   (1UL)

Write: clear error on writing '1'

◆ SPIS_STATUS_OVERREAD_Msk

#define SPIS_STATUS_OVERREAD_Msk   (0x1UL << SPIS_STATUS_OVERREAD_Pos)

Bit mask of OVERREAD field.

◆ SPIS_STATUS_OVERREAD_NotPresent

#define SPIS_STATUS_OVERREAD_NotPresent   (0UL)

Read: error not present

◆ SPIS_STATUS_OVERREAD_Pos

#define SPIS_STATUS_OVERREAD_Pos   (0UL)

Position of OVERREAD field.

◆ SPIS_STATUS_OVERREAD_Present

#define SPIS_STATUS_OVERREAD_Present   (1UL)

Read: error present

◆ SPIS_TXD_AMOUNT_AMOUNT_Msk

#define SPIS_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ SPIS_TXD_AMOUNT_AMOUNT_Pos

#define SPIS_TXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ SPIS_TXD_MAXCNT_MAXCNT_Msk

#define SPIS_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ SPIS_TXD_MAXCNT_MAXCNT_Pos

#define SPIS_TXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ SPIS_TXD_PTR_PTR_Msk

#define SPIS_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ SPIS_TXD_PTR_PTR_Pos

#define SPIS_TXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ TEMP_A0_A0_Msk

#define TEMP_A0_A0_Msk   (0xFFFUL << TEMP_A0_A0_Pos)

Bit mask of A0 field.

◆ TEMP_A0_A0_Pos

#define TEMP_A0_A0_Pos   (0UL)

Position of A0 field.

◆ TEMP_A1_A1_Msk

#define TEMP_A1_A1_Msk   (0xFFFUL << TEMP_A1_A1_Pos)

Bit mask of A1 field.

◆ TEMP_A1_A1_Pos

#define TEMP_A1_A1_Pos   (0UL)

Position of A1 field.

◆ TEMP_A2_A2_Msk

#define TEMP_A2_A2_Msk   (0xFFFUL << TEMP_A2_A2_Pos)

Bit mask of A2 field.

◆ TEMP_A2_A2_Pos

#define TEMP_A2_A2_Pos   (0UL)

Position of A2 field.

◆ TEMP_A3_A3_Msk

#define TEMP_A3_A3_Msk   (0xFFFUL << TEMP_A3_A3_Pos)

Bit mask of A3 field.

◆ TEMP_A3_A3_Pos

#define TEMP_A3_A3_Pos   (0UL)

Position of A3 field.

◆ TEMP_A4_A4_Msk

#define TEMP_A4_A4_Msk   (0xFFFUL << TEMP_A4_A4_Pos)

Bit mask of A4 field.

◆ TEMP_A4_A4_Pos

#define TEMP_A4_A4_Pos   (0UL)

Position of A4 field.

◆ TEMP_A5_A5_Msk

#define TEMP_A5_A5_Msk   (0xFFFUL << TEMP_A5_A5_Pos)

Bit mask of A5 field.

◆ TEMP_A5_A5_Pos

#define TEMP_A5_A5_Pos   (0UL)

Position of A5 field.

◆ TEMP_B0_B0_Msk

#define TEMP_B0_B0_Msk   (0x3FFFUL << TEMP_B0_B0_Pos)

Bit mask of B0 field.

◆ TEMP_B0_B0_Pos

#define TEMP_B0_B0_Pos   (0UL)

Position of B0 field.

◆ TEMP_B1_B1_Msk

#define TEMP_B1_B1_Msk   (0x3FFFUL << TEMP_B1_B1_Pos)

Bit mask of B1 field.

◆ TEMP_B1_B1_Pos

#define TEMP_B1_B1_Pos   (0UL)

Position of B1 field.

◆ TEMP_B2_B2_Msk

#define TEMP_B2_B2_Msk   (0x3FFFUL << TEMP_B2_B2_Pos)

Bit mask of B2 field.

◆ TEMP_B2_B2_Pos

#define TEMP_B2_B2_Pos   (0UL)

Position of B2 field.

◆ TEMP_B3_B3_Msk

#define TEMP_B3_B3_Msk   (0x3FFFUL << TEMP_B3_B3_Pos)

Bit mask of B3 field.

◆ TEMP_B3_B3_Pos

#define TEMP_B3_B3_Pos   (0UL)

Position of B3 field.

◆ TEMP_B4_B4_Msk

#define TEMP_B4_B4_Msk   (0x3FFFUL << TEMP_B4_B4_Pos)

Bit mask of B4 field.

◆ TEMP_B4_B4_Pos

#define TEMP_B4_B4_Pos   (0UL)

Position of B4 field.

◆ TEMP_B5_B5_Msk

#define TEMP_B5_B5_Msk   (0x3FFFUL << TEMP_B5_B5_Pos)

Bit mask of B5 field.

◆ TEMP_B5_B5_Pos

#define TEMP_B5_B5_Pos   (0UL)

Position of B5 field.

◆ TEMP_INTENCLR_DATARDY_Clear

#define TEMP_INTENCLR_DATARDY_Clear   (1UL)

Disable

◆ TEMP_INTENCLR_DATARDY_Disabled

#define TEMP_INTENCLR_DATARDY_Disabled   (0UL)

Read: Disabled

◆ TEMP_INTENCLR_DATARDY_Enabled

#define TEMP_INTENCLR_DATARDY_Enabled   (1UL)

Read: Enabled

◆ TEMP_INTENCLR_DATARDY_Msk

#define TEMP_INTENCLR_DATARDY_Msk   (0x1UL << TEMP_INTENCLR_DATARDY_Pos)

Bit mask of DATARDY field.

◆ TEMP_INTENCLR_DATARDY_Pos

#define TEMP_INTENCLR_DATARDY_Pos   (0UL)

Position of DATARDY field.

◆ TEMP_INTENSET_DATARDY_Disabled

#define TEMP_INTENSET_DATARDY_Disabled   (0UL)

Read: Disabled

◆ TEMP_INTENSET_DATARDY_Enabled

#define TEMP_INTENSET_DATARDY_Enabled   (1UL)

Read: Enabled

◆ TEMP_INTENSET_DATARDY_Msk

#define TEMP_INTENSET_DATARDY_Msk   (0x1UL << TEMP_INTENSET_DATARDY_Pos)

Bit mask of DATARDY field.

◆ TEMP_INTENSET_DATARDY_Pos

#define TEMP_INTENSET_DATARDY_Pos   (0UL)

Position of DATARDY field.

◆ TEMP_INTENSET_DATARDY_Set

#define TEMP_INTENSET_DATARDY_Set   (1UL)

Enable

◆ TEMP_T0_T0_Msk

#define TEMP_T0_T0_Msk   (0xFFUL << TEMP_T0_T0_Pos)

Bit mask of T0 field.

◆ TEMP_T0_T0_Pos

#define TEMP_T0_T0_Pos   (0UL)

Position of T0 field.

◆ TEMP_T1_T1_Msk

#define TEMP_T1_T1_Msk   (0xFFUL << TEMP_T1_T1_Pos)

Bit mask of T1 field.

◆ TEMP_T1_T1_Pos

#define TEMP_T1_T1_Pos   (0UL)

Position of T1 field.

◆ TEMP_T2_T2_Msk

#define TEMP_T2_T2_Msk   (0xFFUL << TEMP_T2_T2_Pos)

Bit mask of T2 field.

◆ TEMP_T2_T2_Pos

#define TEMP_T2_T2_Pos   (0UL)

Position of T2 field.

◆ TEMP_T3_T3_Msk

#define TEMP_T3_T3_Msk   (0xFFUL << TEMP_T3_T3_Pos)

Bit mask of T3 field.

◆ TEMP_T3_T3_Pos

#define TEMP_T3_T3_Pos   (0UL)

Position of T3 field.

◆ TEMP_T4_T4_Msk

#define TEMP_T4_T4_Msk   (0xFFUL << TEMP_T4_T4_Pos)

Bit mask of T4 field.

◆ TEMP_T4_T4_Pos

#define TEMP_T4_T4_Pos   (0UL)

Position of T4 field.

◆ TEMP_TEMP_TEMP_Msk

#define TEMP_TEMP_TEMP_Msk   (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos)

Bit mask of TEMP field.

◆ TEMP_TEMP_TEMP_Pos

#define TEMP_TEMP_TEMP_Pos   (0UL)

Position of TEMP field.

◆ TIMER_BITMODE_BITMODE_08Bit

#define TIMER_BITMODE_BITMODE_08Bit   (1UL)

8 bit timer bit width

◆ TIMER_BITMODE_BITMODE_16Bit

#define TIMER_BITMODE_BITMODE_16Bit   (0UL)

16 bit timer bit width

◆ TIMER_BITMODE_BITMODE_24Bit

#define TIMER_BITMODE_BITMODE_24Bit   (2UL)

24 bit timer bit width

◆ TIMER_BITMODE_BITMODE_32Bit

#define TIMER_BITMODE_BITMODE_32Bit   (3UL)

32 bit timer bit width

◆ TIMER_BITMODE_BITMODE_Msk

#define TIMER_BITMODE_BITMODE_Msk   (0x3UL << TIMER_BITMODE_BITMODE_Pos)

Bit mask of BITMODE field.

◆ TIMER_BITMODE_BITMODE_Pos

#define TIMER_BITMODE_BITMODE_Pos   (0UL)

Position of BITMODE field.

◆ TIMER_CC_CC_Msk

#define TIMER_CC_CC_Msk   (0xFFFFFFFFUL << TIMER_CC_CC_Pos)

Bit mask of CC field.

◆ TIMER_CC_CC_Pos

#define TIMER_CC_CC_Pos   (0UL)

Position of CC field.

◆ TIMER_INTENCLR_COMPARE0_Clear

#define TIMER_INTENCLR_COMPARE0_Clear   (1UL)

Disable

◆ TIMER_INTENCLR_COMPARE0_Disabled

#define TIMER_INTENCLR_COMPARE0_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENCLR_COMPARE0_Enabled

#define TIMER_INTENCLR_COMPARE0_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENCLR_COMPARE0_Msk

#define TIMER_INTENCLR_COMPARE0_Msk   (0x1UL << TIMER_INTENCLR_COMPARE0_Pos)

Bit mask of COMPARE0 field.

◆ TIMER_INTENCLR_COMPARE0_Pos

#define TIMER_INTENCLR_COMPARE0_Pos   (16UL)

Position of COMPARE0 field.

◆ TIMER_INTENCLR_COMPARE1_Clear

#define TIMER_INTENCLR_COMPARE1_Clear   (1UL)

Disable

◆ TIMER_INTENCLR_COMPARE1_Disabled

#define TIMER_INTENCLR_COMPARE1_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENCLR_COMPARE1_Enabled

#define TIMER_INTENCLR_COMPARE1_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENCLR_COMPARE1_Msk

#define TIMER_INTENCLR_COMPARE1_Msk   (0x1UL << TIMER_INTENCLR_COMPARE1_Pos)

Bit mask of COMPARE1 field.

◆ TIMER_INTENCLR_COMPARE1_Pos

#define TIMER_INTENCLR_COMPARE1_Pos   (17UL)

Position of COMPARE1 field.

◆ TIMER_INTENCLR_COMPARE2_Clear

#define TIMER_INTENCLR_COMPARE2_Clear   (1UL)

Disable

◆ TIMER_INTENCLR_COMPARE2_Disabled

#define TIMER_INTENCLR_COMPARE2_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENCLR_COMPARE2_Enabled

#define TIMER_INTENCLR_COMPARE2_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENCLR_COMPARE2_Msk

#define TIMER_INTENCLR_COMPARE2_Msk   (0x1UL << TIMER_INTENCLR_COMPARE2_Pos)

Bit mask of COMPARE2 field.

◆ TIMER_INTENCLR_COMPARE2_Pos

#define TIMER_INTENCLR_COMPARE2_Pos   (18UL)

Position of COMPARE2 field.

◆ TIMER_INTENCLR_COMPARE3_Clear

#define TIMER_INTENCLR_COMPARE3_Clear   (1UL)

Disable

◆ TIMER_INTENCLR_COMPARE3_Disabled

#define TIMER_INTENCLR_COMPARE3_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENCLR_COMPARE3_Enabled

#define TIMER_INTENCLR_COMPARE3_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENCLR_COMPARE3_Msk

#define TIMER_INTENCLR_COMPARE3_Msk   (0x1UL << TIMER_INTENCLR_COMPARE3_Pos)

Bit mask of COMPARE3 field.

◆ TIMER_INTENCLR_COMPARE3_Pos

#define TIMER_INTENCLR_COMPARE3_Pos   (19UL)

Position of COMPARE3 field.

◆ TIMER_INTENCLR_COMPARE4_Clear

#define TIMER_INTENCLR_COMPARE4_Clear   (1UL)

Disable

◆ TIMER_INTENCLR_COMPARE4_Disabled

#define TIMER_INTENCLR_COMPARE4_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENCLR_COMPARE4_Enabled

#define TIMER_INTENCLR_COMPARE4_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENCLR_COMPARE4_Msk

#define TIMER_INTENCLR_COMPARE4_Msk   (0x1UL << TIMER_INTENCLR_COMPARE4_Pos)

Bit mask of COMPARE4 field.

◆ TIMER_INTENCLR_COMPARE4_Pos

#define TIMER_INTENCLR_COMPARE4_Pos   (20UL)

Position of COMPARE4 field.

◆ TIMER_INTENCLR_COMPARE5_Clear

#define TIMER_INTENCLR_COMPARE5_Clear   (1UL)

Disable

◆ TIMER_INTENCLR_COMPARE5_Disabled

#define TIMER_INTENCLR_COMPARE5_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENCLR_COMPARE5_Enabled

#define TIMER_INTENCLR_COMPARE5_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENCLR_COMPARE5_Msk

#define TIMER_INTENCLR_COMPARE5_Msk   (0x1UL << TIMER_INTENCLR_COMPARE5_Pos)

Bit mask of COMPARE5 field.

◆ TIMER_INTENCLR_COMPARE5_Pos

#define TIMER_INTENCLR_COMPARE5_Pos   (21UL)

Position of COMPARE5 field.

◆ TIMER_INTENSET_COMPARE0_Disabled

#define TIMER_INTENSET_COMPARE0_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENSET_COMPARE0_Enabled

#define TIMER_INTENSET_COMPARE0_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENSET_COMPARE0_Msk

#define TIMER_INTENSET_COMPARE0_Msk   (0x1UL << TIMER_INTENSET_COMPARE0_Pos)

Bit mask of COMPARE0 field.

◆ TIMER_INTENSET_COMPARE0_Pos

#define TIMER_INTENSET_COMPARE0_Pos   (16UL)

Position of COMPARE0 field.

◆ TIMER_INTENSET_COMPARE0_Set

#define TIMER_INTENSET_COMPARE0_Set   (1UL)

Enable

◆ TIMER_INTENSET_COMPARE1_Disabled

#define TIMER_INTENSET_COMPARE1_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENSET_COMPARE1_Enabled

#define TIMER_INTENSET_COMPARE1_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENSET_COMPARE1_Msk

#define TIMER_INTENSET_COMPARE1_Msk   (0x1UL << TIMER_INTENSET_COMPARE1_Pos)

Bit mask of COMPARE1 field.

◆ TIMER_INTENSET_COMPARE1_Pos

#define TIMER_INTENSET_COMPARE1_Pos   (17UL)

Position of COMPARE1 field.

◆ TIMER_INTENSET_COMPARE1_Set

#define TIMER_INTENSET_COMPARE1_Set   (1UL)

Enable

◆ TIMER_INTENSET_COMPARE2_Disabled

#define TIMER_INTENSET_COMPARE2_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENSET_COMPARE2_Enabled

#define TIMER_INTENSET_COMPARE2_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENSET_COMPARE2_Msk

#define TIMER_INTENSET_COMPARE2_Msk   (0x1UL << TIMER_INTENSET_COMPARE2_Pos)

Bit mask of COMPARE2 field.

◆ TIMER_INTENSET_COMPARE2_Pos

#define TIMER_INTENSET_COMPARE2_Pos   (18UL)

Position of COMPARE2 field.

◆ TIMER_INTENSET_COMPARE2_Set

#define TIMER_INTENSET_COMPARE2_Set   (1UL)

Enable

◆ TIMER_INTENSET_COMPARE3_Disabled

#define TIMER_INTENSET_COMPARE3_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENSET_COMPARE3_Enabled

#define TIMER_INTENSET_COMPARE3_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENSET_COMPARE3_Msk

#define TIMER_INTENSET_COMPARE3_Msk   (0x1UL << TIMER_INTENSET_COMPARE3_Pos)

Bit mask of COMPARE3 field.

◆ TIMER_INTENSET_COMPARE3_Pos

#define TIMER_INTENSET_COMPARE3_Pos   (19UL)

Position of COMPARE3 field.

◆ TIMER_INTENSET_COMPARE3_Set

#define TIMER_INTENSET_COMPARE3_Set   (1UL)

Enable

◆ TIMER_INTENSET_COMPARE4_Disabled

#define TIMER_INTENSET_COMPARE4_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENSET_COMPARE4_Enabled

#define TIMER_INTENSET_COMPARE4_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENSET_COMPARE4_Msk

#define TIMER_INTENSET_COMPARE4_Msk   (0x1UL << TIMER_INTENSET_COMPARE4_Pos)

Bit mask of COMPARE4 field.

◆ TIMER_INTENSET_COMPARE4_Pos

#define TIMER_INTENSET_COMPARE4_Pos   (20UL)

Position of COMPARE4 field.

◆ TIMER_INTENSET_COMPARE4_Set

#define TIMER_INTENSET_COMPARE4_Set   (1UL)

Enable

◆ TIMER_INTENSET_COMPARE5_Disabled

#define TIMER_INTENSET_COMPARE5_Disabled   (0UL)

Read: Disabled

◆ TIMER_INTENSET_COMPARE5_Enabled

#define TIMER_INTENSET_COMPARE5_Enabled   (1UL)

Read: Enabled

◆ TIMER_INTENSET_COMPARE5_Msk

#define TIMER_INTENSET_COMPARE5_Msk   (0x1UL << TIMER_INTENSET_COMPARE5_Pos)

Bit mask of COMPARE5 field.

◆ TIMER_INTENSET_COMPARE5_Pos

#define TIMER_INTENSET_COMPARE5_Pos   (21UL)

Position of COMPARE5 field.

◆ TIMER_INTENSET_COMPARE5_Set

#define TIMER_INTENSET_COMPARE5_Set   (1UL)

Enable

◆ TIMER_MODE_MODE_Counter

#define TIMER_MODE_MODE_Counter   (1UL)

Deprecated enumerator - Select Counter mode

◆ TIMER_MODE_MODE_LowPowerCounter

#define TIMER_MODE_MODE_LowPowerCounter   (2UL)

Select Low Power Counter mode

◆ TIMER_MODE_MODE_Msk

#define TIMER_MODE_MODE_Msk   (0x3UL << TIMER_MODE_MODE_Pos)

Bit mask of MODE field.

◆ TIMER_MODE_MODE_Pos

#define TIMER_MODE_MODE_Pos   (0UL)

Position of MODE field.

◆ TIMER_MODE_MODE_Timer

#define TIMER_MODE_MODE_Timer   (0UL)

Select Timer mode

◆ TIMER_PRESCALER_PRESCALER_Msk

#define TIMER_PRESCALER_PRESCALER_Msk   (0xFUL << TIMER_PRESCALER_PRESCALER_Pos)

Bit mask of PRESCALER field.

◆ TIMER_PRESCALER_PRESCALER_Pos

#define TIMER_PRESCALER_PRESCALER_Pos   (0UL)

Position of PRESCALER field.

◆ TIMER_SHORTS_COMPARE0_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE0_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE0_CLEAR_Msk

#define TIMER_SHORTS_COMPARE0_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos)

Bit mask of COMPARE0_CLEAR field.

◆ TIMER_SHORTS_COMPARE0_CLEAR_Pos

#define TIMER_SHORTS_COMPARE0_CLEAR_Pos   (0UL)

Position of COMPARE0_CLEAR field.

◆ TIMER_SHORTS_COMPARE0_STOP_Disabled

#define TIMER_SHORTS_COMPARE0_STOP_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE0_STOP_Enabled

#define TIMER_SHORTS_COMPARE0_STOP_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE0_STOP_Msk

#define TIMER_SHORTS_COMPARE0_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos)

Bit mask of COMPARE0_STOP field.

◆ TIMER_SHORTS_COMPARE0_STOP_Pos

#define TIMER_SHORTS_COMPARE0_STOP_Pos   (8UL)

Position of COMPARE0_STOP field.

◆ TIMER_SHORTS_COMPARE1_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE1_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE1_CLEAR_Msk

#define TIMER_SHORTS_COMPARE1_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos)

Bit mask of COMPARE1_CLEAR field.

◆ TIMER_SHORTS_COMPARE1_CLEAR_Pos

#define TIMER_SHORTS_COMPARE1_CLEAR_Pos   (1UL)

Position of COMPARE1_CLEAR field.

◆ TIMER_SHORTS_COMPARE1_STOP_Disabled

#define TIMER_SHORTS_COMPARE1_STOP_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE1_STOP_Enabled

#define TIMER_SHORTS_COMPARE1_STOP_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE1_STOP_Msk

#define TIMER_SHORTS_COMPARE1_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos)

Bit mask of COMPARE1_STOP field.

◆ TIMER_SHORTS_COMPARE1_STOP_Pos

#define TIMER_SHORTS_COMPARE1_STOP_Pos   (9UL)

Position of COMPARE1_STOP field.

◆ TIMER_SHORTS_COMPARE2_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE2_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE2_CLEAR_Msk

#define TIMER_SHORTS_COMPARE2_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos)

Bit mask of COMPARE2_CLEAR field.

◆ TIMER_SHORTS_COMPARE2_CLEAR_Pos

#define TIMER_SHORTS_COMPARE2_CLEAR_Pos   (2UL)

Position of COMPARE2_CLEAR field.

◆ TIMER_SHORTS_COMPARE2_STOP_Disabled

#define TIMER_SHORTS_COMPARE2_STOP_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE2_STOP_Enabled

#define TIMER_SHORTS_COMPARE2_STOP_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE2_STOP_Msk

#define TIMER_SHORTS_COMPARE2_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos)

Bit mask of COMPARE2_STOP field.

◆ TIMER_SHORTS_COMPARE2_STOP_Pos

#define TIMER_SHORTS_COMPARE2_STOP_Pos   (10UL)

Position of COMPARE2_STOP field.

◆ TIMER_SHORTS_COMPARE3_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE3_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE3_CLEAR_Msk

#define TIMER_SHORTS_COMPARE3_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos)

Bit mask of COMPARE3_CLEAR field.

◆ TIMER_SHORTS_COMPARE3_CLEAR_Pos

#define TIMER_SHORTS_COMPARE3_CLEAR_Pos   (3UL)

Position of COMPARE3_CLEAR field.

◆ TIMER_SHORTS_COMPARE3_STOP_Disabled

#define TIMER_SHORTS_COMPARE3_STOP_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE3_STOP_Enabled

#define TIMER_SHORTS_COMPARE3_STOP_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE3_STOP_Msk

#define TIMER_SHORTS_COMPARE3_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos)

Bit mask of COMPARE3_STOP field.

◆ TIMER_SHORTS_COMPARE3_STOP_Pos

#define TIMER_SHORTS_COMPARE3_STOP_Pos   (11UL)

Position of COMPARE3_STOP field.

◆ TIMER_SHORTS_COMPARE4_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE4_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE4_CLEAR_Msk

#define TIMER_SHORTS_COMPARE4_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos)

Bit mask of COMPARE4_CLEAR field.

◆ TIMER_SHORTS_COMPARE4_CLEAR_Pos

#define TIMER_SHORTS_COMPARE4_CLEAR_Pos   (4UL)

Position of COMPARE4_CLEAR field.

◆ TIMER_SHORTS_COMPARE4_STOP_Disabled

#define TIMER_SHORTS_COMPARE4_STOP_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE4_STOP_Enabled

#define TIMER_SHORTS_COMPARE4_STOP_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE4_STOP_Msk

#define TIMER_SHORTS_COMPARE4_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos)

Bit mask of COMPARE4_STOP field.

◆ TIMER_SHORTS_COMPARE4_STOP_Pos

#define TIMER_SHORTS_COMPARE4_STOP_Pos   (12UL)

Position of COMPARE4_STOP field.

◆ TIMER_SHORTS_COMPARE5_CLEAR_Disabled

#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE5_CLEAR_Enabled

#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE5_CLEAR_Msk

#define TIMER_SHORTS_COMPARE5_CLEAR_Msk   (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos)

Bit mask of COMPARE5_CLEAR field.

◆ TIMER_SHORTS_COMPARE5_CLEAR_Pos

#define TIMER_SHORTS_COMPARE5_CLEAR_Pos   (5UL)

Position of COMPARE5_CLEAR field.

◆ TIMER_SHORTS_COMPARE5_STOP_Disabled

#define TIMER_SHORTS_COMPARE5_STOP_Disabled   (0UL)

Disable shortcut

◆ TIMER_SHORTS_COMPARE5_STOP_Enabled

#define TIMER_SHORTS_COMPARE5_STOP_Enabled   (1UL)

Enable shortcut

◆ TIMER_SHORTS_COMPARE5_STOP_Msk

#define TIMER_SHORTS_COMPARE5_STOP_Msk   (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos)

Bit mask of COMPARE5_STOP field.

◆ TIMER_SHORTS_COMPARE5_STOP_Pos

#define TIMER_SHORTS_COMPARE5_STOP_Pos   (13UL)

Position of COMPARE5_STOP field.

◆ TWI_ADDRESS_ADDRESS_Msk

#define TWI_ADDRESS_ADDRESS_Msk   (0x7FUL << TWI_ADDRESS_ADDRESS_Pos)

Bit mask of ADDRESS field.

◆ TWI_ADDRESS_ADDRESS_Pos

#define TWI_ADDRESS_ADDRESS_Pos   (0UL)

Position of ADDRESS field.

◆ TWI_ENABLE_ENABLE_Disabled

#define TWI_ENABLE_ENABLE_Disabled   (0UL)

Disable TWI

◆ TWI_ENABLE_ENABLE_Enabled

#define TWI_ENABLE_ENABLE_Enabled   (5UL)

Enable TWI

◆ TWI_ENABLE_ENABLE_Msk

#define TWI_ENABLE_ENABLE_Msk   (0xFUL << TWI_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ TWI_ENABLE_ENABLE_Pos

#define TWI_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ TWI_ERRORSRC_ANACK_Clear

#define TWI_ERRORSRC_ANACK_Clear   (1UL)

Write: clear error on writing '1'

◆ TWI_ERRORSRC_ANACK_Msk

#define TWI_ERRORSRC_ANACK_Msk   (0x1UL << TWI_ERRORSRC_ANACK_Pos)

Bit mask of ANACK field.

◆ TWI_ERRORSRC_ANACK_NotPresent

#define TWI_ERRORSRC_ANACK_NotPresent   (0UL)

Read: error not present

◆ TWI_ERRORSRC_ANACK_Pos

#define TWI_ERRORSRC_ANACK_Pos   (1UL)

Position of ANACK field.

◆ TWI_ERRORSRC_ANACK_Present

#define TWI_ERRORSRC_ANACK_Present   (1UL)

Read: error present

◆ TWI_ERRORSRC_DNACK_Clear

#define TWI_ERRORSRC_DNACK_Clear   (1UL)

Write: clear error on writing '1'

◆ TWI_ERRORSRC_DNACK_Msk

#define TWI_ERRORSRC_DNACK_Msk   (0x1UL << TWI_ERRORSRC_DNACK_Pos)

Bit mask of DNACK field.

◆ TWI_ERRORSRC_DNACK_NotPresent

#define TWI_ERRORSRC_DNACK_NotPresent   (0UL)

Read: error not present

◆ TWI_ERRORSRC_DNACK_Pos

#define TWI_ERRORSRC_DNACK_Pos   (2UL)

Position of DNACK field.

◆ TWI_ERRORSRC_DNACK_Present

#define TWI_ERRORSRC_DNACK_Present   (1UL)

Read: error present

◆ TWI_ERRORSRC_OVERRUN_Clear

#define TWI_ERRORSRC_OVERRUN_Clear   (1UL)

Write: clear error on writing '1'

◆ TWI_ERRORSRC_OVERRUN_Msk

#define TWI_ERRORSRC_OVERRUN_Msk   (0x1UL << TWI_ERRORSRC_OVERRUN_Pos)

Bit mask of OVERRUN field.

◆ TWI_ERRORSRC_OVERRUN_NotPresent

#define TWI_ERRORSRC_OVERRUN_NotPresent   (0UL)

Read: no overrun occured

◆ TWI_ERRORSRC_OVERRUN_Pos

#define TWI_ERRORSRC_OVERRUN_Pos   (0UL)

Position of OVERRUN field.

◆ TWI_ERRORSRC_OVERRUN_Present

#define TWI_ERRORSRC_OVERRUN_Present   (1UL)

Read: overrun occured

◆ TWI_FREQUENCY_FREQUENCY_K100

#define TWI_FREQUENCY_FREQUENCY_K100   (0x01980000UL)

100 kbps

◆ TWI_FREQUENCY_FREQUENCY_K250

#define TWI_FREQUENCY_FREQUENCY_K250   (0x04000000UL)

250 kbps

◆ TWI_FREQUENCY_FREQUENCY_K400

#define TWI_FREQUENCY_FREQUENCY_K400   (0x06680000UL)

400 kbps (actual rate 410.256 kbps)

◆ TWI_FREQUENCY_FREQUENCY_Msk

#define TWI_FREQUENCY_FREQUENCY_Msk   (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

◆ TWI_FREQUENCY_FREQUENCY_Pos

#define TWI_FREQUENCY_FREQUENCY_Pos   (0UL)

Position of FREQUENCY field.

◆ TWI_INTENCLR_BB_Clear

#define TWI_INTENCLR_BB_Clear   (1UL)

Disable

◆ TWI_INTENCLR_BB_Disabled

#define TWI_INTENCLR_BB_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENCLR_BB_Enabled

#define TWI_INTENCLR_BB_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENCLR_BB_Msk

#define TWI_INTENCLR_BB_Msk   (0x1UL << TWI_INTENCLR_BB_Pos)

Bit mask of BB field.

◆ TWI_INTENCLR_BB_Pos

#define TWI_INTENCLR_BB_Pos   (14UL)

Position of BB field.

◆ TWI_INTENCLR_ERROR_Clear

#define TWI_INTENCLR_ERROR_Clear   (1UL)

Disable

◆ TWI_INTENCLR_ERROR_Disabled

#define TWI_INTENCLR_ERROR_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENCLR_ERROR_Enabled

#define TWI_INTENCLR_ERROR_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENCLR_ERROR_Msk

#define TWI_INTENCLR_ERROR_Msk   (0x1UL << TWI_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

◆ TWI_INTENCLR_ERROR_Pos

#define TWI_INTENCLR_ERROR_Pos   (9UL)

Position of ERROR field.

◆ TWI_INTENCLR_RXDREADY_Clear

#define TWI_INTENCLR_RXDREADY_Clear   (1UL)

Disable

◆ TWI_INTENCLR_RXDREADY_Disabled

#define TWI_INTENCLR_RXDREADY_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENCLR_RXDREADY_Enabled

#define TWI_INTENCLR_RXDREADY_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENCLR_RXDREADY_Msk

#define TWI_INTENCLR_RXDREADY_Msk   (0x1UL << TWI_INTENCLR_RXDREADY_Pos)

Bit mask of RXDREADY field.

◆ TWI_INTENCLR_RXDREADY_Pos

#define TWI_INTENCLR_RXDREADY_Pos   (2UL)

Position of RXDREADY field.

◆ TWI_INTENCLR_STOPPED_Clear

#define TWI_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ TWI_INTENCLR_STOPPED_Disabled

#define TWI_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENCLR_STOPPED_Enabled

#define TWI_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENCLR_STOPPED_Msk

#define TWI_INTENCLR_STOPPED_Msk   (0x1UL << TWI_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ TWI_INTENCLR_STOPPED_Pos

#define TWI_INTENCLR_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ TWI_INTENCLR_SUSPENDED_Clear

#define TWI_INTENCLR_SUSPENDED_Clear   (1UL)

Disable

◆ TWI_INTENCLR_SUSPENDED_Disabled

#define TWI_INTENCLR_SUSPENDED_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENCLR_SUSPENDED_Enabled

#define TWI_INTENCLR_SUSPENDED_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENCLR_SUSPENDED_Msk

#define TWI_INTENCLR_SUSPENDED_Msk   (0x1UL << TWI_INTENCLR_SUSPENDED_Pos)

Bit mask of SUSPENDED field.

◆ TWI_INTENCLR_SUSPENDED_Pos

#define TWI_INTENCLR_SUSPENDED_Pos   (18UL)

Position of SUSPENDED field.

◆ TWI_INTENCLR_TXDSENT_Clear

#define TWI_INTENCLR_TXDSENT_Clear   (1UL)

Disable

◆ TWI_INTENCLR_TXDSENT_Disabled

#define TWI_INTENCLR_TXDSENT_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENCLR_TXDSENT_Enabled

#define TWI_INTENCLR_TXDSENT_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENCLR_TXDSENT_Msk

#define TWI_INTENCLR_TXDSENT_Msk   (0x1UL << TWI_INTENCLR_TXDSENT_Pos)

Bit mask of TXDSENT field.

◆ TWI_INTENCLR_TXDSENT_Pos

#define TWI_INTENCLR_TXDSENT_Pos   (7UL)

Position of TXDSENT field.

◆ TWI_INTENSET_BB_Disabled

#define TWI_INTENSET_BB_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENSET_BB_Enabled

#define TWI_INTENSET_BB_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENSET_BB_Msk

#define TWI_INTENSET_BB_Msk   (0x1UL << TWI_INTENSET_BB_Pos)

Bit mask of BB field.

◆ TWI_INTENSET_BB_Pos

#define TWI_INTENSET_BB_Pos   (14UL)

Position of BB field.

◆ TWI_INTENSET_BB_Set

#define TWI_INTENSET_BB_Set   (1UL)

Enable

◆ TWI_INTENSET_ERROR_Disabled

#define TWI_INTENSET_ERROR_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENSET_ERROR_Enabled

#define TWI_INTENSET_ERROR_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENSET_ERROR_Msk

#define TWI_INTENSET_ERROR_Msk   (0x1UL << TWI_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

◆ TWI_INTENSET_ERROR_Pos

#define TWI_INTENSET_ERROR_Pos   (9UL)

Position of ERROR field.

◆ TWI_INTENSET_ERROR_Set

#define TWI_INTENSET_ERROR_Set   (1UL)

Enable

◆ TWI_INTENSET_RXDREADY_Disabled

#define TWI_INTENSET_RXDREADY_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENSET_RXDREADY_Enabled

#define TWI_INTENSET_RXDREADY_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENSET_RXDREADY_Msk

#define TWI_INTENSET_RXDREADY_Msk   (0x1UL << TWI_INTENSET_RXDREADY_Pos)

Bit mask of RXDREADY field.

◆ TWI_INTENSET_RXDREADY_Pos

#define TWI_INTENSET_RXDREADY_Pos   (2UL)

Position of RXDREADY field.

◆ TWI_INTENSET_RXDREADY_Set

#define TWI_INTENSET_RXDREADY_Set   (1UL)

Enable

◆ TWI_INTENSET_STOPPED_Disabled

#define TWI_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENSET_STOPPED_Enabled

#define TWI_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENSET_STOPPED_Msk

#define TWI_INTENSET_STOPPED_Msk   (0x1UL << TWI_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ TWI_INTENSET_STOPPED_Pos

#define TWI_INTENSET_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ TWI_INTENSET_STOPPED_Set

#define TWI_INTENSET_STOPPED_Set   (1UL)

Enable

◆ TWI_INTENSET_SUSPENDED_Disabled

#define TWI_INTENSET_SUSPENDED_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENSET_SUSPENDED_Enabled

#define TWI_INTENSET_SUSPENDED_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENSET_SUSPENDED_Msk

#define TWI_INTENSET_SUSPENDED_Msk   (0x1UL << TWI_INTENSET_SUSPENDED_Pos)

Bit mask of SUSPENDED field.

◆ TWI_INTENSET_SUSPENDED_Pos

#define TWI_INTENSET_SUSPENDED_Pos   (18UL)

Position of SUSPENDED field.

◆ TWI_INTENSET_SUSPENDED_Set

#define TWI_INTENSET_SUSPENDED_Set   (1UL)

Enable

◆ TWI_INTENSET_TXDSENT_Disabled

#define TWI_INTENSET_TXDSENT_Disabled   (0UL)

Read: Disabled

◆ TWI_INTENSET_TXDSENT_Enabled

#define TWI_INTENSET_TXDSENT_Enabled   (1UL)

Read: Enabled

◆ TWI_INTENSET_TXDSENT_Msk

#define TWI_INTENSET_TXDSENT_Msk   (0x1UL << TWI_INTENSET_TXDSENT_Pos)

Bit mask of TXDSENT field.

◆ TWI_INTENSET_TXDSENT_Pos

#define TWI_INTENSET_TXDSENT_Pos   (7UL)

Position of TXDSENT field.

◆ TWI_INTENSET_TXDSENT_Set

#define TWI_INTENSET_TXDSENT_Set   (1UL)

Enable

◆ TWI_PSELSCL_PSELSCL_Disconnected

#define TWI_PSELSCL_PSELSCL_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ TWI_PSELSCL_PSELSCL_Msk

#define TWI_PSELSCL_PSELSCL_Msk   (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos)

Bit mask of PSELSCL field.

◆ TWI_PSELSCL_PSELSCL_Pos

#define TWI_PSELSCL_PSELSCL_Pos   (0UL)

Position of PSELSCL field.

◆ TWI_PSELSDA_PSELSDA_Disconnected

#define TWI_PSELSDA_PSELSDA_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ TWI_PSELSDA_PSELSDA_Msk

#define TWI_PSELSDA_PSELSDA_Msk   (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos)

Bit mask of PSELSDA field.

◆ TWI_PSELSDA_PSELSDA_Pos

#define TWI_PSELSDA_PSELSDA_Pos   (0UL)

Position of PSELSDA field.

◆ TWI_RXD_RXD_Msk

#define TWI_RXD_RXD_Msk   (0xFFUL << TWI_RXD_RXD_Pos)

Bit mask of RXD field.

◆ TWI_RXD_RXD_Pos

#define TWI_RXD_RXD_Pos   (0UL)

Position of RXD field.

◆ TWI_SHORTS_BB_STOP_Disabled

#define TWI_SHORTS_BB_STOP_Disabled   (0UL)

Disable shortcut

◆ TWI_SHORTS_BB_STOP_Enabled

#define TWI_SHORTS_BB_STOP_Enabled   (1UL)

Enable shortcut

◆ TWI_SHORTS_BB_STOP_Msk

#define TWI_SHORTS_BB_STOP_Msk   (0x1UL << TWI_SHORTS_BB_STOP_Pos)

Bit mask of BB_STOP field.

◆ TWI_SHORTS_BB_STOP_Pos

#define TWI_SHORTS_BB_STOP_Pos   (1UL)

Position of BB_STOP field.

◆ TWI_SHORTS_BB_SUSPEND_Disabled

#define TWI_SHORTS_BB_SUSPEND_Disabled   (0UL)

Disable shortcut

◆ TWI_SHORTS_BB_SUSPEND_Enabled

#define TWI_SHORTS_BB_SUSPEND_Enabled   (1UL)

Enable shortcut

◆ TWI_SHORTS_BB_SUSPEND_Msk

#define TWI_SHORTS_BB_SUSPEND_Msk   (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos)

Bit mask of BB_SUSPEND field.

◆ TWI_SHORTS_BB_SUSPEND_Pos

#define TWI_SHORTS_BB_SUSPEND_Pos   (0UL)

Position of BB_SUSPEND field.

◆ TWI_TXD_TXD_Msk

#define TWI_TXD_TXD_Msk   (0xFFUL << TWI_TXD_TXD_Pos)

Bit mask of TXD field.

◆ TWI_TXD_TXD_Pos

#define TWI_TXD_TXD_Pos   (0UL)

Position of TXD field.

◆ TWIM_ADDRESS_ADDRESS_Msk

#define TWIM_ADDRESS_ADDRESS_Msk   (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos)

Bit mask of ADDRESS field.

◆ TWIM_ADDRESS_ADDRESS_Pos

#define TWIM_ADDRESS_ADDRESS_Pos   (0UL)

Position of ADDRESS field.

◆ TWIM_ENABLE_ENABLE_Disabled

#define TWIM_ENABLE_ENABLE_Disabled   (0UL)

Disable TWIM

◆ TWIM_ENABLE_ENABLE_Enabled

#define TWIM_ENABLE_ENABLE_Enabled   (6UL)

Enable TWIM

◆ TWIM_ENABLE_ENABLE_Msk

#define TWIM_ENABLE_ENABLE_Msk   (0xFUL << TWIM_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ TWIM_ENABLE_ENABLE_Pos

#define TWIM_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ TWIM_ERRORSRC_ANACK_Msk

#define TWIM_ERRORSRC_ANACK_Msk   (0x1UL << TWIM_ERRORSRC_ANACK_Pos)

Bit mask of ANACK field.

◆ TWIM_ERRORSRC_ANACK_NotReceived

#define TWIM_ERRORSRC_ANACK_NotReceived   (0UL)

Error did not occur

◆ TWIM_ERRORSRC_ANACK_Pos

#define TWIM_ERRORSRC_ANACK_Pos   (1UL)

Position of ANACK field.

◆ TWIM_ERRORSRC_ANACK_Received

#define TWIM_ERRORSRC_ANACK_Received   (1UL)

Error occurred

◆ TWIM_ERRORSRC_DNACK_Msk

#define TWIM_ERRORSRC_DNACK_Msk   (0x1UL << TWIM_ERRORSRC_DNACK_Pos)

Bit mask of DNACK field.

◆ TWIM_ERRORSRC_DNACK_NotReceived

#define TWIM_ERRORSRC_DNACK_NotReceived   (0UL)

Error did not occur

◆ TWIM_ERRORSRC_DNACK_Pos

#define TWIM_ERRORSRC_DNACK_Pos   (2UL)

Position of DNACK field.

◆ TWIM_ERRORSRC_DNACK_Received

#define TWIM_ERRORSRC_DNACK_Received   (1UL)

Error occurred

◆ TWIM_ERRORSRC_OVERRUN_Msk

#define TWIM_ERRORSRC_OVERRUN_Msk   (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos)

Bit mask of OVERRUN field.

◆ TWIM_ERRORSRC_OVERRUN_NotReceived

#define TWIM_ERRORSRC_OVERRUN_NotReceived   (0UL)

Error did not occur

◆ TWIM_ERRORSRC_OVERRUN_Pos

#define TWIM_ERRORSRC_OVERRUN_Pos   (0UL)

Position of OVERRUN field.

◆ TWIM_ERRORSRC_OVERRUN_Received

#define TWIM_ERRORSRC_OVERRUN_Received   (1UL)

Error occurred

◆ TWIM_FREQUENCY_FREQUENCY_K100

#define TWIM_FREQUENCY_FREQUENCY_K100   (0x01980000UL)

100 kbps

◆ TWIM_FREQUENCY_FREQUENCY_K250

#define TWIM_FREQUENCY_FREQUENCY_K250   (0x04000000UL)

250 kbps

◆ TWIM_FREQUENCY_FREQUENCY_K400

#define TWIM_FREQUENCY_FREQUENCY_K400   (0x06400000UL)

400 kbps

◆ TWIM_FREQUENCY_FREQUENCY_Msk

#define TWIM_FREQUENCY_FREQUENCY_Msk   (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos)

Bit mask of FREQUENCY field.

◆ TWIM_FREQUENCY_FREQUENCY_Pos

#define TWIM_FREQUENCY_FREQUENCY_Pos   (0UL)

Position of FREQUENCY field.

◆ TWIM_INTEN_ERROR_Disabled

#define TWIM_INTEN_ERROR_Disabled   (0UL)

Disable

◆ TWIM_INTEN_ERROR_Enabled

#define TWIM_INTEN_ERROR_Enabled   (1UL)

Enable

◆ TWIM_INTEN_ERROR_Msk

#define TWIM_INTEN_ERROR_Msk   (0x1UL << TWIM_INTEN_ERROR_Pos)

Bit mask of ERROR field.

◆ TWIM_INTEN_ERROR_Pos

#define TWIM_INTEN_ERROR_Pos   (9UL)

Position of ERROR field.

◆ TWIM_INTEN_LASTRX_Disabled

#define TWIM_INTEN_LASTRX_Disabled   (0UL)

Disable

◆ TWIM_INTEN_LASTRX_Enabled

#define TWIM_INTEN_LASTRX_Enabled   (1UL)

Enable

◆ TWIM_INTEN_LASTRX_Msk

#define TWIM_INTEN_LASTRX_Msk   (0x1UL << TWIM_INTEN_LASTRX_Pos)

Bit mask of LASTRX field.

◆ TWIM_INTEN_LASTRX_Pos

#define TWIM_INTEN_LASTRX_Pos   (23UL)

Position of LASTRX field.

◆ TWIM_INTEN_LASTTX_Disabled

#define TWIM_INTEN_LASTTX_Disabled   (0UL)

Disable

◆ TWIM_INTEN_LASTTX_Enabled

#define TWIM_INTEN_LASTTX_Enabled   (1UL)

Enable

◆ TWIM_INTEN_LASTTX_Msk

#define TWIM_INTEN_LASTTX_Msk   (0x1UL << TWIM_INTEN_LASTTX_Pos)

Bit mask of LASTTX field.

◆ TWIM_INTEN_LASTTX_Pos

#define TWIM_INTEN_LASTTX_Pos   (24UL)

Position of LASTTX field.

◆ TWIM_INTEN_RXSTARTED_Disabled

#define TWIM_INTEN_RXSTARTED_Disabled   (0UL)

Disable

◆ TWIM_INTEN_RXSTARTED_Enabled

#define TWIM_INTEN_RXSTARTED_Enabled   (1UL)

Enable

◆ TWIM_INTEN_RXSTARTED_Msk

#define TWIM_INTEN_RXSTARTED_Msk   (0x1UL << TWIM_INTEN_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ TWIM_INTEN_RXSTARTED_Pos

#define TWIM_INTEN_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ TWIM_INTEN_STOPPED_Disabled

#define TWIM_INTEN_STOPPED_Disabled   (0UL)

Disable

◆ TWIM_INTEN_STOPPED_Enabled

#define TWIM_INTEN_STOPPED_Enabled   (1UL)

Enable

◆ TWIM_INTEN_STOPPED_Msk

#define TWIM_INTEN_STOPPED_Msk   (0x1UL << TWIM_INTEN_STOPPED_Pos)

Bit mask of STOPPED field.

◆ TWIM_INTEN_STOPPED_Pos

#define TWIM_INTEN_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ TWIM_INTEN_SUSPENDED_Disabled

#define TWIM_INTEN_SUSPENDED_Disabled   (0UL)

Disable

◆ TWIM_INTEN_SUSPENDED_Enabled

#define TWIM_INTEN_SUSPENDED_Enabled   (1UL)

Enable

◆ TWIM_INTEN_SUSPENDED_Msk

#define TWIM_INTEN_SUSPENDED_Msk   (0x1UL << TWIM_INTEN_SUSPENDED_Pos)

Bit mask of SUSPENDED field.

◆ TWIM_INTEN_SUSPENDED_Pos

#define TWIM_INTEN_SUSPENDED_Pos   (18UL)

Position of SUSPENDED field.

◆ TWIM_INTEN_TXSTARTED_Disabled

#define TWIM_INTEN_TXSTARTED_Disabled   (0UL)

Disable

◆ TWIM_INTEN_TXSTARTED_Enabled

#define TWIM_INTEN_TXSTARTED_Enabled   (1UL)

Enable

◆ TWIM_INTEN_TXSTARTED_Msk

#define TWIM_INTEN_TXSTARTED_Msk   (0x1UL << TWIM_INTEN_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ TWIM_INTEN_TXSTARTED_Pos

#define TWIM_INTEN_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ TWIM_INTENCLR_ERROR_Clear

#define TWIM_INTENCLR_ERROR_Clear   (1UL)

Disable

◆ TWIM_INTENCLR_ERROR_Disabled

#define TWIM_INTENCLR_ERROR_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENCLR_ERROR_Enabled

#define TWIM_INTENCLR_ERROR_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENCLR_ERROR_Msk

#define TWIM_INTENCLR_ERROR_Msk   (0x1UL << TWIM_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

◆ TWIM_INTENCLR_ERROR_Pos

#define TWIM_INTENCLR_ERROR_Pos   (9UL)

Position of ERROR field.

◆ TWIM_INTENCLR_LASTRX_Clear

#define TWIM_INTENCLR_LASTRX_Clear   (1UL)

Disable

◆ TWIM_INTENCLR_LASTRX_Disabled

#define TWIM_INTENCLR_LASTRX_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENCLR_LASTRX_Enabled

#define TWIM_INTENCLR_LASTRX_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENCLR_LASTRX_Msk

#define TWIM_INTENCLR_LASTRX_Msk   (0x1UL << TWIM_INTENCLR_LASTRX_Pos)

Bit mask of LASTRX field.

◆ TWIM_INTENCLR_LASTRX_Pos

#define TWIM_INTENCLR_LASTRX_Pos   (23UL)

Position of LASTRX field.

◆ TWIM_INTENCLR_LASTTX_Clear

#define TWIM_INTENCLR_LASTTX_Clear   (1UL)

Disable

◆ TWIM_INTENCLR_LASTTX_Disabled

#define TWIM_INTENCLR_LASTTX_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENCLR_LASTTX_Enabled

#define TWIM_INTENCLR_LASTTX_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENCLR_LASTTX_Msk

#define TWIM_INTENCLR_LASTTX_Msk   (0x1UL << TWIM_INTENCLR_LASTTX_Pos)

Bit mask of LASTTX field.

◆ TWIM_INTENCLR_LASTTX_Pos

#define TWIM_INTENCLR_LASTTX_Pos   (24UL)

Position of LASTTX field.

◆ TWIM_INTENCLR_RXSTARTED_Clear

#define TWIM_INTENCLR_RXSTARTED_Clear   (1UL)

Disable

◆ TWIM_INTENCLR_RXSTARTED_Disabled

#define TWIM_INTENCLR_RXSTARTED_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENCLR_RXSTARTED_Enabled

#define TWIM_INTENCLR_RXSTARTED_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENCLR_RXSTARTED_Msk

#define TWIM_INTENCLR_RXSTARTED_Msk   (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ TWIM_INTENCLR_RXSTARTED_Pos

#define TWIM_INTENCLR_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ TWIM_INTENCLR_STOPPED_Clear

#define TWIM_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ TWIM_INTENCLR_STOPPED_Disabled

#define TWIM_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENCLR_STOPPED_Enabled

#define TWIM_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENCLR_STOPPED_Msk

#define TWIM_INTENCLR_STOPPED_Msk   (0x1UL << TWIM_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ TWIM_INTENCLR_STOPPED_Pos

#define TWIM_INTENCLR_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ TWIM_INTENCLR_SUSPENDED_Clear

#define TWIM_INTENCLR_SUSPENDED_Clear   (1UL)

Disable

◆ TWIM_INTENCLR_SUSPENDED_Disabled

#define TWIM_INTENCLR_SUSPENDED_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENCLR_SUSPENDED_Enabled

#define TWIM_INTENCLR_SUSPENDED_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENCLR_SUSPENDED_Msk

#define TWIM_INTENCLR_SUSPENDED_Msk   (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos)

Bit mask of SUSPENDED field.

◆ TWIM_INTENCLR_SUSPENDED_Pos

#define TWIM_INTENCLR_SUSPENDED_Pos   (18UL)

Position of SUSPENDED field.

◆ TWIM_INTENCLR_TXSTARTED_Clear

#define TWIM_INTENCLR_TXSTARTED_Clear   (1UL)

Disable

◆ TWIM_INTENCLR_TXSTARTED_Disabled

#define TWIM_INTENCLR_TXSTARTED_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENCLR_TXSTARTED_Enabled

#define TWIM_INTENCLR_TXSTARTED_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENCLR_TXSTARTED_Msk

#define TWIM_INTENCLR_TXSTARTED_Msk   (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ TWIM_INTENCLR_TXSTARTED_Pos

#define TWIM_INTENCLR_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ TWIM_INTENSET_ERROR_Disabled

#define TWIM_INTENSET_ERROR_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENSET_ERROR_Enabled

#define TWIM_INTENSET_ERROR_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENSET_ERROR_Msk

#define TWIM_INTENSET_ERROR_Msk   (0x1UL << TWIM_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

◆ TWIM_INTENSET_ERROR_Pos

#define TWIM_INTENSET_ERROR_Pos   (9UL)

Position of ERROR field.

◆ TWIM_INTENSET_ERROR_Set

#define TWIM_INTENSET_ERROR_Set   (1UL)

Enable

◆ TWIM_INTENSET_LASTRX_Disabled

#define TWIM_INTENSET_LASTRX_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENSET_LASTRX_Enabled

#define TWIM_INTENSET_LASTRX_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENSET_LASTRX_Msk

#define TWIM_INTENSET_LASTRX_Msk   (0x1UL << TWIM_INTENSET_LASTRX_Pos)

Bit mask of LASTRX field.

◆ TWIM_INTENSET_LASTRX_Pos

#define TWIM_INTENSET_LASTRX_Pos   (23UL)

Position of LASTRX field.

◆ TWIM_INTENSET_LASTRX_Set

#define TWIM_INTENSET_LASTRX_Set   (1UL)

Enable

◆ TWIM_INTENSET_LASTTX_Disabled

#define TWIM_INTENSET_LASTTX_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENSET_LASTTX_Enabled

#define TWIM_INTENSET_LASTTX_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENSET_LASTTX_Msk

#define TWIM_INTENSET_LASTTX_Msk   (0x1UL << TWIM_INTENSET_LASTTX_Pos)

Bit mask of LASTTX field.

◆ TWIM_INTENSET_LASTTX_Pos

#define TWIM_INTENSET_LASTTX_Pos   (24UL)

Position of LASTTX field.

◆ TWIM_INTENSET_LASTTX_Set

#define TWIM_INTENSET_LASTTX_Set   (1UL)

Enable

◆ TWIM_INTENSET_RXSTARTED_Disabled

#define TWIM_INTENSET_RXSTARTED_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENSET_RXSTARTED_Enabled

#define TWIM_INTENSET_RXSTARTED_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENSET_RXSTARTED_Msk

#define TWIM_INTENSET_RXSTARTED_Msk   (0x1UL << TWIM_INTENSET_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ TWIM_INTENSET_RXSTARTED_Pos

#define TWIM_INTENSET_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ TWIM_INTENSET_RXSTARTED_Set

#define TWIM_INTENSET_RXSTARTED_Set   (1UL)

Enable

◆ TWIM_INTENSET_STOPPED_Disabled

#define TWIM_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENSET_STOPPED_Enabled

#define TWIM_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENSET_STOPPED_Msk

#define TWIM_INTENSET_STOPPED_Msk   (0x1UL << TWIM_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ TWIM_INTENSET_STOPPED_Pos

#define TWIM_INTENSET_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ TWIM_INTENSET_STOPPED_Set

#define TWIM_INTENSET_STOPPED_Set   (1UL)

Enable

◆ TWIM_INTENSET_SUSPENDED_Disabled

#define TWIM_INTENSET_SUSPENDED_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENSET_SUSPENDED_Enabled

#define TWIM_INTENSET_SUSPENDED_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENSET_SUSPENDED_Msk

#define TWIM_INTENSET_SUSPENDED_Msk   (0x1UL << TWIM_INTENSET_SUSPENDED_Pos)

Bit mask of SUSPENDED field.

◆ TWIM_INTENSET_SUSPENDED_Pos

#define TWIM_INTENSET_SUSPENDED_Pos   (18UL)

Position of SUSPENDED field.

◆ TWIM_INTENSET_SUSPENDED_Set

#define TWIM_INTENSET_SUSPENDED_Set   (1UL)

Enable

◆ TWIM_INTENSET_TXSTARTED_Disabled

#define TWIM_INTENSET_TXSTARTED_Disabled   (0UL)

Read: Disabled

◆ TWIM_INTENSET_TXSTARTED_Enabled

#define TWIM_INTENSET_TXSTARTED_Enabled   (1UL)

Read: Enabled

◆ TWIM_INTENSET_TXSTARTED_Msk

#define TWIM_INTENSET_TXSTARTED_Msk   (0x1UL << TWIM_INTENSET_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ TWIM_INTENSET_TXSTARTED_Pos

#define TWIM_INTENSET_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ TWIM_INTENSET_TXSTARTED_Set

#define TWIM_INTENSET_TXSTARTED_Set   (1UL)

Enable

◆ TWIM_PSEL_SCL_CONNECT_Connected

#define TWIM_PSEL_SCL_CONNECT_Connected   (0UL)

Connect

◆ TWIM_PSEL_SCL_CONNECT_Disconnected

#define TWIM_PSEL_SCL_CONNECT_Disconnected   (1UL)

Disconnect

◆ TWIM_PSEL_SCL_CONNECT_Msk

#define TWIM_PSEL_SCL_CONNECT_Msk   (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos)

Bit mask of CONNECT field.

◆ TWIM_PSEL_SCL_CONNECT_Pos

#define TWIM_PSEL_SCL_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ TWIM_PSEL_SCL_PIN_Msk

#define TWIM_PSEL_SCL_PIN_Msk   (0x1FUL << TWIM_PSEL_SCL_PIN_Pos)

Bit mask of PIN field.

◆ TWIM_PSEL_SCL_PIN_Pos

#define TWIM_PSEL_SCL_PIN_Pos   (0UL)

Position of PIN field.

◆ TWIM_PSEL_SDA_CONNECT_Connected

#define TWIM_PSEL_SDA_CONNECT_Connected   (0UL)

Connect

◆ TWIM_PSEL_SDA_CONNECT_Disconnected

#define TWIM_PSEL_SDA_CONNECT_Disconnected   (1UL)

Disconnect

◆ TWIM_PSEL_SDA_CONNECT_Msk

#define TWIM_PSEL_SDA_CONNECT_Msk   (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos)

Bit mask of CONNECT field.

◆ TWIM_PSEL_SDA_CONNECT_Pos

#define TWIM_PSEL_SDA_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ TWIM_PSEL_SDA_PIN_Msk

#define TWIM_PSEL_SDA_PIN_Msk   (0x1FUL << TWIM_PSEL_SDA_PIN_Pos)

Bit mask of PIN field.

◆ TWIM_PSEL_SDA_PIN_Pos

#define TWIM_PSEL_SDA_PIN_Pos   (0UL)

Position of PIN field.

◆ TWIM_RXD_AMOUNT_AMOUNT_Msk

#define TWIM_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ TWIM_RXD_AMOUNT_AMOUNT_Pos

#define TWIM_RXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ TWIM_RXD_LIST_LIST_ArrayList

#define TWIM_RXD_LIST_LIST_ArrayList   (1UL)

Use array list

◆ TWIM_RXD_LIST_LIST_Disabled

#define TWIM_RXD_LIST_LIST_Disabled   (0UL)

Disable EasyDMA list

◆ TWIM_RXD_LIST_LIST_Msk

#define TWIM_RXD_LIST_LIST_Msk   (0x7UL << TWIM_RXD_LIST_LIST_Pos)

Bit mask of LIST field.

◆ TWIM_RXD_LIST_LIST_Pos

#define TWIM_RXD_LIST_LIST_Pos   (0UL)

Position of LIST field.

◆ TWIM_RXD_MAXCNT_MAXCNT_Msk

#define TWIM_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ TWIM_RXD_MAXCNT_MAXCNT_Pos

#define TWIM_RXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ TWIM_RXD_PTR_PTR_Msk

#define TWIM_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ TWIM_RXD_PTR_PTR_Pos

#define TWIM_RXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ TWIM_SHORTS_LASTRX_STARTTX_Disabled

#define TWIM_SHORTS_LASTRX_STARTTX_Disabled   (0UL)

Disable shortcut

◆ TWIM_SHORTS_LASTRX_STARTTX_Enabled

#define TWIM_SHORTS_LASTRX_STARTTX_Enabled   (1UL)

Enable shortcut

◆ TWIM_SHORTS_LASTRX_STARTTX_Msk

#define TWIM_SHORTS_LASTRX_STARTTX_Msk   (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos)

Bit mask of LASTRX_STARTTX field.

◆ TWIM_SHORTS_LASTRX_STARTTX_Pos

#define TWIM_SHORTS_LASTRX_STARTTX_Pos   (10UL)

Position of LASTRX_STARTTX field.

◆ TWIM_SHORTS_LASTRX_STOP_Disabled

#define TWIM_SHORTS_LASTRX_STOP_Disabled   (0UL)

Disable shortcut

◆ TWIM_SHORTS_LASTRX_STOP_Enabled

#define TWIM_SHORTS_LASTRX_STOP_Enabled   (1UL)

Enable shortcut

◆ TWIM_SHORTS_LASTRX_STOP_Msk

#define TWIM_SHORTS_LASTRX_STOP_Msk   (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos)

Bit mask of LASTRX_STOP field.

◆ TWIM_SHORTS_LASTRX_STOP_Pos

#define TWIM_SHORTS_LASTRX_STOP_Pos   (12UL)

Position of LASTRX_STOP field.

◆ TWIM_SHORTS_LASTTX_STARTRX_Disabled

#define TWIM_SHORTS_LASTTX_STARTRX_Disabled   (0UL)

Disable shortcut

◆ TWIM_SHORTS_LASTTX_STARTRX_Enabled

#define TWIM_SHORTS_LASTTX_STARTRX_Enabled   (1UL)

Enable shortcut

◆ TWIM_SHORTS_LASTTX_STARTRX_Msk

#define TWIM_SHORTS_LASTTX_STARTRX_Msk   (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos)

Bit mask of LASTTX_STARTRX field.

◆ TWIM_SHORTS_LASTTX_STARTRX_Pos

#define TWIM_SHORTS_LASTTX_STARTRX_Pos   (7UL)

Position of LASTTX_STARTRX field.

◆ TWIM_SHORTS_LASTTX_STOP_Disabled

#define TWIM_SHORTS_LASTTX_STOP_Disabled   (0UL)

Disable shortcut

◆ TWIM_SHORTS_LASTTX_STOP_Enabled

#define TWIM_SHORTS_LASTTX_STOP_Enabled   (1UL)

Enable shortcut

◆ TWIM_SHORTS_LASTTX_STOP_Msk

#define TWIM_SHORTS_LASTTX_STOP_Msk   (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos)

Bit mask of LASTTX_STOP field.

◆ TWIM_SHORTS_LASTTX_STOP_Pos

#define TWIM_SHORTS_LASTTX_STOP_Pos   (9UL)

Position of LASTTX_STOP field.

◆ TWIM_SHORTS_LASTTX_SUSPEND_Disabled

#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled   (0UL)

Disable shortcut

◆ TWIM_SHORTS_LASTTX_SUSPEND_Enabled

#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled   (1UL)

Enable shortcut

◆ TWIM_SHORTS_LASTTX_SUSPEND_Msk

#define TWIM_SHORTS_LASTTX_SUSPEND_Msk   (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos)

Bit mask of LASTTX_SUSPEND field.

◆ TWIM_SHORTS_LASTTX_SUSPEND_Pos

#define TWIM_SHORTS_LASTTX_SUSPEND_Pos   (8UL)

Position of LASTTX_SUSPEND field.

◆ TWIM_TXD_AMOUNT_AMOUNT_Msk

#define TWIM_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ TWIM_TXD_AMOUNT_AMOUNT_Pos

#define TWIM_TXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ TWIM_TXD_LIST_LIST_ArrayList

#define TWIM_TXD_LIST_LIST_ArrayList   (1UL)

Use array list

◆ TWIM_TXD_LIST_LIST_Disabled

#define TWIM_TXD_LIST_LIST_Disabled   (0UL)

Disable EasyDMA list

◆ TWIM_TXD_LIST_LIST_Msk

#define TWIM_TXD_LIST_LIST_Msk   (0x7UL << TWIM_TXD_LIST_LIST_Pos)

Bit mask of LIST field.

◆ TWIM_TXD_LIST_LIST_Pos

#define TWIM_TXD_LIST_LIST_Pos   (0UL)

Position of LIST field.

◆ TWIM_TXD_MAXCNT_MAXCNT_Msk

#define TWIM_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ TWIM_TXD_MAXCNT_MAXCNT_Pos

#define TWIM_TXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ TWIM_TXD_PTR_PTR_Msk

#define TWIM_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ TWIM_TXD_PTR_PTR_Pos

#define TWIM_TXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ TWIS_ADDRESS_ADDRESS_Msk

#define TWIS_ADDRESS_ADDRESS_Msk   (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos)

Bit mask of ADDRESS field.

◆ TWIS_ADDRESS_ADDRESS_Pos

#define TWIS_ADDRESS_ADDRESS_Pos   (0UL)

Position of ADDRESS field.

◆ TWIS_CONFIG_ADDRESS0_Disabled

#define TWIS_CONFIG_ADDRESS0_Disabled   (0UL)

Disabled

◆ TWIS_CONFIG_ADDRESS0_Enabled

#define TWIS_CONFIG_ADDRESS0_Enabled   (1UL)

Enabled

◆ TWIS_CONFIG_ADDRESS0_Msk

#define TWIS_CONFIG_ADDRESS0_Msk   (0x1UL << TWIS_CONFIG_ADDRESS0_Pos)

Bit mask of ADDRESS0 field.

◆ TWIS_CONFIG_ADDRESS0_Pos

#define TWIS_CONFIG_ADDRESS0_Pos   (0UL)

Position of ADDRESS0 field.

◆ TWIS_CONFIG_ADDRESS1_Disabled

#define TWIS_CONFIG_ADDRESS1_Disabled   (0UL)

Disabled

◆ TWIS_CONFIG_ADDRESS1_Enabled

#define TWIS_CONFIG_ADDRESS1_Enabled   (1UL)

Enabled

◆ TWIS_CONFIG_ADDRESS1_Msk

#define TWIS_CONFIG_ADDRESS1_Msk   (0x1UL << TWIS_CONFIG_ADDRESS1_Pos)

Bit mask of ADDRESS1 field.

◆ TWIS_CONFIG_ADDRESS1_Pos

#define TWIS_CONFIG_ADDRESS1_Pos   (1UL)

Position of ADDRESS1 field.

◆ TWIS_ENABLE_ENABLE_Disabled

#define TWIS_ENABLE_ENABLE_Disabled   (0UL)

Disable TWIS

◆ TWIS_ENABLE_ENABLE_Enabled

#define TWIS_ENABLE_ENABLE_Enabled   (9UL)

Enable TWIS

◆ TWIS_ENABLE_ENABLE_Msk

#define TWIS_ENABLE_ENABLE_Msk   (0xFUL << TWIS_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ TWIS_ENABLE_ENABLE_Pos

#define TWIS_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ TWIS_ERRORSRC_DNACK_Msk

#define TWIS_ERRORSRC_DNACK_Msk   (0x1UL << TWIS_ERRORSRC_DNACK_Pos)

Bit mask of DNACK field.

◆ TWIS_ERRORSRC_DNACK_NotReceived

#define TWIS_ERRORSRC_DNACK_NotReceived   (0UL)

Error did not occur

◆ TWIS_ERRORSRC_DNACK_Pos

#define TWIS_ERRORSRC_DNACK_Pos   (2UL)

Position of DNACK field.

◆ TWIS_ERRORSRC_DNACK_Received

#define TWIS_ERRORSRC_DNACK_Received   (1UL)

Error occurred

◆ TWIS_ERRORSRC_OVERFLOW_Detected

#define TWIS_ERRORSRC_OVERFLOW_Detected   (1UL)

Error occurred

◆ TWIS_ERRORSRC_OVERFLOW_Msk

#define TWIS_ERRORSRC_OVERFLOW_Msk   (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos)

Bit mask of OVERFLOW field.

◆ TWIS_ERRORSRC_OVERFLOW_NotDetected

#define TWIS_ERRORSRC_OVERFLOW_NotDetected   (0UL)

Error did not occur

◆ TWIS_ERRORSRC_OVERFLOW_Pos

#define TWIS_ERRORSRC_OVERFLOW_Pos   (0UL)

Position of OVERFLOW field.

◆ TWIS_ERRORSRC_OVERREAD_Detected

#define TWIS_ERRORSRC_OVERREAD_Detected   (1UL)

Error occurred

◆ TWIS_ERRORSRC_OVERREAD_Msk

#define TWIS_ERRORSRC_OVERREAD_Msk   (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos)

Bit mask of OVERREAD field.

◆ TWIS_ERRORSRC_OVERREAD_NotDetected

#define TWIS_ERRORSRC_OVERREAD_NotDetected   (0UL)

Error did not occur

◆ TWIS_ERRORSRC_OVERREAD_Pos

#define TWIS_ERRORSRC_OVERREAD_Pos   (3UL)

Position of OVERREAD field.

◆ TWIS_INTEN_ERROR_Disabled

#define TWIS_INTEN_ERROR_Disabled   (0UL)

Disable

◆ TWIS_INTEN_ERROR_Enabled

#define TWIS_INTEN_ERROR_Enabled   (1UL)

Enable

◆ TWIS_INTEN_ERROR_Msk

#define TWIS_INTEN_ERROR_Msk   (0x1UL << TWIS_INTEN_ERROR_Pos)

Bit mask of ERROR field.

◆ TWIS_INTEN_ERROR_Pos

#define TWIS_INTEN_ERROR_Pos   (9UL)

Position of ERROR field.

◆ TWIS_INTEN_READ_Disabled

#define TWIS_INTEN_READ_Disabled   (0UL)

Disable

◆ TWIS_INTEN_READ_Enabled

#define TWIS_INTEN_READ_Enabled   (1UL)

Enable

◆ TWIS_INTEN_READ_Msk

#define TWIS_INTEN_READ_Msk   (0x1UL << TWIS_INTEN_READ_Pos)

Bit mask of READ field.

◆ TWIS_INTEN_READ_Pos

#define TWIS_INTEN_READ_Pos   (26UL)

Position of READ field.

◆ TWIS_INTEN_RXSTARTED_Disabled

#define TWIS_INTEN_RXSTARTED_Disabled   (0UL)

Disable

◆ TWIS_INTEN_RXSTARTED_Enabled

#define TWIS_INTEN_RXSTARTED_Enabled   (1UL)

Enable

◆ TWIS_INTEN_RXSTARTED_Msk

#define TWIS_INTEN_RXSTARTED_Msk   (0x1UL << TWIS_INTEN_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ TWIS_INTEN_RXSTARTED_Pos

#define TWIS_INTEN_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ TWIS_INTEN_STOPPED_Disabled

#define TWIS_INTEN_STOPPED_Disabled   (0UL)

Disable

◆ TWIS_INTEN_STOPPED_Enabled

#define TWIS_INTEN_STOPPED_Enabled   (1UL)

Enable

◆ TWIS_INTEN_STOPPED_Msk

#define TWIS_INTEN_STOPPED_Msk   (0x1UL << TWIS_INTEN_STOPPED_Pos)

Bit mask of STOPPED field.

◆ TWIS_INTEN_STOPPED_Pos

#define TWIS_INTEN_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ TWIS_INTEN_TXSTARTED_Disabled

#define TWIS_INTEN_TXSTARTED_Disabled   (0UL)

Disable

◆ TWIS_INTEN_TXSTARTED_Enabled

#define TWIS_INTEN_TXSTARTED_Enabled   (1UL)

Enable

◆ TWIS_INTEN_TXSTARTED_Msk

#define TWIS_INTEN_TXSTARTED_Msk   (0x1UL << TWIS_INTEN_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ TWIS_INTEN_TXSTARTED_Pos

#define TWIS_INTEN_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ TWIS_INTEN_WRITE_Disabled

#define TWIS_INTEN_WRITE_Disabled   (0UL)

Disable

◆ TWIS_INTEN_WRITE_Enabled

#define TWIS_INTEN_WRITE_Enabled   (1UL)

Enable

◆ TWIS_INTEN_WRITE_Msk

#define TWIS_INTEN_WRITE_Msk   (0x1UL << TWIS_INTEN_WRITE_Pos)

Bit mask of WRITE field.

◆ TWIS_INTEN_WRITE_Pos

#define TWIS_INTEN_WRITE_Pos   (25UL)

Position of WRITE field.

◆ TWIS_INTENCLR_ERROR_Clear

#define TWIS_INTENCLR_ERROR_Clear   (1UL)

Disable

◆ TWIS_INTENCLR_ERROR_Disabled

#define TWIS_INTENCLR_ERROR_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENCLR_ERROR_Enabled

#define TWIS_INTENCLR_ERROR_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENCLR_ERROR_Msk

#define TWIS_INTENCLR_ERROR_Msk   (0x1UL << TWIS_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

◆ TWIS_INTENCLR_ERROR_Pos

#define TWIS_INTENCLR_ERROR_Pos   (9UL)

Position of ERROR field.

◆ TWIS_INTENCLR_READ_Clear

#define TWIS_INTENCLR_READ_Clear   (1UL)

Disable

◆ TWIS_INTENCLR_READ_Disabled

#define TWIS_INTENCLR_READ_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENCLR_READ_Enabled

#define TWIS_INTENCLR_READ_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENCLR_READ_Msk

#define TWIS_INTENCLR_READ_Msk   (0x1UL << TWIS_INTENCLR_READ_Pos)

Bit mask of READ field.

◆ TWIS_INTENCLR_READ_Pos

#define TWIS_INTENCLR_READ_Pos   (26UL)

Position of READ field.

◆ TWIS_INTENCLR_RXSTARTED_Clear

#define TWIS_INTENCLR_RXSTARTED_Clear   (1UL)

Disable

◆ TWIS_INTENCLR_RXSTARTED_Disabled

#define TWIS_INTENCLR_RXSTARTED_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENCLR_RXSTARTED_Enabled

#define TWIS_INTENCLR_RXSTARTED_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENCLR_RXSTARTED_Msk

#define TWIS_INTENCLR_RXSTARTED_Msk   (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ TWIS_INTENCLR_RXSTARTED_Pos

#define TWIS_INTENCLR_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ TWIS_INTENCLR_STOPPED_Clear

#define TWIS_INTENCLR_STOPPED_Clear   (1UL)

Disable

◆ TWIS_INTENCLR_STOPPED_Disabled

#define TWIS_INTENCLR_STOPPED_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENCLR_STOPPED_Enabled

#define TWIS_INTENCLR_STOPPED_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENCLR_STOPPED_Msk

#define TWIS_INTENCLR_STOPPED_Msk   (0x1UL << TWIS_INTENCLR_STOPPED_Pos)

Bit mask of STOPPED field.

◆ TWIS_INTENCLR_STOPPED_Pos

#define TWIS_INTENCLR_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ TWIS_INTENCLR_TXSTARTED_Clear

#define TWIS_INTENCLR_TXSTARTED_Clear   (1UL)

Disable

◆ TWIS_INTENCLR_TXSTARTED_Disabled

#define TWIS_INTENCLR_TXSTARTED_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENCLR_TXSTARTED_Enabled

#define TWIS_INTENCLR_TXSTARTED_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENCLR_TXSTARTED_Msk

#define TWIS_INTENCLR_TXSTARTED_Msk   (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ TWIS_INTENCLR_TXSTARTED_Pos

#define TWIS_INTENCLR_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ TWIS_INTENCLR_WRITE_Clear

#define TWIS_INTENCLR_WRITE_Clear   (1UL)

Disable

◆ TWIS_INTENCLR_WRITE_Disabled

#define TWIS_INTENCLR_WRITE_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENCLR_WRITE_Enabled

#define TWIS_INTENCLR_WRITE_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENCLR_WRITE_Msk

#define TWIS_INTENCLR_WRITE_Msk   (0x1UL << TWIS_INTENCLR_WRITE_Pos)

Bit mask of WRITE field.

◆ TWIS_INTENCLR_WRITE_Pos

#define TWIS_INTENCLR_WRITE_Pos   (25UL)

Position of WRITE field.

◆ TWIS_INTENSET_ERROR_Disabled

#define TWIS_INTENSET_ERROR_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENSET_ERROR_Enabled

#define TWIS_INTENSET_ERROR_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENSET_ERROR_Msk

#define TWIS_INTENSET_ERROR_Msk   (0x1UL << TWIS_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

◆ TWIS_INTENSET_ERROR_Pos

#define TWIS_INTENSET_ERROR_Pos   (9UL)

Position of ERROR field.

◆ TWIS_INTENSET_ERROR_Set

#define TWIS_INTENSET_ERROR_Set   (1UL)

Enable

◆ TWIS_INTENSET_READ_Disabled

#define TWIS_INTENSET_READ_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENSET_READ_Enabled

#define TWIS_INTENSET_READ_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENSET_READ_Msk

#define TWIS_INTENSET_READ_Msk   (0x1UL << TWIS_INTENSET_READ_Pos)

Bit mask of READ field.

◆ TWIS_INTENSET_READ_Pos

#define TWIS_INTENSET_READ_Pos   (26UL)

Position of READ field.

◆ TWIS_INTENSET_READ_Set

#define TWIS_INTENSET_READ_Set   (1UL)

Enable

◆ TWIS_INTENSET_RXSTARTED_Disabled

#define TWIS_INTENSET_RXSTARTED_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENSET_RXSTARTED_Enabled

#define TWIS_INTENSET_RXSTARTED_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENSET_RXSTARTED_Msk

#define TWIS_INTENSET_RXSTARTED_Msk   (0x1UL << TWIS_INTENSET_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ TWIS_INTENSET_RXSTARTED_Pos

#define TWIS_INTENSET_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ TWIS_INTENSET_RXSTARTED_Set

#define TWIS_INTENSET_RXSTARTED_Set   (1UL)

Enable

◆ TWIS_INTENSET_STOPPED_Disabled

#define TWIS_INTENSET_STOPPED_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENSET_STOPPED_Enabled

#define TWIS_INTENSET_STOPPED_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENSET_STOPPED_Msk

#define TWIS_INTENSET_STOPPED_Msk   (0x1UL << TWIS_INTENSET_STOPPED_Pos)

Bit mask of STOPPED field.

◆ TWIS_INTENSET_STOPPED_Pos

#define TWIS_INTENSET_STOPPED_Pos   (1UL)

Position of STOPPED field.

◆ TWIS_INTENSET_STOPPED_Set

#define TWIS_INTENSET_STOPPED_Set   (1UL)

Enable

◆ TWIS_INTENSET_TXSTARTED_Disabled

#define TWIS_INTENSET_TXSTARTED_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENSET_TXSTARTED_Enabled

#define TWIS_INTENSET_TXSTARTED_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENSET_TXSTARTED_Msk

#define TWIS_INTENSET_TXSTARTED_Msk   (0x1UL << TWIS_INTENSET_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ TWIS_INTENSET_TXSTARTED_Pos

#define TWIS_INTENSET_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ TWIS_INTENSET_TXSTARTED_Set

#define TWIS_INTENSET_TXSTARTED_Set   (1UL)

Enable

◆ TWIS_INTENSET_WRITE_Disabled

#define TWIS_INTENSET_WRITE_Disabled   (0UL)

Read: Disabled

◆ TWIS_INTENSET_WRITE_Enabled

#define TWIS_INTENSET_WRITE_Enabled   (1UL)

Read: Enabled

◆ TWIS_INTENSET_WRITE_Msk

#define TWIS_INTENSET_WRITE_Msk   (0x1UL << TWIS_INTENSET_WRITE_Pos)

Bit mask of WRITE field.

◆ TWIS_INTENSET_WRITE_Pos

#define TWIS_INTENSET_WRITE_Pos   (25UL)

Position of WRITE field.

◆ TWIS_INTENSET_WRITE_Set

#define TWIS_INTENSET_WRITE_Set   (1UL)

Enable

◆ TWIS_MATCH_MATCH_Msk

#define TWIS_MATCH_MATCH_Msk   (0x1UL << TWIS_MATCH_MATCH_Pos)

Bit mask of MATCH field.

◆ TWIS_MATCH_MATCH_Pos

#define TWIS_MATCH_MATCH_Pos   (0UL)

Position of MATCH field.

◆ TWIS_ORC_ORC_Msk

#define TWIS_ORC_ORC_Msk   (0xFFUL << TWIS_ORC_ORC_Pos)

Bit mask of ORC field.

◆ TWIS_ORC_ORC_Pos

#define TWIS_ORC_ORC_Pos   (0UL)

Position of ORC field.

◆ TWIS_PSEL_SCL_CONNECT_Connected

#define TWIS_PSEL_SCL_CONNECT_Connected   (0UL)

Connect

◆ TWIS_PSEL_SCL_CONNECT_Disconnected

#define TWIS_PSEL_SCL_CONNECT_Disconnected   (1UL)

Disconnect

◆ TWIS_PSEL_SCL_CONNECT_Msk

#define TWIS_PSEL_SCL_CONNECT_Msk   (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos)

Bit mask of CONNECT field.

◆ TWIS_PSEL_SCL_CONNECT_Pos

#define TWIS_PSEL_SCL_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ TWIS_PSEL_SCL_PIN_Msk

#define TWIS_PSEL_SCL_PIN_Msk   (0x1FUL << TWIS_PSEL_SCL_PIN_Pos)

Bit mask of PIN field.

◆ TWIS_PSEL_SCL_PIN_Pos

#define TWIS_PSEL_SCL_PIN_Pos   (0UL)

Position of PIN field.

◆ TWIS_PSEL_SDA_CONNECT_Connected

#define TWIS_PSEL_SDA_CONNECT_Connected   (0UL)

Connect

◆ TWIS_PSEL_SDA_CONNECT_Disconnected

#define TWIS_PSEL_SDA_CONNECT_Disconnected   (1UL)

Disconnect

◆ TWIS_PSEL_SDA_CONNECT_Msk

#define TWIS_PSEL_SDA_CONNECT_Msk   (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos)

Bit mask of CONNECT field.

◆ TWIS_PSEL_SDA_CONNECT_Pos

#define TWIS_PSEL_SDA_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ TWIS_PSEL_SDA_PIN_Msk

#define TWIS_PSEL_SDA_PIN_Msk   (0x1FUL << TWIS_PSEL_SDA_PIN_Pos)

Bit mask of PIN field.

◆ TWIS_PSEL_SDA_PIN_Pos

#define TWIS_PSEL_SDA_PIN_Pos   (0UL)

Position of PIN field.

◆ TWIS_RXD_AMOUNT_AMOUNT_Msk

#define TWIS_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ TWIS_RXD_AMOUNT_AMOUNT_Pos

#define TWIS_RXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ TWIS_RXD_MAXCNT_MAXCNT_Msk

#define TWIS_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ TWIS_RXD_MAXCNT_MAXCNT_Pos

#define TWIS_RXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ TWIS_RXD_PTR_PTR_Msk

#define TWIS_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ TWIS_RXD_PTR_PTR_Pos

#define TWIS_RXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ TWIS_SHORTS_READ_SUSPEND_Disabled

#define TWIS_SHORTS_READ_SUSPEND_Disabled   (0UL)

Disable shortcut

◆ TWIS_SHORTS_READ_SUSPEND_Enabled

#define TWIS_SHORTS_READ_SUSPEND_Enabled   (1UL)

Enable shortcut

◆ TWIS_SHORTS_READ_SUSPEND_Msk

#define TWIS_SHORTS_READ_SUSPEND_Msk   (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos)

Bit mask of READ_SUSPEND field.

◆ TWIS_SHORTS_READ_SUSPEND_Pos

#define TWIS_SHORTS_READ_SUSPEND_Pos   (14UL)

Position of READ_SUSPEND field.

◆ TWIS_SHORTS_WRITE_SUSPEND_Disabled

#define TWIS_SHORTS_WRITE_SUSPEND_Disabled   (0UL)

Disable shortcut

◆ TWIS_SHORTS_WRITE_SUSPEND_Enabled

#define TWIS_SHORTS_WRITE_SUSPEND_Enabled   (1UL)

Enable shortcut

◆ TWIS_SHORTS_WRITE_SUSPEND_Msk

#define TWIS_SHORTS_WRITE_SUSPEND_Msk   (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos)

Bit mask of WRITE_SUSPEND field.

◆ TWIS_SHORTS_WRITE_SUSPEND_Pos

#define TWIS_SHORTS_WRITE_SUSPEND_Pos   (13UL)

Position of WRITE_SUSPEND field.

◆ TWIS_TXD_AMOUNT_AMOUNT_Msk

#define TWIS_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ TWIS_TXD_AMOUNT_AMOUNT_Pos

#define TWIS_TXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ TWIS_TXD_MAXCNT_MAXCNT_Msk

#define TWIS_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ TWIS_TXD_MAXCNT_MAXCNT_Pos

#define TWIS_TXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ TWIS_TXD_PTR_PTR_Msk

#define TWIS_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ TWIS_TXD_PTR_PTR_Pos

#define TWIS_TXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ UART_BAUDRATE_BAUDRATE_Baud115200

#define UART_BAUDRATE_BAUDRATE_Baud115200   (0x01D7E000UL)

115200 baud (actual rate: 115942)

◆ UART_BAUDRATE_BAUDRATE_Baud1200

#define UART_BAUDRATE_BAUDRATE_Baud1200   (0x0004F000UL)

1200 baud (actual rate: 1205)

◆ UART_BAUDRATE_BAUDRATE_Baud14400

#define UART_BAUDRATE_BAUDRATE_Baud14400   (0x003B0000UL)

14400 baud (actual rate: 14414)

◆ UART_BAUDRATE_BAUDRATE_Baud19200

#define UART_BAUDRATE_BAUDRATE_Baud19200   (0x004EA000UL)

19200 baud (actual rate: 19208)

◆ UART_BAUDRATE_BAUDRATE_Baud1M

#define UART_BAUDRATE_BAUDRATE_Baud1M   (0x10000000UL)

1Mega baud

◆ UART_BAUDRATE_BAUDRATE_Baud230400

#define UART_BAUDRATE_BAUDRATE_Baud230400   (0x03AFB000UL)

230400 baud (actual rate: 231884)

◆ UART_BAUDRATE_BAUDRATE_Baud2400

#define UART_BAUDRATE_BAUDRATE_Baud2400   (0x0009D000UL)

2400 baud (actual rate: 2396)

◆ UART_BAUDRATE_BAUDRATE_Baud250000

#define UART_BAUDRATE_BAUDRATE_Baud250000   (0x04000000UL)

250000 baud

◆ UART_BAUDRATE_BAUDRATE_Baud28800

#define UART_BAUDRATE_BAUDRATE_Baud28800   (0x0075F000UL)

28800 baud (actual rate: 28829)

◆ UART_BAUDRATE_BAUDRATE_Baud31250

#define UART_BAUDRATE_BAUDRATE_Baud31250   (0x00800000UL)

31250 baud

◆ UART_BAUDRATE_BAUDRATE_Baud38400

#define UART_BAUDRATE_BAUDRATE_Baud38400   (0x009D5000UL)

38400 baud (actual rate: 38462)

◆ UART_BAUDRATE_BAUDRATE_Baud460800

#define UART_BAUDRATE_BAUDRATE_Baud460800   (0x075F7000UL)

460800 baud (actual rate: 470588)

◆ UART_BAUDRATE_BAUDRATE_Baud4800

#define UART_BAUDRATE_BAUDRATE_Baud4800   (0x0013B000UL)

4800 baud (actual rate: 4808)

◆ UART_BAUDRATE_BAUDRATE_Baud56000

#define UART_BAUDRATE_BAUDRATE_Baud56000   (0x00E50000UL)

56000 baud (actual rate: 55944)

◆ UART_BAUDRATE_BAUDRATE_Baud57600

#define UART_BAUDRATE_BAUDRATE_Baud57600   (0x00EBF000UL)

57600 baud (actual rate: 57762)

◆ UART_BAUDRATE_BAUDRATE_Baud76800

#define UART_BAUDRATE_BAUDRATE_Baud76800   (0x013A9000UL)

76800 baud (actual rate: 76923)

◆ UART_BAUDRATE_BAUDRATE_Baud921600

#define UART_BAUDRATE_BAUDRATE_Baud921600   (0x0EBED000UL)

921600 baud (actual rate: 941176)

◆ UART_BAUDRATE_BAUDRATE_Baud9600

#define UART_BAUDRATE_BAUDRATE_Baud9600   (0x00275000UL)

9600 baud (actual rate: 9598)

◆ UART_BAUDRATE_BAUDRATE_Msk

#define UART_BAUDRATE_BAUDRATE_Msk   (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos)

Bit mask of BAUDRATE field.

◆ UART_BAUDRATE_BAUDRATE_Pos

#define UART_BAUDRATE_BAUDRATE_Pos   (0UL)

Position of BAUDRATE field.

◆ UART_CONFIG_HWFC_Disabled

#define UART_CONFIG_HWFC_Disabled   (0UL)

Disabled

◆ UART_CONFIG_HWFC_Enabled

#define UART_CONFIG_HWFC_Enabled   (1UL)

Enabled

◆ UART_CONFIG_HWFC_Msk

#define UART_CONFIG_HWFC_Msk   (0x1UL << UART_CONFIG_HWFC_Pos)

Bit mask of HWFC field.

◆ UART_CONFIG_HWFC_Pos

#define UART_CONFIG_HWFC_Pos   (0UL)

Position of HWFC field.

◆ UART_CONFIG_PARITY_Excluded

#define UART_CONFIG_PARITY_Excluded   (0x0UL)

Exclude parity bit

◆ UART_CONFIG_PARITY_Included

#define UART_CONFIG_PARITY_Included   (0x7UL)

Include parity bit

◆ UART_CONFIG_PARITY_Msk

#define UART_CONFIG_PARITY_Msk   (0x7UL << UART_CONFIG_PARITY_Pos)

Bit mask of PARITY field.

◆ UART_CONFIG_PARITY_Pos

#define UART_CONFIG_PARITY_Pos   (1UL)

Position of PARITY field.

◆ UART_ENABLE_ENABLE_Disabled

#define UART_ENABLE_ENABLE_Disabled   (0UL)

Disable UART

◆ UART_ENABLE_ENABLE_Enabled

#define UART_ENABLE_ENABLE_Enabled   (4UL)

Enable UART

◆ UART_ENABLE_ENABLE_Msk

#define UART_ENABLE_ENABLE_Msk   (0xFUL << UART_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ UART_ENABLE_ENABLE_Pos

#define UART_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ UART_ERRORSRC_BREAK_Msk

#define UART_ERRORSRC_BREAK_Msk   (0x1UL << UART_ERRORSRC_BREAK_Pos)

Bit mask of BREAK field.

◆ UART_ERRORSRC_BREAK_NotPresent

#define UART_ERRORSRC_BREAK_NotPresent   (0UL)

Read: error not present

◆ UART_ERRORSRC_BREAK_Pos

#define UART_ERRORSRC_BREAK_Pos   (3UL)

Position of BREAK field.

◆ UART_ERRORSRC_BREAK_Present

#define UART_ERRORSRC_BREAK_Present   (1UL)

Read: error present

◆ UART_ERRORSRC_FRAMING_Msk

#define UART_ERRORSRC_FRAMING_Msk   (0x1UL << UART_ERRORSRC_FRAMING_Pos)

Bit mask of FRAMING field.

◆ UART_ERRORSRC_FRAMING_NotPresent

#define UART_ERRORSRC_FRAMING_NotPresent   (0UL)

Read: error not present

◆ UART_ERRORSRC_FRAMING_Pos

#define UART_ERRORSRC_FRAMING_Pos   (2UL)

Position of FRAMING field.

◆ UART_ERRORSRC_FRAMING_Present

#define UART_ERRORSRC_FRAMING_Present   (1UL)

Read: error present

◆ UART_ERRORSRC_OVERRUN_Msk

#define UART_ERRORSRC_OVERRUN_Msk   (0x1UL << UART_ERRORSRC_OVERRUN_Pos)

Bit mask of OVERRUN field.

◆ UART_ERRORSRC_OVERRUN_NotPresent

#define UART_ERRORSRC_OVERRUN_NotPresent   (0UL)

Read: error not present

◆ UART_ERRORSRC_OVERRUN_Pos

#define UART_ERRORSRC_OVERRUN_Pos   (0UL)

Position of OVERRUN field.

◆ UART_ERRORSRC_OVERRUN_Present

#define UART_ERRORSRC_OVERRUN_Present   (1UL)

Read: error present

◆ UART_ERRORSRC_PARITY_Msk

#define UART_ERRORSRC_PARITY_Msk   (0x1UL << UART_ERRORSRC_PARITY_Pos)

Bit mask of PARITY field.

◆ UART_ERRORSRC_PARITY_NotPresent

#define UART_ERRORSRC_PARITY_NotPresent   (0UL)

Read: error not present

◆ UART_ERRORSRC_PARITY_Pos

#define UART_ERRORSRC_PARITY_Pos   (1UL)

Position of PARITY field.

◆ UART_ERRORSRC_PARITY_Present

#define UART_ERRORSRC_PARITY_Present   (1UL)

Read: error present

◆ UART_INTENCLR_CTS_Clear

#define UART_INTENCLR_CTS_Clear   (1UL)

Disable

◆ UART_INTENCLR_CTS_Disabled

#define UART_INTENCLR_CTS_Disabled   (0UL)

Read: Disabled

◆ UART_INTENCLR_CTS_Enabled

#define UART_INTENCLR_CTS_Enabled   (1UL)

Read: Enabled

◆ UART_INTENCLR_CTS_Msk

#define UART_INTENCLR_CTS_Msk   (0x1UL << UART_INTENCLR_CTS_Pos)

Bit mask of CTS field.

◆ UART_INTENCLR_CTS_Pos

#define UART_INTENCLR_CTS_Pos   (0UL)

Position of CTS field.

◆ UART_INTENCLR_ERROR_Clear

#define UART_INTENCLR_ERROR_Clear   (1UL)

Disable

◆ UART_INTENCLR_ERROR_Disabled

#define UART_INTENCLR_ERROR_Disabled   (0UL)

Read: Disabled

◆ UART_INTENCLR_ERROR_Enabled

#define UART_INTENCLR_ERROR_Enabled   (1UL)

Read: Enabled

◆ UART_INTENCLR_ERROR_Msk

#define UART_INTENCLR_ERROR_Msk   (0x1UL << UART_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

◆ UART_INTENCLR_ERROR_Pos

#define UART_INTENCLR_ERROR_Pos   (9UL)

Position of ERROR field.

◆ UART_INTENCLR_NCTS_Clear

#define UART_INTENCLR_NCTS_Clear   (1UL)

Disable

◆ UART_INTENCLR_NCTS_Disabled

#define UART_INTENCLR_NCTS_Disabled   (0UL)

Read: Disabled

◆ UART_INTENCLR_NCTS_Enabled

#define UART_INTENCLR_NCTS_Enabled   (1UL)

Read: Enabled

◆ UART_INTENCLR_NCTS_Msk

#define UART_INTENCLR_NCTS_Msk   (0x1UL << UART_INTENCLR_NCTS_Pos)

Bit mask of NCTS field.

◆ UART_INTENCLR_NCTS_Pos

#define UART_INTENCLR_NCTS_Pos   (1UL)

Position of NCTS field.

◆ UART_INTENCLR_RXDRDY_Clear

#define UART_INTENCLR_RXDRDY_Clear   (1UL)

Disable

◆ UART_INTENCLR_RXDRDY_Disabled

#define UART_INTENCLR_RXDRDY_Disabled   (0UL)

Read: Disabled

◆ UART_INTENCLR_RXDRDY_Enabled

#define UART_INTENCLR_RXDRDY_Enabled   (1UL)

Read: Enabled

◆ UART_INTENCLR_RXDRDY_Msk

#define UART_INTENCLR_RXDRDY_Msk   (0x1UL << UART_INTENCLR_RXDRDY_Pos)

Bit mask of RXDRDY field.

◆ UART_INTENCLR_RXDRDY_Pos

#define UART_INTENCLR_RXDRDY_Pos   (2UL)

Position of RXDRDY field.

◆ UART_INTENCLR_RXTO_Clear

#define UART_INTENCLR_RXTO_Clear   (1UL)

Disable

◆ UART_INTENCLR_RXTO_Disabled

#define UART_INTENCLR_RXTO_Disabled   (0UL)

Read: Disabled

◆ UART_INTENCLR_RXTO_Enabled

#define UART_INTENCLR_RXTO_Enabled   (1UL)

Read: Enabled

◆ UART_INTENCLR_RXTO_Msk

#define UART_INTENCLR_RXTO_Msk   (0x1UL << UART_INTENCLR_RXTO_Pos)

Bit mask of RXTO field.

◆ UART_INTENCLR_RXTO_Pos

#define UART_INTENCLR_RXTO_Pos   (17UL)

Position of RXTO field.

◆ UART_INTENCLR_TXDRDY_Clear

#define UART_INTENCLR_TXDRDY_Clear   (1UL)

Disable

◆ UART_INTENCLR_TXDRDY_Disabled

#define UART_INTENCLR_TXDRDY_Disabled   (0UL)

Read: Disabled

◆ UART_INTENCLR_TXDRDY_Enabled

#define UART_INTENCLR_TXDRDY_Enabled   (1UL)

Read: Enabled

◆ UART_INTENCLR_TXDRDY_Msk

#define UART_INTENCLR_TXDRDY_Msk   (0x1UL << UART_INTENCLR_TXDRDY_Pos)

Bit mask of TXDRDY field.

◆ UART_INTENCLR_TXDRDY_Pos

#define UART_INTENCLR_TXDRDY_Pos   (7UL)

Position of TXDRDY field.

◆ UART_INTENSET_CTS_Disabled

#define UART_INTENSET_CTS_Disabled   (0UL)

Read: Disabled

◆ UART_INTENSET_CTS_Enabled

#define UART_INTENSET_CTS_Enabled   (1UL)

Read: Enabled

◆ UART_INTENSET_CTS_Msk

#define UART_INTENSET_CTS_Msk   (0x1UL << UART_INTENSET_CTS_Pos)

Bit mask of CTS field.

◆ UART_INTENSET_CTS_Pos

#define UART_INTENSET_CTS_Pos   (0UL)

Position of CTS field.

◆ UART_INTENSET_CTS_Set

#define UART_INTENSET_CTS_Set   (1UL)

Enable

◆ UART_INTENSET_ERROR_Disabled

#define UART_INTENSET_ERROR_Disabled   (0UL)

Read: Disabled

◆ UART_INTENSET_ERROR_Enabled

#define UART_INTENSET_ERROR_Enabled   (1UL)

Read: Enabled

◆ UART_INTENSET_ERROR_Msk

#define UART_INTENSET_ERROR_Msk   (0x1UL << UART_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

◆ UART_INTENSET_ERROR_Pos

#define UART_INTENSET_ERROR_Pos   (9UL)

Position of ERROR field.

◆ UART_INTENSET_ERROR_Set

#define UART_INTENSET_ERROR_Set   (1UL)

Enable

◆ UART_INTENSET_NCTS_Disabled

#define UART_INTENSET_NCTS_Disabled   (0UL)

Read: Disabled

◆ UART_INTENSET_NCTS_Enabled

#define UART_INTENSET_NCTS_Enabled   (1UL)

Read: Enabled

◆ UART_INTENSET_NCTS_Msk

#define UART_INTENSET_NCTS_Msk   (0x1UL << UART_INTENSET_NCTS_Pos)

Bit mask of NCTS field.

◆ UART_INTENSET_NCTS_Pos

#define UART_INTENSET_NCTS_Pos   (1UL)

Position of NCTS field.

◆ UART_INTENSET_NCTS_Set

#define UART_INTENSET_NCTS_Set   (1UL)

Enable

◆ UART_INTENSET_RXDRDY_Disabled

#define UART_INTENSET_RXDRDY_Disabled   (0UL)

Read: Disabled

◆ UART_INTENSET_RXDRDY_Enabled

#define UART_INTENSET_RXDRDY_Enabled   (1UL)

Read: Enabled

◆ UART_INTENSET_RXDRDY_Msk

#define UART_INTENSET_RXDRDY_Msk   (0x1UL << UART_INTENSET_RXDRDY_Pos)

Bit mask of RXDRDY field.

◆ UART_INTENSET_RXDRDY_Pos

#define UART_INTENSET_RXDRDY_Pos   (2UL)

Position of RXDRDY field.

◆ UART_INTENSET_RXDRDY_Set

#define UART_INTENSET_RXDRDY_Set   (1UL)

Enable

◆ UART_INTENSET_RXTO_Disabled

#define UART_INTENSET_RXTO_Disabled   (0UL)

Read: Disabled

◆ UART_INTENSET_RXTO_Enabled

#define UART_INTENSET_RXTO_Enabled   (1UL)

Read: Enabled

◆ UART_INTENSET_RXTO_Msk

#define UART_INTENSET_RXTO_Msk   (0x1UL << UART_INTENSET_RXTO_Pos)

Bit mask of RXTO field.

◆ UART_INTENSET_RXTO_Pos

#define UART_INTENSET_RXTO_Pos   (17UL)

Position of RXTO field.

◆ UART_INTENSET_RXTO_Set

#define UART_INTENSET_RXTO_Set   (1UL)

Enable

◆ UART_INTENSET_TXDRDY_Disabled

#define UART_INTENSET_TXDRDY_Disabled   (0UL)

Read: Disabled

◆ UART_INTENSET_TXDRDY_Enabled

#define UART_INTENSET_TXDRDY_Enabled   (1UL)

Read: Enabled

◆ UART_INTENSET_TXDRDY_Msk

#define UART_INTENSET_TXDRDY_Msk   (0x1UL << UART_INTENSET_TXDRDY_Pos)

Bit mask of TXDRDY field.

◆ UART_INTENSET_TXDRDY_Pos

#define UART_INTENSET_TXDRDY_Pos   (7UL)

Position of TXDRDY field.

◆ UART_INTENSET_TXDRDY_Set

#define UART_INTENSET_TXDRDY_Set   (1UL)

Enable

◆ UART_PSELCTS_PSELCTS_Disconnected

#define UART_PSELCTS_PSELCTS_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ UART_PSELCTS_PSELCTS_Msk

#define UART_PSELCTS_PSELCTS_Msk   (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos)

Bit mask of PSELCTS field.

◆ UART_PSELCTS_PSELCTS_Pos

#define UART_PSELCTS_PSELCTS_Pos   (0UL)

Position of PSELCTS field.

◆ UART_PSELRTS_PSELRTS_Disconnected

#define UART_PSELRTS_PSELRTS_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ UART_PSELRTS_PSELRTS_Msk

#define UART_PSELRTS_PSELRTS_Msk   (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos)

Bit mask of PSELRTS field.

◆ UART_PSELRTS_PSELRTS_Pos

#define UART_PSELRTS_PSELRTS_Pos   (0UL)

Position of PSELRTS field.

◆ UART_PSELRXD_PSELRXD_Disconnected

#define UART_PSELRXD_PSELRXD_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ UART_PSELRXD_PSELRXD_Msk

#define UART_PSELRXD_PSELRXD_Msk   (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos)

Bit mask of PSELRXD field.

◆ UART_PSELRXD_PSELRXD_Pos

#define UART_PSELRXD_PSELRXD_Pos   (0UL)

Position of PSELRXD field.

◆ UART_PSELTXD_PSELTXD_Disconnected

#define UART_PSELTXD_PSELTXD_Disconnected   (0xFFFFFFFFUL)

Disconnect

◆ UART_PSELTXD_PSELTXD_Msk

#define UART_PSELTXD_PSELTXD_Msk   (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos)

Bit mask of PSELTXD field.

◆ UART_PSELTXD_PSELTXD_Pos

#define UART_PSELTXD_PSELTXD_Pos   (0UL)

Position of PSELTXD field.

◆ UART_RXD_RXD_Msk

#define UART_RXD_RXD_Msk   (0xFFUL << UART_RXD_RXD_Pos)

Bit mask of RXD field.

◆ UART_RXD_RXD_Pos

#define UART_RXD_RXD_Pos   (0UL)

Position of RXD field.

◆ UART_SHORTS_CTS_STARTRX_Disabled

#define UART_SHORTS_CTS_STARTRX_Disabled   (0UL)

Disable shortcut

◆ UART_SHORTS_CTS_STARTRX_Enabled

#define UART_SHORTS_CTS_STARTRX_Enabled   (1UL)

Enable shortcut

◆ UART_SHORTS_CTS_STARTRX_Msk

#define UART_SHORTS_CTS_STARTRX_Msk   (0x1UL << UART_SHORTS_CTS_STARTRX_Pos)

Bit mask of CTS_STARTRX field.

◆ UART_SHORTS_CTS_STARTRX_Pos

#define UART_SHORTS_CTS_STARTRX_Pos   (3UL)

Position of CTS_STARTRX field.

◆ UART_SHORTS_NCTS_STOPRX_Disabled

#define UART_SHORTS_NCTS_STOPRX_Disabled   (0UL)

Disable shortcut

◆ UART_SHORTS_NCTS_STOPRX_Enabled

#define UART_SHORTS_NCTS_STOPRX_Enabled   (1UL)

Enable shortcut

◆ UART_SHORTS_NCTS_STOPRX_Msk

#define UART_SHORTS_NCTS_STOPRX_Msk   (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos)

Bit mask of NCTS_STOPRX field.

◆ UART_SHORTS_NCTS_STOPRX_Pos

#define UART_SHORTS_NCTS_STOPRX_Pos   (4UL)

Position of NCTS_STOPRX field.

◆ UART_TXD_TXD_Msk

#define UART_TXD_TXD_Msk   (0xFFUL << UART_TXD_TXD_Pos)

Bit mask of TXD field.

◆ UART_TXD_TXD_Pos

#define UART_TXD_TXD_Pos   (0UL)

Position of TXD field.

◆ UARTE_BAUDRATE_BAUDRATE_Baud115200

#define UARTE_BAUDRATE_BAUDRATE_Baud115200   (0x01D60000UL)

115200 baud (actual rate: 115108)

◆ UARTE_BAUDRATE_BAUDRATE_Baud1200

#define UARTE_BAUDRATE_BAUDRATE_Baud1200   (0x0004F000UL)

1200 baud (actual rate: 1205)

◆ UARTE_BAUDRATE_BAUDRATE_Baud14400

#define UARTE_BAUDRATE_BAUDRATE_Baud14400   (0x003AF000UL)

14400 baud (actual rate: 14401)

◆ UARTE_BAUDRATE_BAUDRATE_Baud19200

#define UARTE_BAUDRATE_BAUDRATE_Baud19200   (0x004EA000UL)

19200 baud (actual rate: 19208)

◆ UARTE_BAUDRATE_BAUDRATE_Baud1M

#define UARTE_BAUDRATE_BAUDRATE_Baud1M   (0x10000000UL)

1Mega baud

◆ UARTE_BAUDRATE_BAUDRATE_Baud230400

#define UARTE_BAUDRATE_BAUDRATE_Baud230400   (0x03B00000UL)

230400 baud (actual rate: 231884)

◆ UARTE_BAUDRATE_BAUDRATE_Baud2400

#define UARTE_BAUDRATE_BAUDRATE_Baud2400   (0x0009D000UL)

2400 baud (actual rate: 2396)

◆ UARTE_BAUDRATE_BAUDRATE_Baud250000

#define UARTE_BAUDRATE_BAUDRATE_Baud250000   (0x04000000UL)

250000 baud

◆ UARTE_BAUDRATE_BAUDRATE_Baud28800

#define UARTE_BAUDRATE_BAUDRATE_Baud28800   (0x0075C000UL)

28800 baud (actual rate: 28777)

◆ UARTE_BAUDRATE_BAUDRATE_Baud31250

#define UARTE_BAUDRATE_BAUDRATE_Baud31250   (0x00800000UL)

31250 baud

◆ UARTE_BAUDRATE_BAUDRATE_Baud38400

#define UARTE_BAUDRATE_BAUDRATE_Baud38400   (0x009D0000UL)

38400 baud (actual rate: 38369)

◆ UARTE_BAUDRATE_BAUDRATE_Baud460800

#define UARTE_BAUDRATE_BAUDRATE_Baud460800   (0x07400000UL)

460800 baud (actual rate: 457143)

◆ UARTE_BAUDRATE_BAUDRATE_Baud4800

#define UARTE_BAUDRATE_BAUDRATE_Baud4800   (0x0013B000UL)

4800 baud (actual rate: 4808)

◆ UARTE_BAUDRATE_BAUDRATE_Baud56000

#define UARTE_BAUDRATE_BAUDRATE_Baud56000   (0x00E50000UL)

56000 baud (actual rate: 55944)

◆ UARTE_BAUDRATE_BAUDRATE_Baud57600

#define UARTE_BAUDRATE_BAUDRATE_Baud57600   (0x00EB0000UL)

57600 baud (actual rate: 57554)

◆ UARTE_BAUDRATE_BAUDRATE_Baud76800

#define UARTE_BAUDRATE_BAUDRATE_Baud76800   (0x013A9000UL)

76800 baud (actual rate: 76923)

◆ UARTE_BAUDRATE_BAUDRATE_Baud921600

#define UARTE_BAUDRATE_BAUDRATE_Baud921600   (0x0F000000UL)

921600 baud (actual rate: 941176)

◆ UARTE_BAUDRATE_BAUDRATE_Baud9600

#define UARTE_BAUDRATE_BAUDRATE_Baud9600   (0x00275000UL)

9600 baud (actual rate: 9598)

◆ UARTE_BAUDRATE_BAUDRATE_Msk

#define UARTE_BAUDRATE_BAUDRATE_Msk   (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos)

Bit mask of BAUDRATE field.

◆ UARTE_BAUDRATE_BAUDRATE_Pos

#define UARTE_BAUDRATE_BAUDRATE_Pos   (0UL)

Position of BAUDRATE field.

◆ UARTE_CONFIG_HWFC_Disabled

#define UARTE_CONFIG_HWFC_Disabled   (0UL)

Disabled

◆ UARTE_CONFIG_HWFC_Enabled

#define UARTE_CONFIG_HWFC_Enabled   (1UL)

Enabled

◆ UARTE_CONFIG_HWFC_Msk

#define UARTE_CONFIG_HWFC_Msk   (0x1UL << UARTE_CONFIG_HWFC_Pos)

Bit mask of HWFC field.

◆ UARTE_CONFIG_HWFC_Pos

#define UARTE_CONFIG_HWFC_Pos   (0UL)

Position of HWFC field.

◆ UARTE_CONFIG_PARITY_Excluded

#define UARTE_CONFIG_PARITY_Excluded   (0x0UL)

Exclude parity bit

◆ UARTE_CONFIG_PARITY_Included

#define UARTE_CONFIG_PARITY_Included   (0x7UL)

Include parity bit

◆ UARTE_CONFIG_PARITY_Msk

#define UARTE_CONFIG_PARITY_Msk   (0x7UL << UARTE_CONFIG_PARITY_Pos)

Bit mask of PARITY field.

◆ UARTE_CONFIG_PARITY_Pos

#define UARTE_CONFIG_PARITY_Pos   (1UL)

Position of PARITY field.

◆ UARTE_ENABLE_ENABLE_Disabled

#define UARTE_ENABLE_ENABLE_Disabled   (0UL)

Disable UARTE

◆ UARTE_ENABLE_ENABLE_Enabled

#define UARTE_ENABLE_ENABLE_Enabled   (8UL)

Enable UARTE

◆ UARTE_ENABLE_ENABLE_Msk

#define UARTE_ENABLE_ENABLE_Msk   (0xFUL << UARTE_ENABLE_ENABLE_Pos)

Bit mask of ENABLE field.

◆ UARTE_ENABLE_ENABLE_Pos

#define UARTE_ENABLE_ENABLE_Pos   (0UL)

Position of ENABLE field.

◆ UARTE_ERRORSRC_BREAK_Msk

#define UARTE_ERRORSRC_BREAK_Msk   (0x1UL << UARTE_ERRORSRC_BREAK_Pos)

Bit mask of BREAK field.

◆ UARTE_ERRORSRC_BREAK_NotPresent

#define UARTE_ERRORSRC_BREAK_NotPresent   (0UL)

Read: error not present

◆ UARTE_ERRORSRC_BREAK_Pos

#define UARTE_ERRORSRC_BREAK_Pos   (3UL)

Position of BREAK field.

◆ UARTE_ERRORSRC_BREAK_Present

#define UARTE_ERRORSRC_BREAK_Present   (1UL)

Read: error present

◆ UARTE_ERRORSRC_FRAMING_Msk

#define UARTE_ERRORSRC_FRAMING_Msk   (0x1UL << UARTE_ERRORSRC_FRAMING_Pos)

Bit mask of FRAMING field.

◆ UARTE_ERRORSRC_FRAMING_NotPresent

#define UARTE_ERRORSRC_FRAMING_NotPresent   (0UL)

Read: error not present

◆ UARTE_ERRORSRC_FRAMING_Pos

#define UARTE_ERRORSRC_FRAMING_Pos   (2UL)

Position of FRAMING field.

◆ UARTE_ERRORSRC_FRAMING_Present

#define UARTE_ERRORSRC_FRAMING_Present   (1UL)

Read: error present

◆ UARTE_ERRORSRC_OVERRUN_Msk

#define UARTE_ERRORSRC_OVERRUN_Msk   (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos)

Bit mask of OVERRUN field.

◆ UARTE_ERRORSRC_OVERRUN_NotPresent

#define UARTE_ERRORSRC_OVERRUN_NotPresent   (0UL)

Read: error not present

◆ UARTE_ERRORSRC_OVERRUN_Pos

#define UARTE_ERRORSRC_OVERRUN_Pos   (0UL)

Position of OVERRUN field.

◆ UARTE_ERRORSRC_OVERRUN_Present

#define UARTE_ERRORSRC_OVERRUN_Present   (1UL)

Read: error present

◆ UARTE_ERRORSRC_PARITY_Msk

#define UARTE_ERRORSRC_PARITY_Msk   (0x1UL << UARTE_ERRORSRC_PARITY_Pos)

Bit mask of PARITY field.

◆ UARTE_ERRORSRC_PARITY_NotPresent

#define UARTE_ERRORSRC_PARITY_NotPresent   (0UL)

Read: error not present

◆ UARTE_ERRORSRC_PARITY_Pos

#define UARTE_ERRORSRC_PARITY_Pos   (1UL)

Position of PARITY field.

◆ UARTE_ERRORSRC_PARITY_Present

#define UARTE_ERRORSRC_PARITY_Present   (1UL)

Read: error present

◆ UARTE_INTEN_CTS_Disabled

#define UARTE_INTEN_CTS_Disabled   (0UL)

Disable

◆ UARTE_INTEN_CTS_Enabled

#define UARTE_INTEN_CTS_Enabled   (1UL)

Enable

◆ UARTE_INTEN_CTS_Msk

#define UARTE_INTEN_CTS_Msk   (0x1UL << UARTE_INTEN_CTS_Pos)

Bit mask of CTS field.

◆ UARTE_INTEN_CTS_Pos

#define UARTE_INTEN_CTS_Pos   (0UL)

Position of CTS field.

◆ UARTE_INTEN_ENDRX_Disabled

#define UARTE_INTEN_ENDRX_Disabled   (0UL)

Disable

◆ UARTE_INTEN_ENDRX_Enabled

#define UARTE_INTEN_ENDRX_Enabled   (1UL)

Enable

◆ UARTE_INTEN_ENDRX_Msk

#define UARTE_INTEN_ENDRX_Msk   (0x1UL << UARTE_INTEN_ENDRX_Pos)

Bit mask of ENDRX field.

◆ UARTE_INTEN_ENDRX_Pos

#define UARTE_INTEN_ENDRX_Pos   (4UL)

Position of ENDRX field.

◆ UARTE_INTEN_ENDTX_Disabled

#define UARTE_INTEN_ENDTX_Disabled   (0UL)

Disable

◆ UARTE_INTEN_ENDTX_Enabled

#define UARTE_INTEN_ENDTX_Enabled   (1UL)

Enable

◆ UARTE_INTEN_ENDTX_Msk

#define UARTE_INTEN_ENDTX_Msk   (0x1UL << UARTE_INTEN_ENDTX_Pos)

Bit mask of ENDTX field.

◆ UARTE_INTEN_ENDTX_Pos

#define UARTE_INTEN_ENDTX_Pos   (8UL)

Position of ENDTX field.

◆ UARTE_INTEN_ERROR_Disabled

#define UARTE_INTEN_ERROR_Disabled   (0UL)

Disable

◆ UARTE_INTEN_ERROR_Enabled

#define UARTE_INTEN_ERROR_Enabled   (1UL)

Enable

◆ UARTE_INTEN_ERROR_Msk

#define UARTE_INTEN_ERROR_Msk   (0x1UL << UARTE_INTEN_ERROR_Pos)

Bit mask of ERROR field.

◆ UARTE_INTEN_ERROR_Pos

#define UARTE_INTEN_ERROR_Pos   (9UL)

Position of ERROR field.

◆ UARTE_INTEN_NCTS_Disabled

#define UARTE_INTEN_NCTS_Disabled   (0UL)

Disable

◆ UARTE_INTEN_NCTS_Enabled

#define UARTE_INTEN_NCTS_Enabled   (1UL)

Enable

◆ UARTE_INTEN_NCTS_Msk

#define UARTE_INTEN_NCTS_Msk   (0x1UL << UARTE_INTEN_NCTS_Pos)

Bit mask of NCTS field.

◆ UARTE_INTEN_NCTS_Pos

#define UARTE_INTEN_NCTS_Pos   (1UL)

Position of NCTS field.

◆ UARTE_INTEN_RXDRDY_Disabled

#define UARTE_INTEN_RXDRDY_Disabled   (0UL)

Disable

◆ UARTE_INTEN_RXDRDY_Enabled

#define UARTE_INTEN_RXDRDY_Enabled   (1UL)

Enable

◆ UARTE_INTEN_RXDRDY_Msk

#define UARTE_INTEN_RXDRDY_Msk   (0x1UL << UARTE_INTEN_RXDRDY_Pos)

Bit mask of RXDRDY field.

◆ UARTE_INTEN_RXDRDY_Pos

#define UARTE_INTEN_RXDRDY_Pos   (2UL)

Position of RXDRDY field.

◆ UARTE_INTEN_RXSTARTED_Disabled

#define UARTE_INTEN_RXSTARTED_Disabled   (0UL)

Disable

◆ UARTE_INTEN_RXSTARTED_Enabled

#define UARTE_INTEN_RXSTARTED_Enabled   (1UL)

Enable

◆ UARTE_INTEN_RXSTARTED_Msk

#define UARTE_INTEN_RXSTARTED_Msk   (0x1UL << UARTE_INTEN_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ UARTE_INTEN_RXSTARTED_Pos

#define UARTE_INTEN_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ UARTE_INTEN_RXTO_Disabled

#define UARTE_INTEN_RXTO_Disabled   (0UL)

Disable

◆ UARTE_INTEN_RXTO_Enabled

#define UARTE_INTEN_RXTO_Enabled   (1UL)

Enable

◆ UARTE_INTEN_RXTO_Msk

#define UARTE_INTEN_RXTO_Msk   (0x1UL << UARTE_INTEN_RXTO_Pos)

Bit mask of RXTO field.

◆ UARTE_INTEN_RXTO_Pos

#define UARTE_INTEN_RXTO_Pos   (17UL)

Position of RXTO field.

◆ UARTE_INTEN_TXDRDY_Disabled

#define UARTE_INTEN_TXDRDY_Disabled   (0UL)

Disable

◆ UARTE_INTEN_TXDRDY_Enabled

#define UARTE_INTEN_TXDRDY_Enabled   (1UL)

Enable

◆ UARTE_INTEN_TXDRDY_Msk

#define UARTE_INTEN_TXDRDY_Msk   (0x1UL << UARTE_INTEN_TXDRDY_Pos)

Bit mask of TXDRDY field.

◆ UARTE_INTEN_TXDRDY_Pos

#define UARTE_INTEN_TXDRDY_Pos   (7UL)

Position of TXDRDY field.

◆ UARTE_INTEN_TXSTARTED_Disabled

#define UARTE_INTEN_TXSTARTED_Disabled   (0UL)

Disable

◆ UARTE_INTEN_TXSTARTED_Enabled

#define UARTE_INTEN_TXSTARTED_Enabled   (1UL)

Enable

◆ UARTE_INTEN_TXSTARTED_Msk

#define UARTE_INTEN_TXSTARTED_Msk   (0x1UL << UARTE_INTEN_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ UARTE_INTEN_TXSTARTED_Pos

#define UARTE_INTEN_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ UARTE_INTEN_TXSTOPPED_Disabled

#define UARTE_INTEN_TXSTOPPED_Disabled   (0UL)

Disable

◆ UARTE_INTEN_TXSTOPPED_Enabled

#define UARTE_INTEN_TXSTOPPED_Enabled   (1UL)

Enable

◆ UARTE_INTEN_TXSTOPPED_Msk

#define UARTE_INTEN_TXSTOPPED_Msk   (0x1UL << UARTE_INTEN_TXSTOPPED_Pos)

Bit mask of TXSTOPPED field.

◆ UARTE_INTEN_TXSTOPPED_Pos

#define UARTE_INTEN_TXSTOPPED_Pos   (22UL)

Position of TXSTOPPED field.

◆ UARTE_INTENCLR_CTS_Clear

#define UARTE_INTENCLR_CTS_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_CTS_Disabled

#define UARTE_INTENCLR_CTS_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_CTS_Enabled

#define UARTE_INTENCLR_CTS_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_CTS_Msk

#define UARTE_INTENCLR_CTS_Msk   (0x1UL << UARTE_INTENCLR_CTS_Pos)

Bit mask of CTS field.

◆ UARTE_INTENCLR_CTS_Pos

#define UARTE_INTENCLR_CTS_Pos   (0UL)

Position of CTS field.

◆ UARTE_INTENCLR_ENDRX_Clear

#define UARTE_INTENCLR_ENDRX_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_ENDRX_Disabled

#define UARTE_INTENCLR_ENDRX_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_ENDRX_Enabled

#define UARTE_INTENCLR_ENDRX_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_ENDRX_Msk

#define UARTE_INTENCLR_ENDRX_Msk   (0x1UL << UARTE_INTENCLR_ENDRX_Pos)

Bit mask of ENDRX field.

◆ UARTE_INTENCLR_ENDRX_Pos

#define UARTE_INTENCLR_ENDRX_Pos   (4UL)

Position of ENDRX field.

◆ UARTE_INTENCLR_ENDTX_Clear

#define UARTE_INTENCLR_ENDTX_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_ENDTX_Disabled

#define UARTE_INTENCLR_ENDTX_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_ENDTX_Enabled

#define UARTE_INTENCLR_ENDTX_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_ENDTX_Msk

#define UARTE_INTENCLR_ENDTX_Msk   (0x1UL << UARTE_INTENCLR_ENDTX_Pos)

Bit mask of ENDTX field.

◆ UARTE_INTENCLR_ENDTX_Pos

#define UARTE_INTENCLR_ENDTX_Pos   (8UL)

Position of ENDTX field.

◆ UARTE_INTENCLR_ERROR_Clear

#define UARTE_INTENCLR_ERROR_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_ERROR_Disabled

#define UARTE_INTENCLR_ERROR_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_ERROR_Enabled

#define UARTE_INTENCLR_ERROR_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_ERROR_Msk

#define UARTE_INTENCLR_ERROR_Msk   (0x1UL << UARTE_INTENCLR_ERROR_Pos)

Bit mask of ERROR field.

◆ UARTE_INTENCLR_ERROR_Pos

#define UARTE_INTENCLR_ERROR_Pos   (9UL)

Position of ERROR field.

◆ UARTE_INTENCLR_NCTS_Clear

#define UARTE_INTENCLR_NCTS_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_NCTS_Disabled

#define UARTE_INTENCLR_NCTS_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_NCTS_Enabled

#define UARTE_INTENCLR_NCTS_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_NCTS_Msk

#define UARTE_INTENCLR_NCTS_Msk   (0x1UL << UARTE_INTENCLR_NCTS_Pos)

Bit mask of NCTS field.

◆ UARTE_INTENCLR_NCTS_Pos

#define UARTE_INTENCLR_NCTS_Pos   (1UL)

Position of NCTS field.

◆ UARTE_INTENCLR_RXDRDY_Clear

#define UARTE_INTENCLR_RXDRDY_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_RXDRDY_Disabled

#define UARTE_INTENCLR_RXDRDY_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_RXDRDY_Enabled

#define UARTE_INTENCLR_RXDRDY_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_RXDRDY_Msk

#define UARTE_INTENCLR_RXDRDY_Msk   (0x1UL << UARTE_INTENCLR_RXDRDY_Pos)

Bit mask of RXDRDY field.

◆ UARTE_INTENCLR_RXDRDY_Pos

#define UARTE_INTENCLR_RXDRDY_Pos   (2UL)

Position of RXDRDY field.

◆ UARTE_INTENCLR_RXSTARTED_Clear

#define UARTE_INTENCLR_RXSTARTED_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_RXSTARTED_Disabled

#define UARTE_INTENCLR_RXSTARTED_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_RXSTARTED_Enabled

#define UARTE_INTENCLR_RXSTARTED_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_RXSTARTED_Msk

#define UARTE_INTENCLR_RXSTARTED_Msk   (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ UARTE_INTENCLR_RXSTARTED_Pos

#define UARTE_INTENCLR_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ UARTE_INTENCLR_RXTO_Clear

#define UARTE_INTENCLR_RXTO_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_RXTO_Disabled

#define UARTE_INTENCLR_RXTO_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_RXTO_Enabled

#define UARTE_INTENCLR_RXTO_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_RXTO_Msk

#define UARTE_INTENCLR_RXTO_Msk   (0x1UL << UARTE_INTENCLR_RXTO_Pos)

Bit mask of RXTO field.

◆ UARTE_INTENCLR_RXTO_Pos

#define UARTE_INTENCLR_RXTO_Pos   (17UL)

Position of RXTO field.

◆ UARTE_INTENCLR_TXDRDY_Clear

#define UARTE_INTENCLR_TXDRDY_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_TXDRDY_Disabled

#define UARTE_INTENCLR_TXDRDY_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_TXDRDY_Enabled

#define UARTE_INTENCLR_TXDRDY_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_TXDRDY_Msk

#define UARTE_INTENCLR_TXDRDY_Msk   (0x1UL << UARTE_INTENCLR_TXDRDY_Pos)

Bit mask of TXDRDY field.

◆ UARTE_INTENCLR_TXDRDY_Pos

#define UARTE_INTENCLR_TXDRDY_Pos   (7UL)

Position of TXDRDY field.

◆ UARTE_INTENCLR_TXSTARTED_Clear

#define UARTE_INTENCLR_TXSTARTED_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_TXSTARTED_Disabled

#define UARTE_INTENCLR_TXSTARTED_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_TXSTARTED_Enabled

#define UARTE_INTENCLR_TXSTARTED_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_TXSTARTED_Msk

#define UARTE_INTENCLR_TXSTARTED_Msk   (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ UARTE_INTENCLR_TXSTARTED_Pos

#define UARTE_INTENCLR_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ UARTE_INTENCLR_TXSTOPPED_Clear

#define UARTE_INTENCLR_TXSTOPPED_Clear   (1UL)

Disable

◆ UARTE_INTENCLR_TXSTOPPED_Disabled

#define UARTE_INTENCLR_TXSTOPPED_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENCLR_TXSTOPPED_Enabled

#define UARTE_INTENCLR_TXSTOPPED_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENCLR_TXSTOPPED_Msk

#define UARTE_INTENCLR_TXSTOPPED_Msk   (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos)

Bit mask of TXSTOPPED field.

◆ UARTE_INTENCLR_TXSTOPPED_Pos

#define UARTE_INTENCLR_TXSTOPPED_Pos   (22UL)

Position of TXSTOPPED field.

◆ UARTE_INTENSET_CTS_Disabled

#define UARTE_INTENSET_CTS_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_CTS_Enabled

#define UARTE_INTENSET_CTS_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_CTS_Msk

#define UARTE_INTENSET_CTS_Msk   (0x1UL << UARTE_INTENSET_CTS_Pos)

Bit mask of CTS field.

◆ UARTE_INTENSET_CTS_Pos

#define UARTE_INTENSET_CTS_Pos   (0UL)

Position of CTS field.

◆ UARTE_INTENSET_CTS_Set

#define UARTE_INTENSET_CTS_Set   (1UL)

Enable

◆ UARTE_INTENSET_ENDRX_Disabled

#define UARTE_INTENSET_ENDRX_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_ENDRX_Enabled

#define UARTE_INTENSET_ENDRX_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_ENDRX_Msk

#define UARTE_INTENSET_ENDRX_Msk   (0x1UL << UARTE_INTENSET_ENDRX_Pos)

Bit mask of ENDRX field.

◆ UARTE_INTENSET_ENDRX_Pos

#define UARTE_INTENSET_ENDRX_Pos   (4UL)

Position of ENDRX field.

◆ UARTE_INTENSET_ENDRX_Set

#define UARTE_INTENSET_ENDRX_Set   (1UL)

Enable

◆ UARTE_INTENSET_ENDTX_Disabled

#define UARTE_INTENSET_ENDTX_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_ENDTX_Enabled

#define UARTE_INTENSET_ENDTX_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_ENDTX_Msk

#define UARTE_INTENSET_ENDTX_Msk   (0x1UL << UARTE_INTENSET_ENDTX_Pos)

Bit mask of ENDTX field.

◆ UARTE_INTENSET_ENDTX_Pos

#define UARTE_INTENSET_ENDTX_Pos   (8UL)

Position of ENDTX field.

◆ UARTE_INTENSET_ENDTX_Set

#define UARTE_INTENSET_ENDTX_Set   (1UL)

Enable

◆ UARTE_INTENSET_ERROR_Disabled

#define UARTE_INTENSET_ERROR_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_ERROR_Enabled

#define UARTE_INTENSET_ERROR_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_ERROR_Msk

#define UARTE_INTENSET_ERROR_Msk   (0x1UL << UARTE_INTENSET_ERROR_Pos)

Bit mask of ERROR field.

◆ UARTE_INTENSET_ERROR_Pos

#define UARTE_INTENSET_ERROR_Pos   (9UL)

Position of ERROR field.

◆ UARTE_INTENSET_ERROR_Set

#define UARTE_INTENSET_ERROR_Set   (1UL)

Enable

◆ UARTE_INTENSET_NCTS_Disabled

#define UARTE_INTENSET_NCTS_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_NCTS_Enabled

#define UARTE_INTENSET_NCTS_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_NCTS_Msk

#define UARTE_INTENSET_NCTS_Msk   (0x1UL << UARTE_INTENSET_NCTS_Pos)

Bit mask of NCTS field.

◆ UARTE_INTENSET_NCTS_Pos

#define UARTE_INTENSET_NCTS_Pos   (1UL)

Position of NCTS field.

◆ UARTE_INTENSET_NCTS_Set

#define UARTE_INTENSET_NCTS_Set   (1UL)

Enable

◆ UARTE_INTENSET_RXDRDY_Disabled

#define UARTE_INTENSET_RXDRDY_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_RXDRDY_Enabled

#define UARTE_INTENSET_RXDRDY_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_RXDRDY_Msk

#define UARTE_INTENSET_RXDRDY_Msk   (0x1UL << UARTE_INTENSET_RXDRDY_Pos)

Bit mask of RXDRDY field.

◆ UARTE_INTENSET_RXDRDY_Pos

#define UARTE_INTENSET_RXDRDY_Pos   (2UL)

Position of RXDRDY field.

◆ UARTE_INTENSET_RXDRDY_Set

#define UARTE_INTENSET_RXDRDY_Set   (1UL)

Enable

◆ UARTE_INTENSET_RXSTARTED_Disabled

#define UARTE_INTENSET_RXSTARTED_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_RXSTARTED_Enabled

#define UARTE_INTENSET_RXSTARTED_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_RXSTARTED_Msk

#define UARTE_INTENSET_RXSTARTED_Msk   (0x1UL << UARTE_INTENSET_RXSTARTED_Pos)

Bit mask of RXSTARTED field.

◆ UARTE_INTENSET_RXSTARTED_Pos

#define UARTE_INTENSET_RXSTARTED_Pos   (19UL)

Position of RXSTARTED field.

◆ UARTE_INTENSET_RXSTARTED_Set

#define UARTE_INTENSET_RXSTARTED_Set   (1UL)

Enable

◆ UARTE_INTENSET_RXTO_Disabled

#define UARTE_INTENSET_RXTO_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_RXTO_Enabled

#define UARTE_INTENSET_RXTO_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_RXTO_Msk

#define UARTE_INTENSET_RXTO_Msk   (0x1UL << UARTE_INTENSET_RXTO_Pos)

Bit mask of RXTO field.

◆ UARTE_INTENSET_RXTO_Pos

#define UARTE_INTENSET_RXTO_Pos   (17UL)

Position of RXTO field.

◆ UARTE_INTENSET_RXTO_Set

#define UARTE_INTENSET_RXTO_Set   (1UL)

Enable

◆ UARTE_INTENSET_TXDRDY_Disabled

#define UARTE_INTENSET_TXDRDY_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_TXDRDY_Enabled

#define UARTE_INTENSET_TXDRDY_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_TXDRDY_Msk

#define UARTE_INTENSET_TXDRDY_Msk   (0x1UL << UARTE_INTENSET_TXDRDY_Pos)

Bit mask of TXDRDY field.

◆ UARTE_INTENSET_TXDRDY_Pos

#define UARTE_INTENSET_TXDRDY_Pos   (7UL)

Position of TXDRDY field.

◆ UARTE_INTENSET_TXDRDY_Set

#define UARTE_INTENSET_TXDRDY_Set   (1UL)

Enable

◆ UARTE_INTENSET_TXSTARTED_Disabled

#define UARTE_INTENSET_TXSTARTED_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_TXSTARTED_Enabled

#define UARTE_INTENSET_TXSTARTED_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_TXSTARTED_Msk

#define UARTE_INTENSET_TXSTARTED_Msk   (0x1UL << UARTE_INTENSET_TXSTARTED_Pos)

Bit mask of TXSTARTED field.

◆ UARTE_INTENSET_TXSTARTED_Pos

#define UARTE_INTENSET_TXSTARTED_Pos   (20UL)

Position of TXSTARTED field.

◆ UARTE_INTENSET_TXSTARTED_Set

#define UARTE_INTENSET_TXSTARTED_Set   (1UL)

Enable

◆ UARTE_INTENSET_TXSTOPPED_Disabled

#define UARTE_INTENSET_TXSTOPPED_Disabled   (0UL)

Read: Disabled

◆ UARTE_INTENSET_TXSTOPPED_Enabled

#define UARTE_INTENSET_TXSTOPPED_Enabled   (1UL)

Read: Enabled

◆ UARTE_INTENSET_TXSTOPPED_Msk

#define UARTE_INTENSET_TXSTOPPED_Msk   (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos)

Bit mask of TXSTOPPED field.

◆ UARTE_INTENSET_TXSTOPPED_Pos

#define UARTE_INTENSET_TXSTOPPED_Pos   (22UL)

Position of TXSTOPPED field.

◆ UARTE_INTENSET_TXSTOPPED_Set

#define UARTE_INTENSET_TXSTOPPED_Set   (1UL)

Enable

◆ UARTE_PSEL_CTS_CONNECT_Connected

#define UARTE_PSEL_CTS_CONNECT_Connected   (0UL)

Connect

◆ UARTE_PSEL_CTS_CONNECT_Disconnected

#define UARTE_PSEL_CTS_CONNECT_Disconnected   (1UL)

Disconnect

◆ UARTE_PSEL_CTS_CONNECT_Msk

#define UARTE_PSEL_CTS_CONNECT_Msk   (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos)

Bit mask of CONNECT field.

◆ UARTE_PSEL_CTS_CONNECT_Pos

#define UARTE_PSEL_CTS_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ UARTE_PSEL_CTS_PIN_Msk

#define UARTE_PSEL_CTS_PIN_Msk   (0x1FUL << UARTE_PSEL_CTS_PIN_Pos)

Bit mask of PIN field.

◆ UARTE_PSEL_CTS_PIN_Pos

#define UARTE_PSEL_CTS_PIN_Pos   (0UL)

Position of PIN field.

◆ UARTE_PSEL_RTS_CONNECT_Connected

#define UARTE_PSEL_RTS_CONNECT_Connected   (0UL)

Connect

◆ UARTE_PSEL_RTS_CONNECT_Disconnected

#define UARTE_PSEL_RTS_CONNECT_Disconnected   (1UL)

Disconnect

◆ UARTE_PSEL_RTS_CONNECT_Msk

#define UARTE_PSEL_RTS_CONNECT_Msk   (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos)

Bit mask of CONNECT field.

◆ UARTE_PSEL_RTS_CONNECT_Pos

#define UARTE_PSEL_RTS_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ UARTE_PSEL_RTS_PIN_Msk

#define UARTE_PSEL_RTS_PIN_Msk   (0x1FUL << UARTE_PSEL_RTS_PIN_Pos)

Bit mask of PIN field.

◆ UARTE_PSEL_RTS_PIN_Pos

#define UARTE_PSEL_RTS_PIN_Pos   (0UL)

Position of PIN field.

◆ UARTE_PSEL_RXD_CONNECT_Connected

#define UARTE_PSEL_RXD_CONNECT_Connected   (0UL)

Connect

◆ UARTE_PSEL_RXD_CONNECT_Disconnected

#define UARTE_PSEL_RXD_CONNECT_Disconnected   (1UL)

Disconnect

◆ UARTE_PSEL_RXD_CONNECT_Msk

#define UARTE_PSEL_RXD_CONNECT_Msk   (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos)

Bit mask of CONNECT field.

◆ UARTE_PSEL_RXD_CONNECT_Pos

#define UARTE_PSEL_RXD_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ UARTE_PSEL_RXD_PIN_Msk

#define UARTE_PSEL_RXD_PIN_Msk   (0x1FUL << UARTE_PSEL_RXD_PIN_Pos)

Bit mask of PIN field.

◆ UARTE_PSEL_RXD_PIN_Pos

#define UARTE_PSEL_RXD_PIN_Pos   (0UL)

Position of PIN field.

◆ UARTE_PSEL_TXD_CONNECT_Connected

#define UARTE_PSEL_TXD_CONNECT_Connected   (0UL)

Connect

◆ UARTE_PSEL_TXD_CONNECT_Disconnected

#define UARTE_PSEL_TXD_CONNECT_Disconnected   (1UL)

Disconnect

◆ UARTE_PSEL_TXD_CONNECT_Msk

#define UARTE_PSEL_TXD_CONNECT_Msk   (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos)

Bit mask of CONNECT field.

◆ UARTE_PSEL_TXD_CONNECT_Pos

#define UARTE_PSEL_TXD_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ UARTE_PSEL_TXD_PIN_Msk

#define UARTE_PSEL_TXD_PIN_Msk   (0x1FUL << UARTE_PSEL_TXD_PIN_Pos)

Bit mask of PIN field.

◆ UARTE_PSEL_TXD_PIN_Pos

#define UARTE_PSEL_TXD_PIN_Pos   (0UL)

Position of PIN field.

◆ UARTE_RXD_AMOUNT_AMOUNT_Msk

#define UARTE_RXD_AMOUNT_AMOUNT_Msk   (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ UARTE_RXD_AMOUNT_AMOUNT_Pos

#define UARTE_RXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ UARTE_RXD_MAXCNT_MAXCNT_Msk

#define UARTE_RXD_MAXCNT_MAXCNT_Msk   (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ UARTE_RXD_MAXCNT_MAXCNT_Pos

#define UARTE_RXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ UARTE_RXD_PTR_PTR_Msk

#define UARTE_RXD_PTR_PTR_Msk   (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ UARTE_RXD_PTR_PTR_Pos

#define UARTE_RXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ UARTE_SHORTS_ENDRX_STARTRX_Disabled

#define UARTE_SHORTS_ENDRX_STARTRX_Disabled   (0UL)

Disable shortcut

◆ UARTE_SHORTS_ENDRX_STARTRX_Enabled

#define UARTE_SHORTS_ENDRX_STARTRX_Enabled   (1UL)

Enable shortcut

◆ UARTE_SHORTS_ENDRX_STARTRX_Msk

#define UARTE_SHORTS_ENDRX_STARTRX_Msk   (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos)

Bit mask of ENDRX_STARTRX field.

◆ UARTE_SHORTS_ENDRX_STARTRX_Pos

#define UARTE_SHORTS_ENDRX_STARTRX_Pos   (5UL)

Position of ENDRX_STARTRX field.

◆ UARTE_SHORTS_ENDRX_STOPRX_Disabled

#define UARTE_SHORTS_ENDRX_STOPRX_Disabled   (0UL)

Disable shortcut

◆ UARTE_SHORTS_ENDRX_STOPRX_Enabled

#define UARTE_SHORTS_ENDRX_STOPRX_Enabled   (1UL)

Enable shortcut

◆ UARTE_SHORTS_ENDRX_STOPRX_Msk

#define UARTE_SHORTS_ENDRX_STOPRX_Msk   (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos)

Bit mask of ENDRX_STOPRX field.

◆ UARTE_SHORTS_ENDRX_STOPRX_Pos

#define UARTE_SHORTS_ENDRX_STOPRX_Pos   (6UL)

Position of ENDRX_STOPRX field.

◆ UARTE_TXD_AMOUNT_AMOUNT_Msk

#define UARTE_TXD_AMOUNT_AMOUNT_Msk   (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos)

Bit mask of AMOUNT field.

◆ UARTE_TXD_AMOUNT_AMOUNT_Pos

#define UARTE_TXD_AMOUNT_AMOUNT_Pos   (0UL)

Position of AMOUNT field.

◆ UARTE_TXD_MAXCNT_MAXCNT_Msk

#define UARTE_TXD_MAXCNT_MAXCNT_Msk   (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos)

Bit mask of MAXCNT field.

◆ UARTE_TXD_MAXCNT_MAXCNT_Pos

#define UARTE_TXD_MAXCNT_MAXCNT_Pos   (0UL)

Position of MAXCNT field.

◆ UARTE_TXD_PTR_PTR_Msk

#define UARTE_TXD_PTR_PTR_Msk   (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos)

Bit mask of PTR field.

◆ UARTE_TXD_PTR_PTR_Pos

#define UARTE_TXD_PTR_PTR_Pos   (0UL)

Position of PTR field.

◆ UICR_APPROTECT_PALL_Disabled

#define UICR_APPROTECT_PALL_Disabled   (0xFFUL)

Disable

◆ UICR_APPROTECT_PALL_Enabled

#define UICR_APPROTECT_PALL_Enabled   (0x00UL)

Enable

◆ UICR_APPROTECT_PALL_Msk

#define UICR_APPROTECT_PALL_Msk   (0xFFUL << UICR_APPROTECT_PALL_Pos)

Bit mask of PALL field.

◆ UICR_APPROTECT_PALL_Pos

#define UICR_APPROTECT_PALL_Pos   (0UL)

Position of PALL field.

◆ UICR_CUSTOMER_CUSTOMER_Msk

#define UICR_CUSTOMER_CUSTOMER_Msk   (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos)

Bit mask of CUSTOMER field.

◆ UICR_CUSTOMER_CUSTOMER_Pos

#define UICR_CUSTOMER_CUSTOMER_Pos   (0UL)

Position of CUSTOMER field.

◆ UICR_NFCPINS_PROTECT_Disabled

#define UICR_NFCPINS_PROTECT_Disabled   (0UL)

Operation as GPIO pins. Same protection as normal GPIO pins

◆ UICR_NFCPINS_PROTECT_Msk

#define UICR_NFCPINS_PROTECT_Msk   (0x1UL << UICR_NFCPINS_PROTECT_Pos)

Bit mask of PROTECT field.

◆ UICR_NFCPINS_PROTECT_NFC

#define UICR_NFCPINS_PROTECT_NFC   (1UL)

Operation as NFC antenna pins. Configures the protection for NFC operation

◆ UICR_NFCPINS_PROTECT_Pos

#define UICR_NFCPINS_PROTECT_Pos   (0UL)

Position of PROTECT field.

◆ UICR_NRFFW_NRFFW_Msk

#define UICR_NRFFW_NRFFW_Msk   (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos)

Bit mask of NRFFW field.

◆ UICR_NRFFW_NRFFW_Pos

#define UICR_NRFFW_NRFFW_Pos   (0UL)

Position of NRFFW field.

◆ UICR_NRFHW_NRFHW_Msk

#define UICR_NRFHW_NRFHW_Msk   (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos)

Bit mask of NRFHW field.

◆ UICR_NRFHW_NRFHW_Pos

#define UICR_NRFHW_NRFHW_Pos   (0UL)

Position of NRFHW field.

◆ UICR_PSELRESET_CONNECT_Connected

#define UICR_PSELRESET_CONNECT_Connected   (0UL)

Connect

◆ UICR_PSELRESET_CONNECT_Disconnected

#define UICR_PSELRESET_CONNECT_Disconnected   (1UL)

Disconnect

◆ UICR_PSELRESET_CONNECT_Msk

#define UICR_PSELRESET_CONNECT_Msk   (0x1UL << UICR_PSELRESET_CONNECT_Pos)

Bit mask of CONNECT field.

◆ UICR_PSELRESET_CONNECT_Pos

#define UICR_PSELRESET_CONNECT_Pos   (31UL)

Position of CONNECT field.

◆ UICR_PSELRESET_PIN_Msk

#define UICR_PSELRESET_PIN_Msk   (0x3FUL << UICR_PSELRESET_PIN_Pos)

Bit mask of PIN field.

◆ UICR_PSELRESET_PIN_Pos

#define UICR_PSELRESET_PIN_Pos   (0UL)

Position of PIN field.

◆ WDT_CONFIG_HALT_Msk

#define WDT_CONFIG_HALT_Msk   (0x1UL << WDT_CONFIG_HALT_Pos)

Bit mask of HALT field.

◆ WDT_CONFIG_HALT_Pause

#define WDT_CONFIG_HALT_Pause   (0UL)

Pause watchdog while the CPU is halted by the debugger

◆ WDT_CONFIG_HALT_Pos

#define WDT_CONFIG_HALT_Pos   (3UL)

Position of HALT field.

◆ WDT_CONFIG_HALT_Run

#define WDT_CONFIG_HALT_Run   (1UL)

Keep the watchdog running while the CPU is halted by the debugger

◆ WDT_CONFIG_SLEEP_Msk

#define WDT_CONFIG_SLEEP_Msk   (0x1UL << WDT_CONFIG_SLEEP_Pos)

Bit mask of SLEEP field.

◆ WDT_CONFIG_SLEEP_Pause

#define WDT_CONFIG_SLEEP_Pause   (0UL)

Pause watchdog while the CPU is sleeping

◆ WDT_CONFIG_SLEEP_Pos

#define WDT_CONFIG_SLEEP_Pos   (0UL)

Position of SLEEP field.

◆ WDT_CONFIG_SLEEP_Run

#define WDT_CONFIG_SLEEP_Run   (1UL)

Keep the watchdog running while the CPU is sleeping

◆ WDT_CRV_CRV_Msk

#define WDT_CRV_CRV_Msk   (0xFFFFFFFFUL << WDT_CRV_CRV_Pos)

Bit mask of CRV field.

◆ WDT_CRV_CRV_Pos

#define WDT_CRV_CRV_Pos   (0UL)

Position of CRV field.

◆ WDT_INTENCLR_TIMEOUT_Clear

#define WDT_INTENCLR_TIMEOUT_Clear   (1UL)

Disable

◆ WDT_INTENCLR_TIMEOUT_Disabled

#define WDT_INTENCLR_TIMEOUT_Disabled   (0UL)

Read: Disabled

◆ WDT_INTENCLR_TIMEOUT_Enabled

#define WDT_INTENCLR_TIMEOUT_Enabled   (1UL)

Read: Enabled

◆ WDT_INTENCLR_TIMEOUT_Msk

#define WDT_INTENCLR_TIMEOUT_Msk   (0x1UL << WDT_INTENCLR_TIMEOUT_Pos)

Bit mask of TIMEOUT field.

◆ WDT_INTENCLR_TIMEOUT_Pos

#define WDT_INTENCLR_TIMEOUT_Pos   (0UL)

Position of TIMEOUT field.

◆ WDT_INTENSET_TIMEOUT_Disabled

#define WDT_INTENSET_TIMEOUT_Disabled   (0UL)

Read: Disabled

◆ WDT_INTENSET_TIMEOUT_Enabled

#define WDT_INTENSET_TIMEOUT_Enabled   (1UL)

Read: Enabled

◆ WDT_INTENSET_TIMEOUT_Msk

#define WDT_INTENSET_TIMEOUT_Msk   (0x1UL << WDT_INTENSET_TIMEOUT_Pos)

Bit mask of TIMEOUT field.

◆ WDT_INTENSET_TIMEOUT_Pos

#define WDT_INTENSET_TIMEOUT_Pos   (0UL)

Position of TIMEOUT field.

◆ WDT_INTENSET_TIMEOUT_Set

#define WDT_INTENSET_TIMEOUT_Set   (1UL)

Enable

◆ WDT_REQSTATUS_RR0_DisabledOrRequested

#define WDT_REQSTATUS_RR0_DisabledOrRequested   (0UL)

RR[0] register is not enabled, or are already requesting reload

◆ WDT_REQSTATUS_RR0_EnabledAndUnrequested

#define WDT_REQSTATUS_RR0_EnabledAndUnrequested   (1UL)

RR[0] register is enabled, and are not yet requesting reload

◆ WDT_REQSTATUS_RR0_Msk

#define WDT_REQSTATUS_RR0_Msk   (0x1UL << WDT_REQSTATUS_RR0_Pos)

Bit mask of RR0 field.

◆ WDT_REQSTATUS_RR0_Pos

#define WDT_REQSTATUS_RR0_Pos   (0UL)

Position of RR0 field.

◆ WDT_REQSTATUS_RR1_DisabledOrRequested

#define WDT_REQSTATUS_RR1_DisabledOrRequested   (0UL)

RR[1] register is not enabled, or are already requesting reload

◆ WDT_REQSTATUS_RR1_EnabledAndUnrequested

#define WDT_REQSTATUS_RR1_EnabledAndUnrequested   (1UL)

RR[1] register is enabled, and are not yet requesting reload

◆ WDT_REQSTATUS_RR1_Msk

#define WDT_REQSTATUS_RR1_Msk   (0x1UL << WDT_REQSTATUS_RR1_Pos)

Bit mask of RR1 field.

◆ WDT_REQSTATUS_RR1_Pos

#define WDT_REQSTATUS_RR1_Pos   (1UL)

Position of RR1 field.

◆ WDT_REQSTATUS_RR2_DisabledOrRequested

#define WDT_REQSTATUS_RR2_DisabledOrRequested   (0UL)

RR[2] register is not enabled, or are already requesting reload

◆ WDT_REQSTATUS_RR2_EnabledAndUnrequested

#define WDT_REQSTATUS_RR2_EnabledAndUnrequested   (1UL)

RR[2] register is enabled, and are not yet requesting reload

◆ WDT_REQSTATUS_RR2_Msk

#define WDT_REQSTATUS_RR2_Msk   (0x1UL << WDT_REQSTATUS_RR2_Pos)

Bit mask of RR2 field.

◆ WDT_REQSTATUS_RR2_Pos

#define WDT_REQSTATUS_RR2_Pos   (2UL)

Position of RR2 field.

◆ WDT_REQSTATUS_RR3_DisabledOrRequested

#define WDT_REQSTATUS_RR3_DisabledOrRequested   (0UL)

RR[3] register is not enabled, or are already requesting reload

◆ WDT_REQSTATUS_RR3_EnabledAndUnrequested

#define WDT_REQSTATUS_RR3_EnabledAndUnrequested   (1UL)

RR[3] register is enabled, and are not yet requesting reload

◆ WDT_REQSTATUS_RR3_Msk

#define WDT_REQSTATUS_RR3_Msk   (0x1UL << WDT_REQSTATUS_RR3_Pos)

Bit mask of RR3 field.

◆ WDT_REQSTATUS_RR3_Pos

#define WDT_REQSTATUS_RR3_Pos   (3UL)

Position of RR3 field.

◆ WDT_REQSTATUS_RR4_DisabledOrRequested

#define WDT_REQSTATUS_RR4_DisabledOrRequested   (0UL)

RR[4] register is not enabled, or are already requesting reload

◆ WDT_REQSTATUS_RR4_EnabledAndUnrequested

#define WDT_REQSTATUS_RR4_EnabledAndUnrequested   (1UL)

RR[4] register is enabled, and are not yet requesting reload

◆ WDT_REQSTATUS_RR4_Msk

#define WDT_REQSTATUS_RR4_Msk   (0x1UL << WDT_REQSTATUS_RR4_Pos)

Bit mask of RR4 field.

◆ WDT_REQSTATUS_RR4_Pos

#define WDT_REQSTATUS_RR4_Pos   (4UL)

Position of RR4 field.

◆ WDT_REQSTATUS_RR5_DisabledOrRequested

#define WDT_REQSTATUS_RR5_DisabledOrRequested   (0UL)

RR[5] register is not enabled, or are already requesting reload

◆ WDT_REQSTATUS_RR5_EnabledAndUnrequested

#define WDT_REQSTATUS_RR5_EnabledAndUnrequested   (1UL)

RR[5] register is enabled, and are not yet requesting reload

◆ WDT_REQSTATUS_RR5_Msk

#define WDT_REQSTATUS_RR5_Msk   (0x1UL << WDT_REQSTATUS_RR5_Pos)

Bit mask of RR5 field.

◆ WDT_REQSTATUS_RR5_Pos

#define WDT_REQSTATUS_RR5_Pos   (5UL)

Position of RR5 field.

◆ WDT_REQSTATUS_RR6_DisabledOrRequested

#define WDT_REQSTATUS_RR6_DisabledOrRequested   (0UL)

RR[6] register is not enabled, or are already requesting reload

◆ WDT_REQSTATUS_RR6_EnabledAndUnrequested

#define WDT_REQSTATUS_RR6_EnabledAndUnrequested   (1UL)

RR[6] register is enabled, and are not yet requesting reload

◆ WDT_REQSTATUS_RR6_Msk

#define WDT_REQSTATUS_RR6_Msk   (0x1UL << WDT_REQSTATUS_RR6_Pos)

Bit mask of RR6 field.

◆ WDT_REQSTATUS_RR6_Pos

#define WDT_REQSTATUS_RR6_Pos   (6UL)

Position of RR6 field.

◆ WDT_REQSTATUS_RR7_DisabledOrRequested

#define WDT_REQSTATUS_RR7_DisabledOrRequested   (0UL)

RR[7] register is not enabled, or are already requesting reload

◆ WDT_REQSTATUS_RR7_EnabledAndUnrequested

#define WDT_REQSTATUS_RR7_EnabledAndUnrequested   (1UL)

RR[7] register is enabled, and are not yet requesting reload

◆ WDT_REQSTATUS_RR7_Msk

#define WDT_REQSTATUS_RR7_Msk   (0x1UL << WDT_REQSTATUS_RR7_Pos)

Bit mask of RR7 field.

◆ WDT_REQSTATUS_RR7_Pos

#define WDT_REQSTATUS_RR7_Pos   (7UL)

Position of RR7 field.

◆ WDT_RR_RR_Msk

#define WDT_RR_RR_Msk   (0xFFFFFFFFUL << WDT_RR_RR_Pos)

Bit mask of RR field.

◆ WDT_RR_RR_Pos

#define WDT_RR_RR_Pos   (0UL)

Position of RR field.

◆ WDT_RR_RR_Reload

#define WDT_RR_RR_Reload   (0x6E524635UL)

Value to request a reload of the watchdog timer

◆ WDT_RREN_RR0_Disabled

#define WDT_RREN_RR0_Disabled   (0UL)

Disable RR[0] register

◆ WDT_RREN_RR0_Enabled

#define WDT_RREN_RR0_Enabled   (1UL)

Enable RR[0] register

◆ WDT_RREN_RR0_Msk

#define WDT_RREN_RR0_Msk   (0x1UL << WDT_RREN_RR0_Pos)

Bit mask of RR0 field.

◆ WDT_RREN_RR0_Pos

#define WDT_RREN_RR0_Pos   (0UL)

Position of RR0 field.

◆ WDT_RREN_RR1_Disabled

#define WDT_RREN_RR1_Disabled   (0UL)

Disable RR[1] register

◆ WDT_RREN_RR1_Enabled

#define WDT_RREN_RR1_Enabled   (1UL)

Enable RR[1] register

◆ WDT_RREN_RR1_Msk

#define WDT_RREN_RR1_Msk   (0x1UL << WDT_RREN_RR1_Pos)

Bit mask of RR1 field.

◆ WDT_RREN_RR1_Pos

#define WDT_RREN_RR1_Pos   (1UL)

Position of RR1 field.

◆ WDT_RREN_RR2_Disabled

#define WDT_RREN_RR2_Disabled   (0UL)

Disable RR[2] register

◆ WDT_RREN_RR2_Enabled

#define WDT_RREN_RR2_Enabled   (1UL)

Enable RR[2] register

◆ WDT_RREN_RR2_Msk

#define WDT_RREN_RR2_Msk   (0x1UL << WDT_RREN_RR2_Pos)

Bit mask of RR2 field.

◆ WDT_RREN_RR2_Pos

#define WDT_RREN_RR2_Pos   (2UL)

Position of RR2 field.

◆ WDT_RREN_RR3_Disabled

#define WDT_RREN_RR3_Disabled   (0UL)

Disable RR[3] register

◆ WDT_RREN_RR3_Enabled

#define WDT_RREN_RR3_Enabled   (1UL)

Enable RR[3] register

◆ WDT_RREN_RR3_Msk

#define WDT_RREN_RR3_Msk   (0x1UL << WDT_RREN_RR3_Pos)

Bit mask of RR3 field.

◆ WDT_RREN_RR3_Pos

#define WDT_RREN_RR3_Pos   (3UL)

Position of RR3 field.

◆ WDT_RREN_RR4_Disabled

#define WDT_RREN_RR4_Disabled   (0UL)

Disable RR[4] register

◆ WDT_RREN_RR4_Enabled

#define WDT_RREN_RR4_Enabled   (1UL)

Enable RR[4] register

◆ WDT_RREN_RR4_Msk

#define WDT_RREN_RR4_Msk   (0x1UL << WDT_RREN_RR4_Pos)

Bit mask of RR4 field.

◆ WDT_RREN_RR4_Pos

#define WDT_RREN_RR4_Pos   (4UL)

Position of RR4 field.

◆ WDT_RREN_RR5_Disabled

#define WDT_RREN_RR5_Disabled   (0UL)

Disable RR[5] register

◆ WDT_RREN_RR5_Enabled

#define WDT_RREN_RR5_Enabled   (1UL)

Enable RR[5] register

◆ WDT_RREN_RR5_Msk

#define WDT_RREN_RR5_Msk   (0x1UL << WDT_RREN_RR5_Pos)

Bit mask of RR5 field.

◆ WDT_RREN_RR5_Pos

#define WDT_RREN_RR5_Pos   (5UL)

Position of RR5 field.

◆ WDT_RREN_RR6_Disabled

#define WDT_RREN_RR6_Disabled   (0UL)

Disable RR[6] register

◆ WDT_RREN_RR6_Enabled

#define WDT_RREN_RR6_Enabled   (1UL)

Enable RR[6] register

◆ WDT_RREN_RR6_Msk

#define WDT_RREN_RR6_Msk   (0x1UL << WDT_RREN_RR6_Pos)

Bit mask of RR6 field.

◆ WDT_RREN_RR6_Pos

#define WDT_RREN_RR6_Pos   (6UL)

Position of RR6 field.

◆ WDT_RREN_RR7_Disabled

#define WDT_RREN_RR7_Disabled   (0UL)

Disable RR[7] register

◆ WDT_RREN_RR7_Enabled

#define WDT_RREN_RR7_Enabled   (1UL)

Enable RR[7] register

◆ WDT_RREN_RR7_Msk

#define WDT_RREN_RR7_Msk   (0x1UL << WDT_RREN_RR7_Pos)

Bit mask of RR7 field.

◆ WDT_RREN_RR7_Pos

#define WDT_RREN_RR7_Pos   (7UL)

Position of RR7 field.

◆ WDT_RUNSTATUS_RUNSTATUS_Msk

#define WDT_RUNSTATUS_RUNSTATUS_Msk   (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos)

Bit mask of RUNSTATUS field.

◆ WDT_RUNSTATUS_RUNSTATUS_NotRunning

#define WDT_RUNSTATUS_RUNSTATUS_NotRunning   (0UL)

Watchdog not running

◆ WDT_RUNSTATUS_RUNSTATUS_Pos

#define WDT_RUNSTATUS_RUNSTATUS_Pos   (0UL)

Position of RUNSTATUS field.

◆ WDT_RUNSTATUS_RUNSTATUS_Running

#define WDT_RUNSTATUS_RUNSTATUS_Running   (1UL)

Watchdog is running